MITSUBISHI LSIs MITSUBISHI LSIs M5M28F101AFP,J,VP,RV-85,-10 M5M28F101AFP,J,VP,RV-85,-10 1048576-BIT 1048576-BIT (131072-WORD (131072-WORD BY BY 8-BIT) 8-BIT) CMOS CMOS FLASH FLASH MEMORY MEMORY ADDRESS INPUTS DATA INPUTS/ OUTPUTS 1 32 2 31 3 30 4 29 5 28 6 7 8 9 10 27 26 25 24 23 11 22 12 21 13 20 14 19 15 18 16 17 VCC ENABLE WE WRITE INPUT NC A14 A13 A8 ADDRESS INPUTS A9 A11 OE OUTPUT ENABLE INPUT A10 ADDRESS INPUT ENABLE CE CHIP INPUT D7 D6 D5 D4 D3 DATA INPUTS/ OUTPUTS Outline 525mil 32pin SOP (32P2M-A) 30 5 29 6 28 7 27 8 26 9 25 M5M28F101AJ 20 A14 A13 A8 A9 A11 OE A10 CE D7 D1 D2 GND D3 D4 D5 D6 19 21 18 22 13 17 23 12 16 24 11 14 10 15 A7 A6 A5 A4 A3 A2 A1 A0 D0 Micro-computer system and peripheral equipment 31 1 APPLICATION 32 2 4 Speed item ........................................................ 85 ns (max.) Speed item .......................................................100 ns (max.) ................................... VCC = 5V±0.5V Power supply voltage ................................... Write and erase voltage ................................ ................................ VPP = 12V±0.6V Byte program and Chip erase Auto program and Auto erase Program/erase operation controlled by software command Program/erase pulse controlled by an embedded timer 10000 program/erase cycles Tri-state output buffer TTL-compatible input and output in read and write mode Contained device-identifier code Incorporated data-protection Available packaging for Surface Mount VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND M5M28F101AFP FEATURES PIN CONFIGURATION (TOP VIEW) A12 A15 A16 VPP VCC WE NC The MITSUBISHI M5M28F101A is high-speed 1048576-bit CMOS Flash Memories. This is suitable for the applications with microprocessor or micro-controller where on-board reprogramming is required. The M5M28F101A is fabricated by N-channel double polysilicon gate for memory and CMOS technology for peripheral circuits, and is available in 32pin plastic molded packages. 3 DESCRIPTION Outline 32pin PLCC (32P0) A11 A9 A8 A13 A14 NC WE VCC VPP A16 A15 A12 A7 A6 A5 A4 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 9 M5M28F101AVP 25 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 Outline 32pin TSOP type-I (8x20mm) 32P3H-E (normal bend) OE A10 CE D7 D6 D5 D4 D3 GND D2 D1 D0 A0 A1 A2 A3 A4 A5 A6 A7 A12 A15 A16 VPP VCC WE NC A14 A13 A8 A9 A11 16 17 15 18 14 19 13 20 12 21 11 22 10 9 8 23 M5M28F101ARV 24 25 7 26 6 27 5 28 4 29 3 30 2 31 1 32 A3 A2 A1 A0 D0 D1 D2 GND D3 D4 D5 D6 D7 CE A10 OE Outline 32pin TSOP type-I (8x20mm) 32P3H-F (reverse bend) NC : NO CONNECTION 1 (970407) MITSUBISHI LSIs M5M28F101AFP,J,VP,RV-85,-10 1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY BLOCK DIAGRAM A9 A8 PROGRAM VOLTAGE SW. ERASE VOLTAGE SW. VCC (5V) A7 GND (0V) A6 A5 A4 VPP (5V, 12V) X-DECODER 131072 WORD x8 BIT CELL MATRIX Y-DECODER Y-GATE CHIP ENABLE OUTPUT ENABLE CIRCUITS OUTPUT SENSE AND OUTPUT BUFFERS A3 ADDRESS INPUTS A2 A1 A0 A16 A15 A14 A13 A12 A11 A10 CHIP ENABLE INPUT CE VERIFY VOLTAGE SW. TIMER CONTROL CIRCUITS COMMAND LATCH OUTPUT ENABLE INPUT OE WRITE ENABLE WE INPUT D0 D1 D2 D3 D4 D5 D6 D7 DATA INPUTS/OUTPUTS FUNCTION DATA PROTECTION M5M28F101A are set to the Read-only mode or Read-write mode by applying the voltage of V PPL or V PPH, respectively, to V PP pin. In Read-only mode, three operation modes, Read, Out-put disable and Stand-by are accessible. While, in Read-Write mode, four operation modes, Read, Output disable, Stand-by and Write are functional. 1. Read Set CE and OE terminals to the read mode (low level). Low level input to CE and OE, and address signals to the address inputs (A0~A16) make the data contents of the designated address location available at data input/output(D0~D7). Output Disable When OE is at high level, output from the devices is disabled. Data input/output are in a high-impedance (High-Z) state. 2. 3. Power Supply Voltage When the power supply voltage (Vcc) is less than 2.5V, the device ignores WE signal. Write Inhibit In the cases, as below, write mode is not set. 1) When OE is terminated to the low level. 2) From each mode beginning through finish after 2nd rising edge of WE for program, auto-program, erase, and autoerase. Over-erase Protection Just after powering up, if erase command is inputted, erase operation is not executed. Once byte-program is performed or verified data is not FFH in the erase-verify mode, successive command input for erase will be accepted. Because of this, it is applicable to the case of multi-chip erasing simultaneously. Stand-by When CE is at high level, the devices is in the stand-by mode and its power consumption is substantially reduced. Data input/output are in a high-impedance (High-Z) state. Write Software command accomplishes program and erase operations via the command latch in the device, when high voltage is supplied to VPP. The contents of the latch serve as input to the internal controller. The controller output dictates the function of device. The command latch is written by bringing WE to low level, while CE is at low level and OE is at high level. Addresses are latched on the falling edge of WE, while data is latched on the rising edge of WE. Standard micro-processor write timings are used. 2 (970407) MITSUBISHI LSIs M5M28F101AFP,J,VP,RV-85,-10 1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY SOFTWARE COMMAND When V PP is low (VPP = V PPL), the contents of the command latch are fixed to 00H, and the device is in read-only mode. When VPP is high (V PP = VPPH), the device enters read/write mode. The device operations are selected by writing specific software command into the command latch. Read Command The device is in read mode after writing Read Command (00H) to the command latch. The device continues to be in read mode until the other commands are written. When VPP powers-up to high voltage (VPP = V PPH), the default contents of the command latch is 00H. So it is ensured that the false alteration of memory data does not occur during VPP power transition. Program Command Program Command is the command for byte-program, and program is initiated by twice of write cycles. Program Command (40H) is written to the command latch in first write cycle, and the address and data to be programmed are latched in second write cycle. Then the address and data are latched on the falling edge and the rising edge of WE pulse, respectively. The byte- program operation is initiated at the rising edge of WE in second write cycle, and terminates in 10 µs, controlled by the internal timer. Program Verify Command Following byte program, the programmed byte must be verified. The program-verify is initiated by writing Program Verify Command (C0H) to the command latch. After writing Program Verify Command, programmed data is verified in read mode. Then the address information is not needed. Auto Program Command Auto Program Command is the command for automated program and program-verify of one byte, and Auto Program is initiated by twice of write cycles. Auto Program Command (10H or 50H) is written to the command latch in first write cycle, and the address and data to be programmed are latched in second write cycle. Then the address and data are latched on the falling edge and the rising edge of WE pulse, respectively. The program operation is initiated at the rising edge of WE in second write cycle, and program-verify begin automatically. So it is not necessary to program-verify mode after this. And the complete of Auto Program can be indicated by data polling. Data polling is the indication of the complete of Auto Program. During the Auto Program, on WE=V IH and CE=OE=VIL , the data of D0~D7 are the inverse of written datum. When Auto Program is completed, the written datum will be output. It is necessary to fix the address of written byte during data polling. Erase Verify Command Following each erase, all bytes must be verified. The erase verify is initiated by writing Erase Verify Command (A0H) to the command latch, while the address to be verified is latched on the falling edge of the WE pulse. The erase verify command must be written to the command latch and each address is latched before each byte is verified. The operation continues for each byte until a byte is not erased, or the last address is accessed. Auto Erase Command Auto Erase Command is the command for automated erase and erase-verify of all bytes, and Auto Erase is initiated by twice of the Erase Command (30H) consecutively to the command latch. First, the preprogram operation is initiated at the rising edge of WE in second write cycle, and so all byte become zero data. Second, erase and erase-verify begin, automatically. So it is not necessary to preprogram and erase-verify mode. And the complete of Auto Erase can be indicated by status polling. Status polling is the indication of the complete of Auto Erase. During the Auto Erase, on WE=VIH and CE=OE=VIL , the data of D7 is "0". When Auto Erase is completed, the data of D7 is "1". (D0~D7 are "FFH". ) Reset Command Reset Command is the command to safely abort the erase or program sequences. Following erase or program command in first write cycle, the operation is aborted safely by writing the two consecutive Reset Commands (FFH). Then the device enters read mode without altering memory contents. Read Device Identifier Code Device Identifier operation is initiated by writing 80H into the command latch. Following the command write, the manufacturer code (1CH) and the device code (D9H) can be read from address00000H and 00001H, respectively. The M5M28F101A is supported with the Common Device Identifier Code of MITSUBISHI 1M Flash memory (x8) family. Common Device Identifier operation is initiated by writing 90H into the command latch. Under this case, following the command write, the manufacturer code (1CH) and the device code (D0H) can be read from address-00000H and 00001H, respectively. Additionally, Common Device Identifier operation is initiated by rising A9 to high voltage for PROM programmers. Erase Command Erase Command is the command for chip-erase, and chip-erase is initiated by writing twice of the Erase Command (20H) consecutively to the command latch. The erase operation is initiated with the rising edge of the WE pulse and terminates in 9.5ms, controlled by the internal timer. This two-step sequence for chip-erase prevents from erasing accidentally. 3 (970407) MITSUBISHI LSIs M5M28F101AFP,J,VP,RV-85,-10 1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY MODE SELECTION Pins CE OE WE VPP Data I/O Read Output disable Stand by Read Output disable Stand by Write VIL VIL VIH VIL VIL VIH VIL VIL VIH X VIL VIH X VIH VIH VIH X VIH VIH X VIL VPPL VPPL VPPL VPPH VPPH VPPH VPPH Data out Hi-Z Hi-Z Data out Hi-Z Hi-Z Data out Mode Read-Only Read/Write Note 1 : X can be VIL or VIH ABSOLUTE MAXIMUM RATINGS Symbol VI1 VI2 VI3 Topr Tstg Parameter All input or output voltage except VPP/A9 VPP supply voltage A9 supply voltage Operating temperature Storage temperature Ratings –0.6~7 –0.6~14.0 –0.6~13.5 –10~80 –65~125 Conditions With respect to Ground Unit V V V °C °C SOFTWARE COMMAND DEFINITION Mode Write First bus cycle Address X Data I/O 00H Mode ––– Write X 40H Write Write X C0H Read Auto Program Write X 10H or 50H Write Erase (Chip Erase) Erase verify Auto Erase Reset Read device identifier code Read common device identifier code Write Write Write Write Write Write X Verify address X X X X 20H A0H 30H FFH 80H 90H Write Read Write Write Read Read Command Read Program (Byte Program) Program verify Second bus cycle Address Data I/O ––– ––– Program Program Data Address X Program Address Verify Data Program Data X X X X ADI ADI 20H Verify Data 30H FFH DDI1 DDI2 Note 2 : Write and read mode are defined in mode selection table. ADI = Address of Device Identifier : 00000H for manufacturer code, 00001H for device code. DDI1 = Data of Device Identifier : 1CH for manufacturer code, D9H for device code. DDI2 = Data of Common Device Identifier : 1CH for manufacturer code, D0H for device code. COMMON DEVICE IDENTIFIER CODE (not use the software command) Pins Code Manufacturer Code Device Code A0 D7 D6 D5 D4 D3 D2 D1 D0 VIL VIH 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 0 Hex. Data 1CH D0H Note 3 : A9 = 11.5V~13.0V A1~A8, A10~A16, CE, OE = VIL, WE = VIH VCC = VPP = 5V±0.5V CAPACITANCE Symbol CIN COUT 4 Parameter Input capacitance (Address, CE, OE, WE) Output capacitance Test conditions Ta = 25°C, f = 1MHz, Vin = Vout = 0V Min Limits Typ Max 8 12 Unit pF pF (970407) MITSUBISHI LSIs M5M28F101AFP,J,VP,RV-85,-10 1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY DC ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, Vcc = 5V±0.5V, unless otherwise noted) Symbol Parameter ILI ILO ISB1 ISB2 ICC1 ICC2 ICC3 Input leakage current Output leakage current IPP1 VPP read current IPP2 IPP3 VIL VIH VOL VOH1 VOH2 VPPL VPPH VPP program current VPP erase current Input low voltage Input high voltage Output low voltage Test conditions Min Limits Typ 0V≤VIN≤VCC 0V≤VOUT≤VCC VCC = 5.5V, CE = VIH VCC = 5.5V, CE = VCC±0.2V VCC stand-by current VCC = 5.5V, CE = VIL, f = 11.8MHz, IOUT = 0mA VCC active read current VCC program current VCC erase current VPP = VPPH VPP = VPPH 0V≤VPP≤VCC VCC<VPP≤6.5V VPP = VPPH VPP = VPPH VPP = VPPH – 0.5 2.0 IOL = 5.8mA IOH = –2.5mA IOH = –100µA Output high voltage Max 10 10 1 100 30 30 30 10 100 100 30 30 0.8 Vcc+0.5 0.45 2.4 0 11.4 µA µA mA µA mA mA mA µA mA mA V V V V Vcc–0.4 VPP voltage during read-only mode VPP voltage during read/write mode Unit 12.0 6.5 12.6 V V AC ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, Vcc = 5V±0.5V, unless otherwise noted) Read-Only Mode Symbol tRC ta (AD) ta (CE) ta (OE) tCLZ tOLZ tDF tOH tWRR tAVAV tAVQV tELQV tGLQV tELQX tGLQX tGHQZ tOH tWHGL Parameter Read cycle time Address access time Chip enable access time Output enable access time Chip enable to output in low Z Output enable to output in low Z Output enable high to output in low Z Output hold from CE, OE, addresses Write recovery time before read Limits M5M28F101A-85 M5M28F101A-10 Min Max Min Max 85 100 85 100 85 100 50 45 0 0 0 0 25 25 0 0 6 6 Unit ns ns ns ns ns ns ns ns µs Note 4 : VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. Timing measurements are made under AC WAVEFORMS FOR READ OPERATIONS. 5 (970407) MITSUBISHI LSIs M5M28F101AFP,J,VP,RV-85,-10 1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY Read/Write Mode Symbol tWC tAS tAH tDS tDH tWRR tRRW tCS tCH tWP tWPH tDP tDE tOEH tDAEC tDAP tVSC tOWP tOWS tOWH tOAS tOAH tODS tODH tAVAV tAVWL tWLAX tDVWH tWHDX tWHGL tGHWL tELWL tWHEH tWLWH tWHWL tWHWL1 tWHWL2 tVPEH Limits Parameter M5M28F101A-85 Min 85 0 60 50 10 6 0 20 0 60 20 10 9.5 100 1.7 12 1 70 0 0 0 55 45 20 Write cycle time Address set-up time Address hold time Data set-up time Data hold time Write recovery time before read Read recovery time before write Chip enable set-up time Chip enable hold time Write pulse width Write pulse width high Duration of program operation Duration of erase operation Output enable hold time before status / data polling Duration of auto erase operation Duration of auto program operation VPP set-up time to chip enable low Write pulse width (optional write) Write enable set-up time (optional write) Write enable hold time (optional write) Address set-up time (optional write) Address hold time (optional write) Data set-up time (optional write) Data hold time (optional write) Max 12.5 400 M5M28F101A-10 Min 100 0 60 50 10 6 0 20 0 60 20 10 9.5 100 1.7 12 1 70 0 0 0 55 45 20 Unit Max ns ns ns ns ns µs ns ns ns ns ns µs ms ns s µs µs ns ns ns ns ns ns ns 12.5 400 Note 5 : a. Read timing parameters during read/write mode are the same as during read-only mode. b. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. AC WAVEFORMS FOR READ OPERATIONS TEST CONDITIONS FOR AC CHARACTERISTICS VIH ADDREVIL SSES Input voltage : VIL = 0.45V, VIH = 2.4V Input rise and fall times : ≤10ns Reference voltage at timing measurement : 1.5V Output load : 1TTL gate + CL (= 100pF) or CE ADDRESS VALID tRC VIH VIL OE ta (CE) VIH VIL WE tWRR tDF 1.3V VIH ta (OE) VIL 1N914 tOH 3.3kΩ tOLZ DATA VOH VOL VCC 6 HIGH-Z tCLZ ta (AD) OUTPUT VALID HIGH-Z DUT CL = 100pF 5.0V GND (970407) MITSUBISHI LSIs M5M28F101AFP,J,VP,RV-85,-10 1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY AC WAVEFORMS FOR PROGRAM OPERATIONS CE VIL tCS tCH tRRW tWPH VIH DIN C0H COMMAND SET DATA SET COMMAND SET tVSC DATA TO BE VERIFIED tODH VPPH tOAS tOWS OPTIONAL WRITE tODS tOWH VIH VIL CE tDS 40H VPPL WE ta (CE) tDH 5.0V 0.0V VPP tWRR tDP ta (OE) tWP VIL VCC tAH VIH VIL DATA tAS VIH VIL WE tWC VIH VIL OE PROGRAM VERIFY PROGRAM VIH ADDRESSES tOAH tOWP VIH VIL AC WAVEFORMS FOR ERASE OPERATIONS ERASE VIH ADDRESSES CE VIL tCS tCH tRRW tWPH tWP VIH 20H COMMAND SET ta (CE) tDH tDS 20H A0H COMMAND SET COMMAND SET DATA TO BE VERIFIED 5.0V 0.0V VPP tWRR ta (OE) VIL VCC tDE VIH VIL DATA tAS VIH VIL WE tAH VIH VIL OE tWC ERASE VERIFY tVSC VPPH VPPL 7 (970407) MITSUBISHI LSIs M5M28F101AFP,J,VP,RV-85,-10 1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY AC WAVEFORMS FOR AUTO PROGRAM OPERATION PROGRAM / DATA POLLING VIH ADDRESSES CE ADDRESS VALID VIL tWC tCS ta (AD) tAH ta (CE) tCH tWPH tRRW tOEH ta (OE) VIH tDAP VIL DATA ADDRESS VALID VIH VIL WE ADDRESS VALID VIH VIL OE tAS tWP VIH VIL tDH tDS 10H or 50H Din Din COMMAND SET DATA SET OUTPUT Din Din OUTPUT 5.0V VCC VPP 0.0V tVSC VPPH VPPL AC WAVEFORMS FOR AUTO CHIP ERASE OPERATION ADDRESSES ERASE / STATUS POLLING VIH VIL CE tWC ta (CE) VIH VIL OE VIL WE tCS tDAEC tWP VIH tDH tDS 30H COMMAND SET 30H COMMAND SET "1" /(FFH) "0" D7OUTPUT "0" D7OUTPUT D7 / (D0~D7)OUTPUT 5.0V 0.0V VPP tOEH VIH VIL VCC ta (OE) tWPH tRRW VIL DATA tCH VIH tVSC VPPH VPPL 8 (970407) MITSUBISHI LSIs M5M28F101AFP,J,VP,RV-85,-10 1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY PROGRAMMING AND ERASE ALGORITHM FLOW CHART PROGRAM : ERASE : INPUT DATA START INPUT DATA START VCC = 5V, VPP = VPPH VCC = 5V, VPP = VPPH ADDR = FIRST LOCATION YES ALL BYTES = 00H? X=0 WRITE PROGRAM COMMAND 40H WRITE PROGRAM DATA DIN NO PROGRAM ALL BYTES = 00H ADDR = FIRST LOCATION DURATION = 10µs X=0 X=X+1 WRITE PROGRAMVERIFY COMMAND C0H WRITE ERASE COMMAND 20H WRITE ERASE COMMAND 20H DURATION = 6µs DURATION = 9.5ms X=X+1 X = 25? YES WRITE ERASE-VERIFY COMMAND A0H NO DURATION = 6µs FAIL VERIFY BYTE? PASS PASS VERIFY BYTE? X = 1000? FAIL YES NO INC ADDR NO LAST ADDR? FAIL VERIFY BYTE? YES WRITE READ COMMAND PASS VPP = VPPL INC ADDR DEVICE PASSED NO PASS VERIFY BYTE? FAIL LAST ADDR? DEVICE FAILED YES WRITE READ COMMAND VPP = VPPL DEVICE PASSED DEVICE FAILED (Erase Complete) 9 (970407) MITSUBISHI LSIs M5M28F101AFP,J,VP,RV-85,-10 1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY AUTO PROGRAM AND AUTO ERASE OPERATION AUTO PROGRAM : AUTO ERASE : START INPUT DATA VCC = 5.0V, VPP = VPPH INPUT DATA VCC = 5.0V, VPP = VPPH WRITE AUTO PROGRAM SETUP COMMAND 10H OR 50H WRITE AUTOERASE SETUP COMMAND 30H WRITE AUTO PROGRAM ADDRESS DATA DIN WRITE AUTOERASE COMMAND 30H DATA POLLING INCREMENT ADDR START NO LAST ADDR? STATUS POLLING ERASURE COMPLETE YES PROGRAMMING COMPLETE 10 (970407)