TI SMJ28F010B

SMJ28F010B
131072 BY 8-BIT
FLASH MEMORY
SGMS738 – APRIL 1998
D
D
D
D
D
D
D
D
D
D
D
Organization . . . 131 072 × 8-Bit Flash
Memory
Pin Compatible With Existing 1M-bit
EPROMs
High-Reliability MIL-PRF-38535 Processing
VCC Tolerance ±10%
All Inputs / Outputs TTL Compatible
Maximum Access / Minimum Cycle Time
28F010B-12
120 ns
’28F010B-15
150 ns
’28F010B-20
200 ns
Industry-Standard Programming Algorithm
10 000 Program / Erase-Cycle
Latchup Immunity of 250 mA on All Input
and Output Lines
Low Power Dissipation ( VCC = 5.5 V )
–Active Write . . . 55 mW
–Active Read . . . 165 mW
–Electrical Erase . . . 82.5 mW
–Standby . . . 0.55 mW
(CMOS-Input Levels)
Military Temperature Range
– 55°C to 125°C
JDD or FE PACKAGE
( TOP VIEW )
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
VCC
W
NC
A14
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
PIN NOMENCLATURE
A0 – A16
DQ0 – DQ7
E
G
NC
VCC
VPP
VSS
W
Address Inputs
Inputs (programming) / Outputs
Chip Enable
Output Enable
No Internal Connection
5-V Power Supply
12-V Power Supply
Ground
Write Enable
description
The SMJ28F010B is a 104 8 576-bit, programmable read-only memory that can be electrically bulk-erased and
reprogrammed. It is available in 10 000 program / erase-endurance-cycle version.
The SMJ28F010B flash memory is offered in a 32-lead ceramic 600-mil side-braze dual in-line package (DIP)
(JDD suffix) and a leadless ceramic chip carrier (FE suffix).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
• HOUSTON, TEXAS 77251–1443
1
SMJ28F010B
131072 BY 8-BIT
FLASH MEMORY
SGMS738 – APRIL 1998
device symbol nomenclature
SMJ28F010B
-12
JDD
M
Temperature Range Designator
M = – 55°C to 125°C
Package Designator
JDD = Ceramic Side-Braze
Dual- In-Line Package
Speed Designator
-12 = 120 ns
-15 = 150 ns
-20 = 200 ns
2
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SMJ28F010B
131072 BY 8-BIT
FLASH MEMORY
SGMS738 – APRIL 1998
logic symbol†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
E
G
W
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
22
24
31
13
0
FLASH
MEMORY
131 072 × 8
A
0
131 071
16
G1
[PWR DWN]
G2
1, 2 EN (READ)
1C3 (WRITE)
A, 3D
∇4
A, Z4
14
15
17
18
19
20
21
† This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the JDD package.
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3
SMJ28F010B
131072 BY 8-BIT
FLASH MEMORY
SGMS738 – APRIL 1998
functional block diagram
DQ0 – DQ7
8
Erase-Voltage Switch
VPP
W
Input / Output Buffers
State Control
To Array
Program / Erase
Stop Timer
Command Register
Program-Voltage
Switch
STB
Data Latch
Chip-Enable and
Output-Enable
Logic
E
G
STB
A0 – A16
A
d
d
r
e
s
s
17
L
a
t
c
h
4
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Column Decoder
Column Gating
Row Decoder
1 048 576-Bit
Array Matrix
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SMJ28F010B
131072 BY 8-BIT
FLASH MEMORY
SGMS738 – APRIL 1998
operation
Table 1 lists the modes of operation for the device.
Table 1. Operation Modes
FUNCTION†
MODE
VPP‡
(1)
E
(22)
G
(24)
A0
(12)
A9
(26)
W
(31)
DQ0 – DQ7
(13 – 15, 17 – 21)
VPPL
VPPL
VIL
VIL
X
X
VIH
VIH
Data Out
X
Standby and Write Inhibit
VPPL
VIH
VIL
VIH
X
X
Output Disable
X
X
X
Read
Read
g
Algorithm-Selection
Mode
VPPL
Read
Read /
Write
Output Disable
Standby and Write Inhibit
Write
VIL
VIL
VIL
VID
VIH
VIH
X
X
Hi-Z
Hi-Z
Manufacturer-Equivalent
Code 89h
Device-Equivalent Code B4h
VPPH
VPPH
VIL
VIL
VIL
VIH
X
X
VIH
VIH
VPPH
VPPH
VIH
VIL
X
X
X
X
VIH
X
X
Data Out
Hi-Z
Hi-Z
Data In
VIL
† X can be VIL or VIH.
‡ VPPL ≤ VCC + 2 V; VPPH is the programming voltage specified for the device. For more details, see the recommended operating conditions.
read/ output disable
When the outputs of two or more SMJ28F010B devices are connected in parallel on the same bus, the output
of any particular device in the circuit can be read with no interference from the competing outputs of other
devices. Reading the output of the SMJ28F010B is enabled when a low-level signal is applied to the E and G
pins. All other devices in the circuit must have their outputs disabled by applying a high-level signal to one of
these pins.
standby and write inhibit
Active ICC current can be reduced from 30 mA to 1 mA by applying a high TTL level on E or to 100 µA with a
high CMOS level on E. In this mode, all outputs are in the high-impedance state. The SMJ28F010B draws active
current when it is deselected during programming, erasure, or program / erase verification. It continues to draw
active current until the operation is terminated.
algorithm-selection mode
The algorithm-selection mode provides access to a binary code identifying the correct programming and erase
algorithms. This mode is activated when A9 ( pin 26) is forced to VID. Two identifier bytes are accessed by
toggling A0. All other addresses must be held low. A0 low selects the manufacturer-equivalent code 89h, and
A0 high selects the device-equivalent code B4h, as shown in Table 2.
Table 2. Algorithm-Selection Modes
IDENTIFIER§
PINS
A0
DQ7
DQ6
Manufacturer-Equivalent Code
DQ5
VIL
1
0
0
Device-Equivalent Code
VIH
1
0
1
§ E =VIL, G = VIL, A1 – A8 = VIL, A9 = VID, A10 – A16 = VIL, VPP = VPPL.
POST OFFICE BOX 1443
DQ4
DQ3
DQ2
DQ1
DQ0
0
1
0
0
1
89
1
0
1
0
0
B4
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HEX
5
SMJ28F010B
131072 BY 8-BIT
FLASH MEMORY
SGMS738 – APRIL 1998
programming and erasure
In the erased state, all bits are at a logic 1. Before erasing the device, all memory bits must be programmed to
a logic 0. Then the entire chip is erased. At this point, the bits, which are now logic 1s, can be programmed
accordingly. See the fast-write and fast-erase algorithms for further details.
command register
The command register controls the program and erase functions of the SMJ28F010B. The algorithm-selection
mode can be activated using the command register in addition to the previously described method. When VPP
is high, the contents of the command register and the function being performed can be changed. The command
register is written to when E is low and W is pulsed low. The address is latched on the leading edge of the pulse,
while the data is latched on the trailing edge. Accidental programming or erasure is minimized because two
commands must be executed to invoke either operation. The command register is inhibited when VCC is below
the erase / write lockout voltage, VLKO .
power-supply considerations
Each device must have a 0.1-µF ceramic capacitor connected between VCC and VSS to suppress circuit noise.
Changes in current drain on VPP require it to have a bypass capacitor as well. Printed-circuit traces for both
power supplies should be appropriate to handle the current demand.
command definitions
The commands include read, algorithm-selection mode, set-up-erase, erase, erase-verify, set-up-program,
program, program-verify, and reset. Table 3 lists the command definitions with the required bus cycles.
Table 3. Command Definitions
REQUIRED
BUS
CYCLES
OPERATION†
ADDRESS
DATA
OPERATION†
ADDRESS
DATA
Read
1
Write
X
00h
Read
RA
RD
Algorithm-Selection Mode
3
Write
X
90h
Read
0000h
0001h
89h
B4h
Set-Up-Erase / Erase
2
Write
X
20h
Write
X
20h
Erase-Verify
2
Write
EA
A0h
Read
X
EVD
Set-Up-Program / Program
2
Write
X
40h
Write
PA
PD
Program-Verify
2
Write
X
C0h
Read
X
PVD
Reset
2
Write
X
FFh
Write
X
FFh
COMMAND
FIRST BUS CYCLE
SECOND BUS CYCLE
Legend:
EA
Address of memory location to be read during erase verify
RA
Address of memory location to be read
PA
Address of memory location to be programmed. Address is latched on the falling edge of W.
RD
Data read from location RA during the read operation
EVD
Data read from location EA during erase verify
PD
Data to be programmed at location PA. Data is latched on the rising edge of W.
PVD
Data read from location PA during program verify
† Modes of operation are defined in Table 1.
read command
Memory contents can be accessed while VPP is high or low. When VPP is high, writing 00h into the command
register invokes the read operation. When the device is powered up, the default contents of the command
register are 00h and the read operation is enabled. The read operation remains enabled until a different
command is written to the command register.
6
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SMJ28F010B
131072 BY 8-BIT
FLASH MEMORY
SGMS738 – APRIL 1998
algorithm-selection mode command
The algorithm-selection mode is activated by writing 90h into the command register. The device-equivalent code
( B4h) is identified by the value read from address location 0001h, and the manufacturer-equivalent code ( 89h)
is identified by the value read from address location 0000h.
set-up-erase / erase commands
The erase-algorithm initiates with E = VIL, W = VIL, G = VIH, VPP = VPPH, and VCC = 5 V. To enter the erase mode,
write the set-up-erase command, 20h, into the command register. After the SMJ28F010B is in the erase mode,
writing a second erase command, 20h, into the command register invokes the erase operation. The erase
operation begins on the rising edge of W and ends on the rising edge of the next W. The erase operation requires
at least 9.5 ms to complete before the erase-verify command, A0h, can be loaded.
Maximum erase timing is controlled by the internal stop timer. When the stop timer terminates the erase
operation, the device enters an inactive state and remains inactive until a command is received.
program-verify command
The SMJ28F010B can be programmed sequentially or randomly, because it is programmed one byte at a time.
Each byte must be verified after it is programmed. The program-verify operation prepares the device to verify
the most recently programmed byte. To invoke the program-verify operation, C0h must be written into the
command register. The program-verify operation ends on the rising edge of W.
While verifying a byte, the SMJ28F010B applies an internal margin voltage to the designated byte. If the true
data and programmed data match, programming continues to the next designated byte location; otherwise, the
byte must be reprogrammed. Figure 1 shows how commands and bus operations are combined for byte
programming.
erase-verify command
All bytes must be verified following an erase operation. After the erase operation is complete, an erased byte
can be verified by writing the erase-verify command, A0h, into the command register. This command causes
the device to exit the erase mode on the rising edge of W. The address of the byte to be verified is latched on
the falling edge of W. The erase-verify operation remains enabled until a command is written to the command
register.
To determine whether all the bytes have been erased, the SMJ28F010B applies a margin voltage to each byte.
If FFh is read from the byte, all bits in the designated byte have been erased. The erase-verify operation
continues until all of the bytes have been verified. If FFh is not read from a byte, an additional erase operation
needs to be executed. Figure 2 shows the combination of commands and bus operations for electrically erasing
the SMJ28F010B.
set-up-program / program commands
The programming algorithm initiates with E = VIL, W = VIL, G = VIH, VPP = VPPH, and VCC = 5 V. To enter the
programming mode, write the set-up-program command, 40h, into the command register. The programming
operation is invoked by the next write-enable pulse. Addresses are latched internally on the falling edge of W,
and data is latched internally on the rising edge of W. The programming operation begins on the rising edge
of W and ends on the rising edge of the next W pulse. The program operation requires 10 µs for completion
before the program-verify command, C0h, can be loaded.
Maximum program timing is controlled by the internal stop timer. When the stop timer terminates the program
operation, the device enters an inactive state and remains inactive until a command is received.
reset command
To reset the SMJ28F010B after set-up-erase-command or set-up-program-command operations without
changing the contents in memory, perofrm two consecutive writes of FFh into the command register. After
executing the reset command, the device defaults to the read mode.
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SMJ28F010B
131072 BY 8-BIT
FLASH MEMORY
SGMS738 – APRIL 1998
fast-write algorithm
Figure 1 shows the process flow for programming the SMJ28F010B. The fast-write algorithm programs in a
nominal time of two seconds.
fast-erase algorithm
Figure 2 shows the process flow for erasing the SMJ28F010B using the fast-erase algorithm. The memory array
must be completely programmed (using the fast-write algorithm) before erasure begins. Erasure typically
occurs in one second.
parallel erasure
Several devices can be erased in parallel, reducing total erase time. Since the rate at which each flash memory
can erase differs, every device must be verified separately after each erase pulse. After a given device has been
successfully erased, the erase command should not be reissued to this device. All devices that complete
erasure should be masked until the parallel erasure process is finished (see Figure 3).
Examples of how to mask a device during parallel erase include driving the E pin high, writing the read command
(00h) to the device when the others receive a set-up-erase or erase command, and disconnecting the device
from all electrical signals with relays or other types of switches.
flow charts
Figure 1, Figure 2, and Figure 3 are flow charts showing the fast-write algorithm, the fast-erase algorithm, and
the parallel-erase flow.
8
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SMJ28F010B
131072 BY 8-BIT
FLASH MEMORY
SGMS738 – APRIL 1998
flow charts (continued)
Bus
Operation
Start
Address = 00h
Initialize
Address
VCC = 5 V ± 10%, VPP = 12 V ± 5%
Standby
Command
Comments
Wait for VPP to ramp to
VPPH (see Note A)
Setup
X=1
Initialize pulse count
Write Set-Up-Program Command
Write
Set-UpProgram
Write
Data = 40h
Write
Write Data
Valid address / data
Write Data
Increment
Address
Wait = 10 µs
X=X+1
Write Program-Verify Command
Wait = 10 µs
Standby
Wait = 6 µs
No
Read
Fail
and Verify
Byte
Write
ProgramVerify
X = 25?
Data = C0h; ends
program operation
Standby
Wait = 6 µs
Read
Read byte to verify
programming; compare
output to expected output
Yes
Pass
Interactive
Mode
No
Last
Address
?
—
—
—
Write
Read
Data = 00h; resets register
for read operations
Yes
Write Read Command
Power
Down
Apply VPPL
Apply VPPL
Standby
Device Passed
Wait for VPP to ramp to
VPPL (see Note B)
Device Failed
NOTES: A. See the recommended operating conditions for the value of VPPH.
B. See the recommended operating conditions for the value of VPPL.
Figure 1. Algorithm-Selection Programming Flow Chart
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SMJ28F010B
131072 BY 8-BIT
FLASH MEMORY
SGMS738 – APRIL 1998
flow charts (continued)
Bus
Operation
Start
Command
Preprogram
All Bytes = 00h
?
No
Comments
Entire memory must = 00h
before erasure
Program All
Bytes to 00h
Use fast-write
programming algorithm
Yes
Address = 00h
Initialize addresses
VCC = 5 V ± 10%, VPP = 12 V ± 5%
Setup
X=1
Standby
Wait for VPP to ramp to
VPPH (see Note A)
Write Set-Up-Erase Command
Initialize pulse count
Write-Erase Command
Wait = 10 ms
Write
Set-UpErase
Data = 20h
Write
Erase
Data = 20h
X=X+1
Interactive
Mode
Write Erase-Verify Command
Wait = 6 µs
Standby
Wait = 10 ms
No
Increment
Address
Read
and Verify
Byte
Pass
No
Write
Fail
X = 1000?
EraseVerify
Addr = Byte to verify;
Data = A0h; ends the erase
operation
Yes
Standby
Wait = 6 µs
Read
Read byte to verify erasure;
compare output to FFh
Last
Address?
Yes
Write Read Command
Apply VPPL
Apply VPPL
Device Passed
Device Failed
Power
Down
Write
Standby
NOTES: A. Refer to the recommended operating conditions for the value of VPPH.
B. Refer to the recommended operating conditions for the value of VPPL.
Figure 2. Flash-Erase Flow Chart
10
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Read
Data = 00h; resets register
for read operations
Wait for VPP to ramp to
VPPL (see Note B)
SMJ28F010B
131072 BY 8-BIT
FLASH MEMORY
SGMS738 – APRIL 1998
flow charts (continued)
Start
Program All Devices to 00h
X=1
Give Erase Command to All
Devices
Device # D = 1
Yes
Mask Device #D
Is
Device #D
Erased
?
X = X+1
No
D = n†
?
Give Erase
Command to
All Unmasked
Devices
No
D = D+1
Yes
No
Are
All Devices
Erased
?
No
X = 1000
?
Yes
Yes
Give Read
Command to
All Devices
Give Read
Command to
All Devices
All Devices Pass
Finished With Errors
† n = number of devices being erased.
Figure 3. Parallel-Erase Flow Chart
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SMJ28F010B
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FLASH MEMORY
SGMS738 – APRIL 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V
Supply voltage range, VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 14 V
Input voltage range (see Note 2): All inputs except A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V
A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 13.5 V
Output voltage range (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V
Output short-circuit current (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Operating free-air temperature range during read / erase / program, TA . . . . . . . . . . . . . . . . . – 55° C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Maximum power dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to VSS.
2. The voltage on any input pin can undershoot to – 2 V for periods less than 20 ns.
3. The voltage on any output pin can overshoot to 7 V for periods less than 20 ns.
4. No more than one output can be shorted at a time, and the duration cannot exceed one second.
recommended operating conditions
VCC
VPP
Supply voltage
Supply voltage
During write / read / flash erase
During read only ( VPPL)
MIN
NOM
MAX
4.5
5
5.5
V
V
12
VCC + 2
12.6
0
During write / read / flash erase (VPPH)
11.4
TTL
2
VCC + 0.5
VCC + 0.5
UNIT
V
VIH
High level dc input voltage
High-level
VIL
Low level dc input voltage
Low-level
VID
TA
Voltage level on A9 for algorithm-selection mode
11.5
13
V
Operating free-air temperature
– 55
125
°C
12
CMOS
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TTL
VCC – 0.5
– 0.5
CMOS
GND – 0.2
• HOUSTON, TEXAS 77251–1443
0.8
GND + 0.2
V
V
SMJ28F010B
131072 BY 8-BIT
FLASH MEMORY
SGMS738 – APRIL 1998
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MAX
VOH
High level output voltage
High-level
VOL
Low level output voltage
Low-level
VCC = 4.5 V,
IOL = 100 µA
IOL = 5.8 mA
IID
A9 algorithm-selection-mode current
VCC = 5.5 V,
VCC = 5.5 V,
A9 = VID max
VI = 0 V to 5.5 V
±1
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0 V to 13 V
± 200
VO = 0 V to VCC
±10
Read mode
200
All except A9
IOH = – 2.5 mA
MIN
VCC = 4.5 V,
VCC = 4.5 V,
IOH = – 100 µA
2.4
UNIT
V
VCC – 0.4
0.45
0.1
200*
V
µA
µA
II
Input current (leakage)
IO
Output current (leakage)
IPP1
VPP supply current (read / standby)
VPP = VPPH,
VPP = VPPL
IPP2
IPP3
VPP supply current (during program pulse)
VPP supply current (during flash erase)
VPP = VPPH
VPP = VPPH
30*
mA
30*
mA
IPP4
VPP supply current (during program / erase-verify)
TTL-input level
VCC supply current (standby)
CMOS-input level
VPP = VPPH
VCC = 5.5 V,
5.0*
mA
A9
±10
µA
µA
ICC1
VCC supply current (active read)
ICC2
VCC average supply current (active write)
E = VIH
VCC = 5.5 V,
E = VCC ± 0.2 V
VCC = 5.5 V,
E = VIL,
f = 6 MHz,
IOUT = 0 mA,
G = VIH
VCC = 5.5 V,
E = VIL,
Programming in progress
ICC3
VCC average supply current (flash erase)
VCC = 5.5 V,
E = VIL,
Erasure in progress
15*
mA
ICC4
VCC average supply current (program / erase-verify)
VCC = 5.5 V,
E = VIL,
VPP = VPPH,
Program / erase-verify in progress
15*
mA
ICCS
VLKO VCC erase / write-lockout voltage
* This parameter is not production tested.
VPP = VPPH
1
mA
100
µA
30
mA
10*
mA
2.5
V
capacitance over recommended range of supply voltage
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Ci1
Input capacitance
VI = 0 V, TA = 25°C,
f = 1 MHz
Co
Output capacitance
VO = 0 V, TA = 25°C,
f = 1 MHz
12*
pF
Ci2
VPP input capacitance
VI = 0 V, TA = 25°C,
f = 1 MHz
12*
pF
10*
pF
* This parameter is not production tested.
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SMJ28F010B
131072 BY 8-BIT
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switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 6)
PARAMETER
TEST
CONDITIONS
ALTERNATE
SYMBOL
’28F010B-12
MIN
MAX
’28F010B-15
MIN
MAX
’28F010B-20
MIN
MAX
UNIT
ta(A)
Access time from address,
A0 – A16
tAVQV
120
150
200
ns
ta(E)
Access time from chip enable, E
tELQV
120
150
200
ns
ten(G)
Access time from output
enable, G
tGLQV
50
55
60
ns
tc(R)
Cycle time, read
CL = 100 pF,
1 Series 74
TTL load
load,
Input tr ≤ 10 ns,
Input tf ≤ 10 ns
tAVAV
120
150
200
ns
tELQX
0*
0*
0*
ns
tGLQX
0*
0*
0*
ns
td(E)
Delay time, E low to low-Z
output
td(G)
Delay time, G low to low-Z
output
tdis(E)
Chip disable time to Hi-Z output
tEHQZ
0*
55*
0*
55*
0*
55*
ns
tdis(G)
Output disable time to Hi-Z
output
tGHQZ
0*
30*
0*
35*
0*
45*
ns
th(D)
Hold time, data valid from
address, E or G (see Note 5)
tAXQX
0*
0*
0*
ns
tWHGL
6
6
6
µs
trec(W) Recovery time, W before read
* This parameter is not production tested.
NOTE 5: Whichever occurs first
14
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SMJ28F010B
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timing requirements–write/erase/program operations (see Figure 7 and Figure 8)
’28F010B-12
’28F010B-15
’28F010B-20
ALTERNATE
SYMBOL
MIN
tAVAV
120
150
200
ns
10
10
µs
NOM
MAX
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
tc(W)
Cycle time, write
using W
tc(W)PR
Cycle time, programming operation
tWHWH1
10
tc(W)ER
Cycle time, erase
operation
tWHWH2
9.5
tWLAX
tWHEH
60
60
60
ns
Hold time, E
0
0
0
ns
Hold time, data valid
after W high
tWHDX
10
10
10
ns
tAVWL
tDVWH
0
0
0
ns
Setup time, data
50
50
50
ns
tsu(E)
Setup time, E before
W
tELWL
20
20
20
ns
tsu(VPPEL)
Setup time, VPP to E
low
tVPEL
1
1
1
µs
trec(W)
Recovery time, W
before read
tWHGL
6
6
6
µs
trec(R)
Recovery time, read
before W
tGHWL
0
0
0
µs
tw(W)
Pulse duration, W
(see Note 6)
tWLWH
60
60
60
ns
tw(WH)
Pulse duration, W
high
tWHWL
20
20
20
ns
tVPPR
tVPPF
1
1
1
µs
1
1
1
µs
th(A)
th(E)
th(WHD)
tsu(A)
tsu(D)
tr(VPP)
tf(VPP)
Hold time, address
Setup time, address
Rise time, VPP
Fall time, VPP
10
9.5
10
9.5
10
ms
NOTE 6: Rise / fall time ≤ 10 ns.
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SMJ28F010B
131072 BY 8-BIT
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SGMS738 – APRIL 1998
timing requirements — alternative E-controlled writes (see Figure 9)
’28F010B 12
’28F010B-12
ALTERNATE
SYMBOL
tc(W)
tc(E)PR
Cycle time, write using E
th(EA)
th(ED)
Hold time, address
th(W)
tsu(A)
Hold time, W
tsu(D)
tsu(W)
Setup time, data
tsu(VPPEL)
trec(E)R
Setup time, VPP to E low
trec(E)W
tw(E)
Recovery time, read before write using E
tw(EH)
Pulse duration, write, E high
Cycle time, programming operation
Hold time, data
Setup time, address
Setup time, W before E
Recovery time, write using E before read
MIN
MAX
’28F010B 15
’28F010B-15
MIN
MAX
’28F010B 20
’28F010B-20
MIN
MAX
UNIT
tAVAV
tEHEH
120
150
200
ns
10
10
10
µs
tELAX
tEHDX
80
80
80
ns
10
10
10
ns
tEHWH
tAVEL
0
0
0
ns
0
0
0
ns
tDVEH
tWLEL
50
50
50
ns
0
0
0
ns
tVPEL
tEHGL
tGHEL
1
1
1
µs
6
6
6
µs
0
0
0
µs
tELEH
tEHEL
70
70
70
ns
20
20
20
ns
Pulse duration, write using E
PARAMETER MEASUREMENT INFORMATION
2.08 V
RL = 800 Ω
Output
Under Test
CL = 100 pF
(see Note A)
NOTE A: CL includes probe and fixture capacitance.
Figure 4. AC Test Output Load Circuit
2.4 V
0.45 V
2V
0.8 V
2V
0.8 V
See Note A
NOTE A: The ac testing inputs are driven at 2.4 V for logic high and 0.45 V for logic low. Timing measurements are made at 2 V for logic high
and 0.8 V for logic low on both inputs and outputs. Each device should have a 0.1-µF ceramic capacitor connected between VCC and
VSS as closely as possible to the device pins.
Figure 5. AC Test Input / Output Waveform
16
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PARAMETER MEASUREMENT INFORMATION
tc(R)
Address Valid
A0 – A16
ta(A)
E
ta(E)
tdis(E)
G
trec(W)
ten(G)
W
td(E)
DQ0 – DQ7
td(G)
Hi-Z
tdis(G)
th(D)
Ouput Valid
Hi-Z
Figure 6. Read-Cycle Timing
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PARAMETER MEASUREMENT INFORMATION
Program
Command
Program
Latch
Verify
Address
and Data Programming Command
Power Up Set-UpProgram
and
Standby Command
Program
Verification
Standby /
Power Down
A0 – A16
tc(W)
tc(W)
tc(W)
tsu(A)
tc(R)
th(A)
th(A)
tsu(A)
E
tsu(E)
tsu(E)
tdis(E)
tsu(E)
th(E)
th(E)
G
th(E)
tc(W)PR
trec(R)
tw(WH)
tdis(G)
trec(W)
W
th(WHD)
th(WHD)
tw(W)
tw(W)
tsu(D)
DQ0 – DQ7
tsu(D)
th(WHD)
tsu(D)
Data In
Data In = C0h
Valid Data Out
tsu(VPPEL)
VPPH
VPPL
tf(VPP)
tr(VPP)
Figure 7. Write-Cycle Timing
18
td(E)
ta(E)
5V
0V
VPP
td(G)
tw(W)
Hi-Z
Data In = 40h
VCC
th(D)
ten(G)
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PARAMETER MEASUREMENT INFORMATION
Power Up Set-UpErase
and
Standby Command
Erase
Command
EraseVerify
Command
Erasing
Erase
Standby /
Verification Power Down
A0 – A16
tc(W)
tc(W)
tc(W)
tc(R)
th(A)
tsu(A)
E
tsu(E)
tsu(E)
tsu(E)
th(E)
th(E)
G
tw(WH)
trec(R)
tdis(E)
th(E)
tc(W)ER
trec(W)
tdis(G)
W
th(D)
th(WHD)
th(WHD)
tw(W)
tw(W)
tsu(D)
DQ0 – DQ7
tsu(D)
th(WHD)
ten(G)
td(G)
tw(W)
tsu(D)
Hi-Z
Data In = 20h
Data In = 20h
Data In = A0h
td(E)
ta(E)
Valid Data Out
5V
VCC
0V
tsu(VPPEL)
VPPH
VPP
VPPL
tf(VPP)
tr(VPP)
Figure 8. Flash-Erase-Cycle Timing
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SMJ28F010B
131072 BY 8-BIT
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SGMS738 – APRIL 1998
PARAMETER MEASUREMENT INFORMATION
Program
Command
Program
Latch
Verify
Address
and Data Programming Command
Power Up Set-UpProgram
and
Standby Command
Program
Verification
Standby /
Power Down
A0 – A16
tc(W)
tc(W)
tc(W)
tsu(A)
th(EA)
tc(R)
th(EA)
tsu(A)
W
tsu(W)
tsu(W)
tdis(G)
tsu(W)
th(W)
th(W)
th(W)
G
tc(E)PR
trec(E)W
tdis(E)
trec(E)R
tw(EH)
E
tw(E)
tsu(D)
DQ0 – DQ7
th(D)
th(ED)
th(ED)
tw(E)
tsu(D)
th(ED)
td(G)
tw(E)
tsu(D)
Hi-Z
Data In
Data In = 40h
VCC
ten(G)
Data In = C0h
td(E)
ta(E)
Valid Data Out
5V
0V
tsu(VPPEL)
VPPH
VPP
VPPL
tf(VPP)
tr(VPP)
Figure 9. Write-Cycle (Alternative E-Controlled Writes) Timing
20
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131072 BY 8-BIT
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SGMS738 – APRIL 1998
MECHANICAL DATA
FE (R-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
17
NO. OF
TERMINALS
**
13
18
12
B
A
C
MIN
MAX
MIN
MAX
MIN
MAX
18
0.285
(7,24)
0.295
(7,49)
0.061
(1,55)
0.073
(1,85)
0.345
(8,76)
0.365
(9,27)
28
0.345
(8,76)
0.355
(9,02)
0.065
(1,65)
0.079
(2,01)
0.540
(13,72)
0.560
(14,22)
32
0.445
(11,30)
0.455
(11,56)
0.065
(1,65)
0.079
(2,01)
0.540
(13,72)
0.560
(14,22)
C
26
4
27
1
3
0.045 (1,14)
0.035 (0,89)
0.025 (0,64)
0.015 (0,38)
0.045 (1,14)
0.035 (0,89)
0.025 (0,64)
0.015 (0,38)
0.028 (0,71)
0.022 (0,56)
B
0.050 (1,27)
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
4040137 / B 03/95
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
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SMJ28F010B
131072 BY 8-BIT
FLASH MEMORY
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MECHANICAL DATA
JDD (R-CDIP-T32)
CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
1.620 (41,15)
1.580 (40,13)
32
17
0.605 (15,37)
0.585 (14,86)
1
16
0.065 (1,65)
0.045 (1,14)
0.120 (3,05)
0.089 (2,26)
0.060 (1,52)
0.030 (0,76)
0.610 (15,49)
0.590 (14,99)
Seating Plane
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.175 (4,45)
0.125 (3,18)
0.014 (0,36)
0.008 (0,20)
4040280/B 03/96
NOTES: A.
B.
C.
D.
22
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals will be gold plated.
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