MITSUBISHI LSIs MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7, M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S -5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD 16-BIT) DYNAMIC RAM FAST PAGE MODE 4194304-BIT (262144-WORD BY BY 16-BIT) DYNAMIC RAM DESCRIPTION This is a family of 262144-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS process, and is ideal for memory systems where high speed, low power dissipation, and low costs are essential. The use of double-layer metalization process technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is small enough for battery back-up application. This device has 2CAS and 1W terminals with a refresh cycle of 512 cycles every 8.2ms. FEATURES RAS CAS access access time time (max.ns) (max.ns) Type name M5M44260CXX-5,-5S M5M44260CXX-6,-6S M5M44260CXX-7,-7S 50 60 70 Address OE access access time time (max.ns) (max.ns) 13 15 20 25 30 35 13 15 20 Power Cycle dissipatime tion (min.ns) (typ.mW) 90 110 130 625 550 475 XX=J,TP Standard 40pin SOJ, 44 pin TSOP (II) Single 5V±10% supply Low stand-by power dissipation CMOS Input level 5.5mW (Max) CMOS Input level 550µW (Max) * Operating power dissipation M5M44260Cxx-5,-5S 688mW (Max) M5M44260Cxx-6,-6S 605mW (Max) M5M44260Cxx-7,-7S 523mW (Max) Self refresh capability * Self refresh current 150µA (Max) Extended refresh capability Extended refresh current 150µA (Max) Fast-page mode (512-column random access), Read-modify-write, RAS-only refresh, CAS before RAS refresh, Hidden refresh capabilities. Early-write mode, LCAS / UCAS and OE to control output buffer impedance 512 refresh cycles every 8.2ms (A0~A8) 512 refresh cycles every 128ms (A0~A8) * Byte or word control for Read/Write operation (2CAS, 1W type) * : Applicable to self refresh version (M5M44260CJ,TP-5S,-6S,-7S : option) only PIN CONFIGURATION (TOP VIEW) 1 40 VSS(0V) DQ1 2 39 DQ16 DQ2 3 38 DQ15 DQ3 4 37 DQ14 DQ4 5 36 DQ13 (5V)VCC 6 35 VSS(0V) DQ5 7 34 DQ12 DQ6 8 33 DQ11 DQ7 9 32 DQ10 DQ8 10 31 DQ9 NC 11 30 NC NC 12 29 LCAS W 13 28 UCAS RAS 14 27 OE NC 15 26 A8 A0 16 25 A7 A1 17 24 A6 A2 18 23 A5 A3 19 22 A4 (5V)VCC 20 21 VSS(0V) (5V)VCC Outline 40P0K (400mil SOJ) (5V)VCC 1 44 VSS(0V) DQ1 2 43 DQ16 DQ2 3 42 DQ15 DQ3 4 41 DQ14 DQ4 5 40 DQ13 (5V)VCC 6 39 VSS(0V) DQ5 7 38 DQ12 DQ6 8 37 DQ11 DQ7 9 36 DQ10 DQ8 10 35 DQ9 NC 13 32 NC NC 14 31 LCAS 15 30 UCAS RAS 16 29 OE NC 17 28 A8 A0 18 27 A7 A1 19 26 A6 A2 20 25 A5 A3 21 24 A4 (5V)VCC 22 23 VSS(0V) APPLICATION Microcomputer memory, Refresh memory for CRT PIN DESCRIPTION W Pin name A0~A8 DQ1~DQ16 RAS LCAS UCAS 1 Function Address inputs Data inputs / outputs Row address strobe input Lower byte control column address strobe input Upper byte control column address strobe input W Write control input OE Output enable input VCC VSS Power supply (+5V) Ground (0V) M5M44260CJ,TP-5,-5S : Under development Outline 44P3W-R (400mil TSOP Nomal Bend) NC: NO CONNECTION MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM FUNCTION In addition to normal read,write and read-modify-write operations the M5M44260CJ, TP provides a number of other functions, e.g., fast page mode, RAS-only refresh and delayed-write. The input conditions for each are shown in Table 1. Table 1 Input conditions for each mode Input/Output Inputs Operation Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write RAS only refresh Hidden refresh CAS before RAS (Extended *) refresh Self refresh * Stand-by RAS LCAS UCAS ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT NAC ACT NAC ACT ACT NAC ACT NAC ACT ACT ACT DNC NAC ACT ACT NAC ACT ACT NAC ACT ACT ACT DNC W NAC NAC NAC ACT ACT ACT DNC DNC DNC DNC DNC OE ACT ACT ACT NAC NAC NAC DNC ACT DNC DNC DNC Row address Column address DQ1~ DQ8 APD APD APD APD APD APD APD DNC DNC DNC DNC APD APD APD APD APD APD DNC DNC DNC DNC DNC DOUT OPN DOUT DIN DNC DIN OPN DOUT OPN OPN OPN Refresh Remark DQ9~ DQ16 YES YES YES YES YES YES YES YES YES YES No OPN DOUT DOUT DNC DIN DIN OPN DOUT OPN OPN OPN Fast page mode identical Note : ACT : active, NAC : nonactive, DNC : don' t care, OPN : open BLOCK DIAGRAM VCC (5V) ROW ADDRESS STROBE INPUT RAS LOWER BYTE CONTROL COLUMN ADDRESS LCAS STROBE INPUT CLOCK GENERATOR CIRCUIT LOWER UPPER BYTE CONTROL UCAS COLUMN ADDRESS STROBE INPUT WRITE CONTROL INPUT VSS (0V) (8)LOWER DATA IN BUFFER UPPER DQ1 DQ2 LOWER DATA INPUTS / OUTPUTS W DQ8 (8)LOWER DATA OUT BUFFER VCC (5V) VSS (0V) A0~A8 COLUMN DECODER ADDRESS INPUTS A0 A1 A2 A3 A4 A5 A6 A7 A8 (8)UPPER DATA IN BUFFER SENSE REFRESH AMPLIFIER & I /O CONTROL ROW & COLUMN ADDRESS BUFFER ROW A 0~ A8 DECODER MEMORY CELL (4194304 BITS) (8)UPPER DATA OUT BUFFER DQ9 DQ10 DQ16 UPPER DATA INPUTS / OUTPUTS VCC (5V) VSS (0V) OE 2 M5M44260CJ,TP-5,-5S : Under development OUTPUT ENABLE INPUT MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IO Pd Topr Tstg Ratings -1~7 -1~7 -1~7 50 1000 0~70 -65~150 Conditions Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature With respect to VSS Ta=25˚C RECOMMENDED OPERATING CONDITIONS (Ta=0~70˚C, unless otherwise noted) Symbol VCC VSS VIH VIL Parameter Min 4.5 0 2.4 -0.5 * * Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs Limits Nom 5.0 0 Max 5.5 0 6.0 0.8 Unit V V V mA mW ˚C ˚C (Note 1) Unit V V V V Note 1 : All voltage values are with respect to VSS. * * : VIL(min) is -2.0V when pulse width is less than 25ns. (Pulse width is with respect to Vss.) ELECTRICAL CHARACTERISTICS (Ta=0~70˚C , VCC=5V±10%, VSS=0V, unless otherwise noted) Symbol Parameter VOH VOL IOZ II High-level output voltage Low-level output voltage Off-state output current Input current ICC1(AV) Average supply current from Vcc, operating Test conditions IOH=-5mA IOL=4.2mA Q floating 0V ≤ VOUT ≤ 5.5V 0V ≤ VIN ≤ +6.0V, Other inputs pins=0V M5M44260C-5,-5S M5M44260C-6,-6S (Note 3,4,5) M5M44260C-7,-7S (Note 2) Min 2.4 0 -10 -10 Limits Typ RAS, CAS cycling tRC=tWC=min. output open RAS= CAS =VIH, output open ICC2 ICC3(AV) ICC4(AV) ICC6(AV) ICC8(AV) * ICC9(AV) * 3 Supply current from VCC, stand-by (Note 6) RAS= CAS ≥ VCC -0.5V output open Max VCC 0.4 10 10 Unit V V µA µA 125 110 mA 95 2 1.0 mA 0.1 * 125 Average supply current M5M44260C-5,-5S from Vcc, RAS only M5M44260C-6,-6S refresh mode (Note 3,5) M5M44260C-7,-7S RAS cycling, CAS=VIH tRC=min. output open Average supply current M5M44260C-5,-5S from Vcc M5M44260C-6,-6S Fast page mode (Note 3,4,5) M5M44260C-7,-7S RAS=VIL, CAS cycling tPC=min. output open Average supply current M5M44260C-5,-5S from Vcc CAS before RAS refresh M5M44260C-6,-6S (Note 3,5) M5M44260C-7,-7S mode CAS before RAS refresh cycling tRC=min. output open 100 Average supply current from VCC Extended-refresh mode 150 µA (Note 6) RAS cycling CAS ≤ 0.2V or CAS before RAS refresh cycling RAS ≤ 0.2V or ≥ VCC-0.2V CAS ≤ 0.2V or ≥ VCC-0.2V W ≤ 0.2V or ≥ VCC-0.2V OE ≤ 0.2V or ≥ VCC-0.2V A0~A8 ≤ 0.2V or ≥ VCC-0.2V, DQ=open tRC=250µs, tRAS=tRAS min~1µs Average supply current from VCC Self-refresh mode (Note 6) RAS=CAS ≤ 0.2V output open 150 µA Note 2: Current flowing into an IC is positive, out is negative. 3: ICC1 (AV), ICC3 (AV), ICC4 (AV), and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: ICC1 (AV) and ICC4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column Address can be changed once or less while RAS=VIL and CAS=VIH. M5M44260CJ,TP-5,-5S : Under development 110 mA 95 125 110 mA 95 115 mA 85 MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM CAPACITANCE (Ta=0~70˚C , VCC=5V±10%, VSS=0V, unless otherwise noted) Symbol CI (A) CI (CLK) CI / O Parameter Input capacitance, address inputs Input capacitance, clock inputs Input/Output capacitance, data ports Test conditions Min Limits Typ VI=VSS f=1MHz VI=25mVrms Max 5 7 7 Unit pF pF pF SWITCHING CHARACTERISTICS (Ta=0~70˚C, VCC=5V±10%, Vss=0V, unless otherwise noted, see notes 6,13,14) Limits Symbol M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S Parameter Min tCAC tRAC tAA tCPA tOEA tCLZ tOFF tOEZ Access time from CAS Access time from RAS Columu address access time Access time from CAS precharge Access time from OE Output low impedance time from CAS low Output disable time after CAS high Output disable time after OE high (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7) (Note 7) (Note 12) (Note 12) Max 13 50 25 30 13 5 Min Max 15 60 30 35 15 5 13 13 Min Max 20 70 35 40 20 5 15 15 20 20 Unit ns ns ns ns ns ns ns ns Note 6: An initial pause of 500 µs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh cycles). Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 8.2ms) of RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to 2TTL loads and 100pF. 8: Assumes that tRCD ≥ tRCD(max) and tASC ≥ tASC(max). 9: Assumes that tRCD ≤ tRCD(max) and tRAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD ≥ tRAD(max) and tASC ≤ tASC(max). 11: Assumes that tCP ≤ tCP(max) and tASC ≥ tASC(max). 12: tOFF(max) and tOEZ (max) defines the time at which the output achieves the high impedance state (IOUT ≤ ±10 µA ) and is not reference to VOH(min) or VOL(max). 4 M5M44260CJ,TP-5,-5S : Under development MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and Fast-Page Mode Cycles) (Ta=0~70˚C, VCC=5V±10%, VSS=0V, unless otherwise noted, see notes 6,13,14) Limits Symbol Parameter M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S Min tREF tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tCDD tODD tT Refresh cycle time Refresh cycle time * RAS high pulse width Delay time, RAS low to CAS low Delay time, CAS high to RAS low Delay time, RAS high to CAS low CAS high pulse width Column address delay time from RAS low Row address setup time before RAS low Column address setup time before CAS low Row address hold time after RAS low Column address hold time after CAS low Delay time, data to CAS low Delay time, data to OE low Delay time, CAS high to data Delay time, OE high to data Transition time (Note 15) (Note 16) (Note 17) (Note 18) (Note 18) (Note 19) (Note 19) (Note 20) 30 18 5 0 10 13 0 0 8 13 0 0 13 13 1 Max 8.2 128 37 25 7 50 Min Max 8.2 128 40 20 5 0 10 15 0 0 10 15 0 0 15 15 1 45 30 10 50 Min 50 20 5 0 10 15 0 0 10 15 0 0 20 20 1 Max 8.2 128 50 35 10 50 Unit ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 13: The timing requirements are assumed tT =5ns. 14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. 16: tRAD(max) is specified as a reference point only. If tRAD ≥ tRAD(max) and tASC ≤ tASC(max), access time is controlled exclusively by tAA. 17: tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC. 18: Either tDZC or tDZO must be satisfied. 19: Either tCDD or tODD must be satisfied. 20: tT is measured between VIH(min) and VIL(max). Read and Refresh Cycles Limits Symbol Read cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Read setup time before CAS low Read hold time after CAS high Read hold time after RAS high Column address to RAS hold time CAS hold time after OE low RAS hold time after OE low Note 21: Either tRCH or tRRH must be satisfied for a read cycle. tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tOCH tORH 5 M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S Parameter M5M44260CJ,TP-5,-5S : Under development (Note 21) (Note 21) Min 90 50 13 50 13 0 0 0 25 13 13 Max 10000 10000 Min 110 60 15 60 15 0 0 0 30 15 15 Max 10000 10000 Min 130 70 20 70 20 0 0 0 35 20 20 Unit Max 10000 10000 ns ns ns ns ns ns ns ns ns ns ns MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Write Cycle (Early Write and Delayed Write) Limits Symbol tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH tOEH Parameter Write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Write setup time before CAS low Write hold time after CAS low CAS hold time after W low RAS hold time after W low Write pulse width Data setup time before CAS low or W low Data hold time after CAS low or W low OE hold time after W low M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S (Note 23) Min 90 50 13 50 13 0 8 13 13 8 0 8 13 Max 10000 10000 Min 110 60 15 60 15 0 10 15 15 10 0 10 15 Max 10000 10000 Min 130 70 20 70 20 0 15 20 20 15 0 15 20 Unit Max 10000 10000 ns ns ns ns ns ns ns ns ns ns ns ns ns Read-Write and Read-Modify-Write Cycles Limits Symbol tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tCWL tRWL tWP tDS tDH tOEH M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S Parameter Read write/read modify write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Read setup time before CAS low Delay time, CAS low to W low Delay time, RAS low to W low Delay time, address to W low CAS hold time after W low RAS hold time after W low Write pulse width Data setup time before CAS low or W low Data hold time after CAS low or W low OE hold time after W low (Note 22) (Note 23) (Note 23) (Note 23) Min 126 86 49 86 49 0 31 68 43 13 13 8 0 8 13 Max 10000 10000 Min 150 100 55 100 55 0 35 80 50 15 15 10 0 10 15 Max 10000 10000 Min 180 120 70 120 70 0 45 95 60 20 20 15 0 15 20 Unit Max 10000 10000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 23: tWCS, tCWD, tRWD and tAWD and tCPWD are specified as reference points only. If tWCS ≥ tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD ≥ tCWD(min), tRWD ≥ tRWD(min), tAWD ≥ tAWD(min) and tCPWD ≥ tCPWD(min) (for fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH) is indeterminate. 6 M5M44260CJ,TP-5,-5S : Under development MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Fast-Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) (Note 24) Limits Symbol tPC tPRWC tRAS tCP tCPRH tCPWD M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S Parameter Fast page mode read/write cycle time Fast page mode read write/read modify write cycle time RAS low pulse width for read or write cycle (Note 25) (Note 26) CAS high pulse width RAS hold time after CAS precharge Delay time, CAS precharge to W low (Note 23) Min 35 71 85 8 30 48 Max 100000 12 Min 40 80 100 10 35 55 Max 100000 15 Min 45 95 115 10 40 65 Unit Max 100000 15 ns ns ns ns ns ns Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle. 25: tRAS(min) is specified as two cycles of CAS input are performed. 26: tCP(max) is specified as a reference point only. CAS before RAS Refresh Cycle, Extended Refresh Cycle * (Note 27) Limits Symbol tCSR tCHR tCAS Parameter CAS setup time before RAS low CAS hold time after RAS low CAS low pulse width M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S Min 5 10 20 Max Min 5 10 20 Max Min 5 15 25 Unit Max ns ns ns Note 27: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode. Self Refresh Cycle * (Note 28) Limits Symbol tRASS tRPS tCHS Parameter CBR self refresh RAS low pulse width CBR self refresh RAS high precharge time CBR self refresh CAS hold time 7 M5M44260CJ,TP-5,-5S : Under development M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S Min 100 90 -50 Max Min 100 110 -50 Max Min 100 130 -50 Unit Max µs ns ns MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Timing Diagrams Read Cycle (Note 29) tRC tRAS RAS tRP VIH VIL tCSH tCRP tRPC tRSH tCAS tRCD tCRP VIH LCAS/UCAS VIL tRAD tASR A0~A8 VIH VIL tRAL tRAH tASC ROW ADDRESS tASR tCAH ROW ADDRESS COLUMN ADDRESS tRRH tRCH tRCS W VIH VIL tCDD tDZC DQ1~DQ16 (INPUTS) VIH Hi-Z VIL tCAC tAA tOFF tCLZ DQ1~DQ16 VOH (OUTPUTS) VOL Hi-Z Hi-Z DATA VALID tRAC tDZO tOEZ tOEA tODD tOCH OE VIH VIL tORH Note 29 Indicates the don't care input. VIH(min) ≤ VIN ≤ VIH(max) or VIL(min) ≤ VIN ≤ VIL(max) Indicates the invalid output. 8 M5M44260CJ,TP-5,-5S : Under development MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Byte Read Cycle tRC tRAS RAS tRP VIH VIL tCSH tCRP tRCD tRSH tRPC tCAS UCAS (or LCAS) tCRP VIH VIL tCPN LCAS (or UCAS) VIH VIL tRAD tASR A0~A8 VIH VIL tRAH tRAL tASC ROW ADDRESS tASR tCAH COLUMN ADDRESS ROW ADDRESS tRRH tRCH tRCS W VIH VIL DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS) DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL Hi-Z tCDD tDZC DQ9~DQ16 VIH (or DQ1~DQ8) VIL (INPUTS) Hi-Z tCAC tOFF tAA tCLZ DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL Hi-Z tRAC tOEZ tDZO tOEA tODD tOCH OE VIH VIL tORH 9 M5M44260CJ,TP-5,-5S : Under development Hi-Z DATA VALID MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Write Cycle (Early write) tWC tRP tRAS RAS VIH tRPC VIL tCSH tCRP tRSH tRCD tCAS tCRP tCPN VIH LCAS/UCAS VIL tASR A0~A8 VIH VIL W DQ1~DQ16 (INPUTS) tRAH ROW ADDRESS tASR tCAH COLUMN ADDRESS ROW ADDRESS tWCS tWCH tDS tDH VIH VIL VIH VIL DQ1~DQ16 VOH (OUTPUTS) VOL OE tASC VIH VIL 10 M5M44260CJ,TP-5,-5S : Under development DATA VALID Hi-Z MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Byte Write Cycle (Early write) tWC tRP tRAS RAS VIH VIL tCSH tCRP tRPC tRSH tRCD tCRP tCAS UCAS (or LCAS) VIH VIL tCPN LCAS (or UCAS) VIH VIL tASR A0~A8 VIH VIL tRAH tASC COLUMN ADDRESS ROW ADDRESS tWCS W tASR tCAH tWCH VIH VIL DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS) DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL Hi-Z tDS DQ9~DQ16 VIH (or DQ1~DQ8) VIL (INPUTS) DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL OE VIH VIL 11 M5M44260CJ,TP-5,-5S : Under development tDH DATA VALID Hi-Z ROW ADDRESS MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Write Cycle (Delayed write) tWC tRP tRAS RAS VIH VIL tRPC tCSH tRSH tRCD tCRP tCPN tCAS tCRP VIH LCAS/UCAS VIL tASR A0~A8 VIH VIL tRAH tCAH tASC tASR ROW ADDRESS COLUMN ADDRESS ROW ADDRESS tCWL tRWL tRCS W tWP VIH VIL tWCH tDS tDZC DQ1~DQ16 (INPUTS) VIH Hi-Z tDH DATA VALID VIL tCLZ DQ1~DQ16 VOH (OUTPUTS) VOL Hi-Z Hi-Z tDZO tOEH tOEZ tODD OE VIH VIL 12 M5M44260CJ,TP-5,-5S : Under development MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Byte Write Cycle (Delayed write) tWC tRAS RAS tRP VIH VIL tCSH tCRP tRPC tRCD tRSH tCRP tCAS UCAS (or LCAS) VIH VIL tCPN LCAS (or UCAS) VIH VIL tASR A0~A8 VIH VIL tRAH tCAH tASC ROW ADDRESS tASR COLUMN ADDRESS ROW ADDRESS tCWL tRWL tWP tRCS W VIH VIL DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS) DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL Hi-Z tWCH tDZC tDS DQ9~DQ16 VIH (or DQ1~DQ8) VIL (INPUTS) Hi-Z tDH DATA VALID tCLZ DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL Hi-Z Hi-Z tDZO tOEH tOEZ tODD OE VIH VIL 13 M5M44260CJ,TP-5,-5S : Under development MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Read-Write, Read-Modify-Write Cycle tRWC tRAS RAS tRP VIH VIL tRPC tCSH tCRP tRSH tRCD tCRP tCAS VIH LCAS/UCAS VIL tRAD tASR A0~A8 VIH VIL tRAH ROW ADDRESS ROW ADDRESS COLUMN ADDRESS tAWD tCWD tRWD tRCS W tASR tCAH tASC tCWL tRWL tWP VIH VIL tDZC DQ1~DQ16 (INPUTS) tDH tDS VIH Hi-Z VIL tCAC DATA VALID tAA tCLZ DQ1~DQ16 VOH (OUTPUTS) VOL Hi-Z tRAC tDZO OE VIH VIL 14 M5M44260CJ,TP-5,-5S : Under development Hi-Z DATA VALID tODD tOEA tOEZ tOEH MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Byte Read-Write, Read-Modify-Write Cycle tRWC tRP tRAS RAS VIH VIL tCSH tRPC tRSH tRCD tCRP UCAS (or LCAS) tCRP tCAS VIH VIL tCPN LCAS (or UCAS) VIH VIL tRAD tASR A0~A8 VIH VIL tRAH tCAH tASC ROW ADDRESS COLUMN ADDRESS ROW ADDRESS tAWD tCWD tRWD tRCS W tASR tCWL tRWL tWP VIH VIL DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS) DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL Hi-Z tDH tDS tDZC DQ9~DQ16 VIH (or DQ1~DQ8) VIL (INPUTS) Hi-Z DATA VALID tCAC tAA tCLZ DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL Hi-Z tRAC tODD tDZO OE VIH VIL 15 M5M44260CJ,TP-5,-5S : Under development Hi-Z DATA VALID tOEA tOEZ tOEH MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM RAS-only Refresh Cycle tRC tRAS RAS tRP VIH VIL tRPC tCRP tCRP VIH LCAS/UCAS VIL tASR A0~A8 VIH VIL W DQ1~DQ16 (INPUTS) VIH VIL VIH VIL VIH VIL 16 ROW ADDRESS ROW ADDRESS DQ1~DQ16 VOH (OUTPUTS) VOL OE tASR tRAH M5M44260CJ,TP-5,-5S : Under development Hi-Z MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM CAS before RAS Refresh Cycle, Extended Refresh Cycle * tRC tRP RAS tRC tRAS tRAS tRP VIH VIL tCSR tRPC tCHR tRPC tCSR tCHR tRPC tCRP VIH LCAS/UCAS VIL tCPN tASR A0~A8 VIH ROW ADDRESS VIL tRCS tRCH W VIH VIL tCDD DQ1~DQ16 (INPUTS) VIH Hi-Z VIL tOFF DQ1~DQ16 VOH (OUTPUTS) VOL Hi-Z tOEZ tODD OE VIH VIL 17 M5M44260CJ,TP-5,-5S : Under development COLUMN ADDRESS MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Hidden Refresh Cycle (Read) (Note 30) tRC tRC tRAS RAS tRP tRAS tRP VIH VIL tCRP tRCD tRSH tCHR VIH LCAS/UCAS VIL tRAD tASR A0~A8 VIH VIL tRAH tASC ROW ADDRESS tASR tCAH COLUMN ADDRESS ROW ADDRESS tRCS tRAL tRRH VIH W VIL tDZC DQ1~DQ16 (INPUTS) tCDD VIH Hi-Z VIL tCAC tAA tOFF tCLZ DQ1~DQ16 VOH (OUTPUTS) VOL Hi-Z Hi-Z DATA VALID tRAC tDZO OE tOEA tORH tOEZ tODD VIH VIL Note 30: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle described above. 18 M5M44260CJ,TP-5,-5S : Under development MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Fast Page Mode Read Cycle tRAS RAS tRP VIH VIL tPC tCSH tCRP tRCD tCAS tRSH tCAS tCP tCP tCAS VIH LCAS/UCAS VIL tRAD tASR A0~A8 VIH VIL tRAH tCPRH tASC ROW ADDRESS tASC tCAH COLUMN ADDRESS1 tASC tCAH tASR tCAH COLUMN ADDRESS3 COLUMN ADDRESS2 ROW ADDRESS tRAL tRCS W tRCH tRCS VIL tDZC VIH Hi-Z VIL tCLZ DATA VALID-1 tRAC tDZO Hi-Z tAA tOFF DATA VALID-2 tCPA tOEA tOCH Hi-Z tCAC tCAC tOFF Hi-Z tCDD tAA tCLZ DQ1~DQ16 VOH (OUTPUTS) VOL tDZC Hi-Z tCAC tAA OE tRCH tRRH tRCS VIH tDZC DQ1~DQ16 (INPUTS) tRCH tCLZ Hi-Z DATA VALID-3 tCPA tOEA tOEZ tOFF tOCH tOEZ tOEA tOCH tOEZ VIH VIL tODD tDZO 19 M5M44260CJ,TP-5,-5S : Under development tODD tDZO tORH tODD MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Fast Page Mode Byte Read Cycle tRP tRAS RAS VIH VIL tCSH tCRP UCAS (or LCAS) LCAS (or UCAS) tRCD tRSH tPC tCAS tCP tCAS tCP VIH VIL VIH VIL tCPRH tRAD tASR A0~A8 tCAS VIH VIL tASC tRAH tASC tCAH COLUMN ADDRESS1 ROW ADDRESS tCAH tASR tCAH tASC COLUMN ADDRESS3 COLUMN ADDRESS2 ROW ADDRESS tRAL tRCS W tRCH tRRH tRCH tRCS tRCH tRCS VIH VIL DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS) DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL Hi-Z tDZC tDZC tDZC DQ9~DQ16 VIH (or DQ1~DQ8) VIL (INPUTS) Hi-Z Hi-Z tOFF DATA VALID-1 tRAC tDZO tCPA DATA VALID-3 tCPA tOEA tOEA tOEZ tOFF tCLZ DATA VALID-2 tOEA tOCH OE tOFF tCLZ tCLZ Hi-Z tCAC tAA tCAC tAA tCAC tAA DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL tCDD tOCH tOEZ tOCH tOEZ VIH VIL tODD tDZO 20 M5M44260CJ,TP-5,-5S : Under development tODD tDZO tORH tODD MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Fast Page Mode Write Cycle (Early Write) tRAS RAS tRP VIH VIL tCSH tCRP tPC tCAS tRCD tCP tRSH tCAS tCP tCAS VIH LCAS/UCAS VIL tASR A0~A8 VIH VIL W DQ1~DQ16 (INPUTS) ROW ADDRESS tCAH tASC COLUMN ADDRESS1 tWCS tWCH tDS tDH tCAH COLUMN ADDRESS2 tWCS tWCH tDS tDH tASC tCAH COLUMN ADDRESS3 tWCS tWCH VIL VIH VIL VIH VIL 21 tASC VIH DQ1~DQ16 VOH (OUTPUTS) VOL OE tRAH M5M44260CJ,TP-5,-5S : Under development DATA VALID-2 DATA VALID-1 Hi-Z tDS tDH DATA VALID-3 tASR ROW ADDRESS MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Fast Page Mode Byte Write Cycle (Early Write) tRAS RAS tRP VIH VIL tCSH tCRP UCAS (or LCAS) VIH LCAS (or UCAS) VIH tCAS tCP tCAS VIL VIH VIL tRAH ROW ADDRESS tASC tASC tCAH COLUMN ADDRESS1 tWCS W tRSH tCAS tCP VIL tASR A0~A8 tPC tRCD tWCH tCAH COLUMN ADDRESS2 tWCS tASC tCAH COLUMN ADDRESS3 tWCH tWCS tWCH tDH tDS tDH VIH VIL DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS) DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL Hi-Z tDS DQ9~DQ16 VIH (or DQ1~DQ8) VIL (INPUTS) DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL OE VIH VIL 22 M5M44260CJ,TP-5,-5S : Under development tDH tDS DATA VALID-2 DATA VALID-1 Hi-Z DATA VALID-3 tASR ROW ADDRESS MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Fast-Page Mode Write Cycle (Delayed Write) tRP tRAS RAS VIH VIL tRSH tCSH tCRP tRCD tPC tCAS tCAS tCP VIH LCAS/UCAS VIL tASR A0~A8 VIH VIL tRAH tASC tCAH tASC ROW ADDRESS COLUMN ADDRESS1 tRWL tCWL tCAH ROW ADDRESS COLUMN ADDRESS2 tCWL tRCS tRCS tWP tWP W VIH VIL tWCH tWCH tDZC DQ1~DQ16 (INPUTS) VIH tDS Hi-Z tDH DATA VALID-1 VIL DQ1~DQ16 VOH (OUTPUTS) VOL tDZO VIL 23 M5M44260CJ,TP-5,-5S : Under development tDS Hi-Z tDH DATA VALID-2 Hi-Z Hi-Z VIH tDZC tCLZ tCLZ OE tASR Hi-Z tOEZ tOEZ tODD tDZO tODD tOEH MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Fast-Page Mode Byte Write Cycle (Delayed Write) tRP tRAS RAS VIH VIL tCSH tCRP tRCD tRSH tCAS tPC tCP UCAS (or LCAS) LCAS (or UCAS) VIH VIL VIH VIL tRWL tASR A0~A8 tCAS VIH VIL tRAH tASC ROW ADDRESS tASC tCAH tCAH tCWL ROW ADDRESS COLUMN ADDRESS2 COLUMN ADDRESS1 tCWL tRCS tRCS tWP tWP W tASR VIH VIL tWCH tWCH DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS) DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL Hi-Z tDZC DQ9~DQ16 VIH (or DQ1~DQ8) (INPUTS) VIL tDS Hi-Z tDH DATA VALID-1 VIL 24 M5M44260CJ,TP-5,-5S : Under development tDH DATA VALID-2 Hi-Z tOEZ tOEZ VIH Hi-Z Hi-Z Hi-Z tDZO OE tDS tCLZ tCLZ DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL tDZC tODD tDZO tODD tOEH MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Fast Page Mode Read-Write, Read-Modify-Write Cycle tRAS RAS tRP VIH VIL tRWL tCSH tCRP tPRWC tCAS tRCD tCP tCAS VIH LCAS/UCAS VIL tRAD tASR A0~A8 VIH VIL tRAH tASC tCAH tASC ROW ADDRESS tAWD tCWL tCWD ROW ADDRESS tAWD tRCS tCWD tWP W VIL tCPWD tDZC tDS Hi-Z VIH VIL tDH tCAC DQ1~DQ16 (OUTPUTS) VOL VIH VIL 25 M5M44260CJ,TP-5,-5S : Under development Hi-Z tCAC tDH DATA VALID-2 tCLZ Hi-Z Hi-Z DATA VALID-1 tRAC tDZO tDS tAA tCLZ VOH tDZC DATA VALID-1 tAA OE tWP VIH tRWD DQ1~DQ16 (INPUTS) tASR COLUMN ADDRESS2 COLUMN ADDRESS1 tRCS tCWL tCAH tCPA tODD tOEA tOEZ DATA VALID-2 tDZO tOEA Hi-Z tODD tOEZ tOEH MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Fast Page Mode Byte Read-Write, Read-Modify-Write Cycle tRP tRAS RAS VIH VIL tCSH tCRP UCAS (or LCAS) LCAS (or UCAS) tCP tRWL VIL VIH VIL VIH VIL tRAD tRAH tASC ROW ADDRESS tASC tCAH tCAH tCWL tASR COLUMN ADDRESS2 COLUMN ADDRESS1 tAWD tCWD tRCS ROW ADDRESS tAWD tCWD tCWL tWP W tPRWC tCAS VIH tASR A0~A8 tCAS tRCD tRCS tWP VIH VIL tRWD tCPWD DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS) DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL Hi-Z tDS tDZC DQ9~DQ16 VIH (or DQ1~DQ8) VIL (INPUTS) Hi-Z tDH tDZC Hi-Z DATA VALID-1 tCAC tAA OE VIH VIL 26 M5M44260CJ,TP-5,-5S : Under development DATA VALID-2 tCAC tCLZ Hi-Z Hi-Z DATA VALID-1 tRAC tDZO tDH tAA tCLZ DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL tDS tOEA tCPA tODD tOEZ Hi-Z DATA VALID-2 tDZO tOEA tODD tOEZ tOEH MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Self Refresh Cycle * (Note28) RAS tRPS tRASS tRP VIH VIL tRPC tRPC tCSR tCHS tCRP VIH LCAS/UCAS VIL tCPN tASR A0~A8 VIH ROW ADDRESS VIL tRCS tRCH W VIH VIL tCDD DQ1~DQ16 (INPUTS) VIH Hi-Z VIL tOFF DQ1~DQ16 VOH (OUTPUTS) VOL Hi-Z tOEZ tODD OE VIH VIL 27 M5M44260CJ,TP-5,-5S : Under development COLUMN ADDRESS MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Note 28 : Self refresh sequence Two refreshing methods should be used properly depending on the low pulse width (tRASS) of RAS signal during self refresh period. 1. Distributed refresh during Read/Write operation (A) Timing Diagram Read / Write Cycle Self Refresh Cycle tRASS≥100µs tNSD Read / Write Cycle tSND RAS last refresh cycle first refresh cycle Table 2 Read / Write Cycle Read / Write Self Refresh Self Refresh Read / Write CBR distributed refresh tNSD≤250µs tSND≤250µs RAS only distributed refresh tNSD≤16µs tSND≤16µs (B) Definition of distributed refresh tREF tREF / 512 tREF / 512 RAS refresh cycle read/write cycles refresh cycle Definition of CBR distributed refresh (Including extended refresh) The CBR distributed refresh performs more than 512 constant period (250µs max.) CBR cycles within 128 ms. Definition of RAS only distributed refresh All combinations of nine row address signals (A0~A8) are selected during 512 constant period (16µs max.) RAS only refresh cycles within 8.2 ms. Note: Hidden refresh may be used instead of CBR refresh. RAS/CAS refresh may be used instead of RAS only refresh. 1.1 CBR distributed refresh Switching from read/write operation to self refresh operation. The time interval from the falling edge of RAS signal in the last CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tNSD (shown in table 2). 28 M5M44260CJ,TP-5,-5S : Under development refresh cycle read/write cycles Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within tSND (shown in table 2). 1.2 RAS only distributed refresh Switching from read/write operation to self refresh operation. The time interval tNSD from the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 16µs. Switching from self refresh operation to read/write operation. The time interval tSND from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within 16µs. MITSUBISHI LSIs M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM 2. Burst refresh during Read/Write operation (A) Timing diagram Read / Write Read / Write Self Refresh tRASS≥100µs tNSB tSNB RAS first refresh cycles refresh cycles 511 cycles refresh cycles 511 cycles last refresh Cycles Table 3 Read / Write Cycle CBR burst refresh Read / Write Self Refresh tNSB≤8.2ms RAS only burst refresh Self Refresh Read / Write tSNB≤8.2ms tNSB+tSNB≤8.2ms (B) Definition of burst refresh 8.2ms RAS refresh cycles 512 cycles read/write cycles Definition of CBR burst refresh The CBR burst refresh performs more than 512 continuous CBR cycles within 8.2 ms. Definition of RAS only burst refresh All combination of nine row address signals (A0~A8) are selected during 512 continuous RAS only refresh cycles within 8.2 ms. 2.1 CBR burst refresh Switching from read/write operation to self refresh operation. The time interval tNSB from the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 8.2 ms. Switching from self refresh operation to read/write operation. The time interval tSNB from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last CBR refresh cycle during read/write operation period should be set within 8.2 ms. 29 M5M44260CJ,TP-5,-5S : Under development 2.2 RAS only burst refresh Switching from read/write operation to self refresh operation. The time interval from the falling edge of RAS signal in the first RAS only refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tNSB (shown in table 3). Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period should be set within tSNB (shown in table 3).