revision-K0.1e, ' 98.07.30 MITSUBISHI LSIs M5M5408BFP/TP/RT/KV/KR PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM FEATURES DESCRIPTION The M5M5408B is a family of 4-Mbit static RAMs organized as 524,288-words by 8-bit, fabricated by Mitsubishi's highperformance 0.25µm CMOS technology. The M5M5408B is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives. M5M5408B is packaged in 32-pin plastic SOP, 32-pin plastic TSOP and 32-pin 8mm x 13.4mm STSOP packages. Two types of TSOPs and two types of STSOPs are available , M5M5408BTP (normal-lead-bend TSOP) , M5M5408BRT (reverse-lead-bend TSOP) , M5M5408BKV (normal-lead-bend STSOP) and M5M5408BKR (reverse-lead-bend STSOP). These two types TSOPs and two types STSOPs are suitable for a surface mounting on double-sided printed circuit boards. From the point of operating temperature, the family is divided into three versions; "Standard", "W-version", and "I-version". Those are summarized in the part name table below. • Single +5V power supply • Small stand-by current: 0.4µA(3V,typ.) • No clocks, No refresh • Data retention supply voltage=2.0V to 5.5V • All inputs and outputs are TTL compatible. • Easy memory expansion by S • Common Data I/O • Three-state outputs: OR-tie capability • OE prevents data contention in the I/O bus • Process technology: 0.25µm CMOS • Package: M5M5408BFP: 32 pin 525 mil SOP M5M5408BTP/RT: 32 pin 400 mil TSOP(ll) M5M5408BKV/KR: 32 pin 8mm x 13.4mm STSOP PART NAME TABLE Version, Operating temperature Part name (## stands for "FP","TP", "RT","KV"or"KR") Power Supply M5M5408B## -70L 5.0V 100ns M5M5408B## -55H 55ns 5.0V 70ns 5.0V 70ns M5M5408B## -10LW 100ns M5M5408B## -55HW 55ns M5M5408B## -70HW 5.0V --- 50µA --- 0.4µA 10µA --- --- --- 100µA 70ns 0.4µA --- 20µA --- --- 100µA 0.4µA --- 20µA 50mA (10MHz) 25mA (1MHz) 55ns M5M5408B## -55LI 5.0V 70ns 100ns M5M5408B## -10LI 55ns M5M5408B## -55HI M5M5408B## -70HI 85°C 100ns M5M5408B## -10HW M5M5408B## -70LI 70°C 55ns M5M5408B## -55LW M5M5408B## -70LW 25°C Active current Icc1 (5.0V, typ.) 100ns M5M5408B## -10H I-version -40 ~ +85°C 70ns M5M5408B## -10L M5M5408B## -70H W-version -20 ~ +85°C max. Stand-by current Icc(PD), Vcc=3.0V typical * Ratings (max.) 55ns M5M5408B## -55L Standard 0 ~ +70°C Access time 5.0V 70ns 100ns M5M5408B## -10HI * "typical" parameter is sampled, not 100% tested. MITSUBISHI ELECTRIC 1 revision-K0.1e, ' 98.07.30 MITSUBISHI LSIs M5M5408BFP/TP/RT/KV/KR PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM PIN CONFIGURATION (TOP VIEW) A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 (0V) GND 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 Outline A11 A9 A8 A13 W A18 A15 Vcc A17 A16 A14 A12 A7 A6 A5 A4 A15 A17 W A13 A8 A9 A11 OE A10 S DQ8 DQ7 DQ6 DQ5 DQ4 32P2M-A (FP) 32P3Y-H (TP) 32 2 3 31 30 4 5 29 28 6 7 27 26 M5M5408BKV 10 25 24 23 22 21 11 12 13 20 19 14 15 18 17 16 Outline 32P3K-B 32 1 31 2 30 3 29 4 28 5 27 6 26 7 25 8 24 9 23 10 22 11 21 12 20 13 19 14 18 15 17 16 Outline 1 8 9 (5V) VCC VCC (5V) A15 A17 W A13 A8 A9 A11 OE A10 S DQ8 DQ7 DQ6 DQ5 DQ4 OE A10 S DQ8 DQ7 DQ6 DQ5 DQ4 GND DQ3 DQ2 DQ1 A0 A1 A2 A3 A4 A5 A6 A7 A12 A14 A16 A17 Vcc A15 A18 W A13 A8 A9 A11 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 GND (0V) 32P3Y-J (RT) 16 15 17 18 14 19 13 20 12 21 11 22 23 10 9 M5M5408BKR 8 7 24 25 26 27 6 5 28 4 3 29 2 1 31 30 32 A3 A2 A1 A0 DQ1 DQ2 DQ3 GND DQ4 DQ5 DQ6 DQ7 DQ8 S A10 OE Outline 32P3K-C MITSUBISHI ELECTRIC 2 revision-K0.1e, ' 98.07.30 MITSUBISHI LSIs M5M5408BFP/TP/RT/KV/KR PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM FUNCTION The M5M5408BFP,TP,RT,KV,KR is organized as 524,288words by 8-bit. These devices operate on a single +5.0V power supply, and are directly TTL compatible to both input and output. Its fully static circuit needs no clocks and no refresh, and makes it useful. A write operation is executed during the S low and W low overlap time. The address(A0~A18) must be set up before the write cycle A read operation is executed by setting W at a high level and OE at a low level while S are in an active state(S=L). When setting S at a high level, the chips are in a nonselectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips. Setting the OE at a high level,the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. The power supply current is reduced as low as 0.4µA(25°C, typical), and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode. Pin FUNCTION TABLE A0 ~ A18 S W OE H L X L X X L L H H L H Mode Non selection Icc DQ Function Address input DQ1 ~ DQ8 Data input / output Chip select input High-impedance Standby S W Read Data input (D) Data output (Q) Active Read Active Active OE Vcc Output inable input High-impedance GND Ground supply Write Write control input Power supply BLOCK DIAGRAM M5M5408B FP/TP/RT M5M5408BKV/KR M5M5408BKV/KR M5M5408B FP/TP/RT A4 A5 8 16 7 15 21 13 A6 A7 6 14 22 14 5 13 23 15 A12 4 12 25 17 26 18 MEMORY ARRAY 524288 WORDS x 8 BITS DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 A14 A16 3 11 2 10 27 19 A17 A18 30 9 28 20 1 6 29 21 A15 31 7 A10 23 31 A11 25 1 A9 A8 26 2 27 3 A13 28 4 5 29 W 30 22 S 32 24 OE 8 32 A0 12 20 A1 11 19 A2 A3 10 18 9 17 CLOCK GENERATOR VCC (3V) 24 16 GND (0V) MITSUBISHI ELECTRIC 3 revision-K0.1e, ' 98.07.30 MITSUBISHI LSIs M5M5408BFP/TP/RT/KV/KR PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI VO Pd Parameter Conditions Supply voltage With respect to GND Input voltage With respect to GND Output voltage With respect to GND Power dissipation Ta Operating temperature Tstg Storage temperature Ratings -0.3* ~ +7 -0.3* ~ Vcc + 0.3 0 ~ Vcc 700 0 ~ +70 -20 ~ +85 -40 ~ +85 -65 ~150 Ta=25°C Standard (-L, -H) W-version (-LW, -HW) I-version (-LI, -HI) Units V mW °C °C * -3.0V in case of AC (Pulse width ≤ 30ns) DC ELECTRICAL CHARACTERISTICS Symbol ( Vcc=5V±10%, unless otherwise noted) Limits Parameter Conditions Min VIH VIL VOH1 VOH2 VOL II High-level input voltage 2.2 Low-level input voltage -0.3 * 2.4 IO Output leakage current IOL=2mA VI =0 ~ Vcc S=VIH or OE=VIH, VI/O=0 ~ Vcc Icc1 Active supply current ( AC,MOS level ) S ≤0.2V Output-open Other inputs ≤0.2V or ≥Vcc-0.2V minimum cycle Output-open S=VIL Other inputs=VIH or VIL minimum cycle Icc2 Active supply current ( AC,TTL level ) Icc3 Stand by supply current ( AC,MOS level ) S ≥Vcc-0.2V Other inputs=0~Vcc Icc4 Stand by supply current ( AC,TTL level ) S=V ,Other inputs= 0 ~ Vcc High-level output voltage 1 IOH= -1mA High-level output voltage 2 IOH= -0.1mA Low-level output voltage Input leakage current Note 1: Direction for current flowing into IC is indicated as positive (no mark) Note 2: Typical value is for Vcc=5.0V and Ta=25°C CAPACITANCE CI CO Parameter Input capacitance Output capacitance Max Units Vcc+0.3V 0.8 V Vcc-0.5V 0.4 ±1 ±1 f= 1MHz f= 1MHz -LW, -LI Symbol Typ -L -HW, -HI -H - 50 25 60 30 0.4 0.4 - - 80 30 90 40 200 100 40 20 3 µA mA µA mA * -3.0V in case of AC (Pulse width ≤ 50ns) (Vcc=5.0V±10%, unless otherwise noted) Conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz MITSUBISHI ELECTRIC Min Limits Typ Max 8 10 Units pF 4 revision-K0.1e, ' 98.07.30 MITSUBISHI LSIs M5M5408BFP/TP/RT/KV/KR PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (Vcc=5.0V±10%, unless otherwise noted) (1) TEST CONDITIONS Supply voltage 5.0V Input pulse VIH=2.4V,VIL=0.6V (FP,TP,RT,KV,KR-70,-10 ) VIH=3.0V,VIL=0V (FP,TP,RT,KV,KR-55 ) Input rise time and fall time 5ns Reference level VOH=VOL=1.5V Transition is measured ±500mV from steady state voltage.(for ten,tdis) Output loads Fig.1, CL=100pF (FP,TP,RT,KV,KR-70,-10 ) CL=30pF (FP,TP,RT,KV,KR-55 ) CL=5pF (for ten,tdis) 1.8kΩ DQ 990Ω CL CL Including scope and jig capacitance Fig.1 Output load (2) READ CYCLE Limits M5M5408BFP,TP,RT, KV,KR-55 Parameter Symbol Min tCR ta(A) ta(S) ta(OE) tdis(S) tdis(OE) ten(S) ten(OE) tV(A) Max 55 Read cycle time Address access time Chip select access time M5M5408BFP,TP,RT, M5M5408BFP,TP,RT, KV,KR-70 KV,KR-10 Min Max Output disable time after S high Output disable time after OE high 100 100 50 35 35 70 70 35 25 25 Output enable time after S low 10 10 10 Output enable time after OE low Data valid time after address 5 10 5 10 5 10 Units Max 100 70 55 55 25 20 20 Output enable access time Min ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE Limits Symbol M5M5408BFP,TP,RT, KV,KR-55 Parameter Min tCW tw(W) tsu(A) tsu(A-WH) tsu(S) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) Write cycle time Write pulse width Address set up time Address set up time with respect to W high Chip select set up time Data set up time Data hold time Write recovery time Max Min 70 50 0 100 60 0 50 50 25 0 60 60 30 0 80 80 35 0 0 5 5 25 25 5 5 MITSUBISHI ELECTRIC 35 35 5 5 Units Max 0 0 20 20 Output disable time after OE high Output enable time after OE low Min 55 40 0 Output disable time after W low Output enable time after W high Max M5M5408BFP,TP,RT, M5M5408BFP,TP,RT, KV,KR-10 KV,KR-70 ns ns ns ns ns ns ns ns ns ns ns ns 5 revision-K0.1e, ' 98.07.30 MITSUBISHI LSIs M5M5408BFP/TP/RT/KV/KR PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM (4)TIMING DIAGRAMS Read cycle tCR A0~18 ta(A) tv (A) ta(S) S tdis (S) (Note3) (Note3) ta (OE) OE ten (OE) (Note3) W = "H" level (Note3) ten (S) tdis (OE) DQ1~8 VALID DATA Write cycle ( W control mode ) tCW A0~18 tsu (S) S (Note3) (Note3) tsu (A-WH) OE tsu (A) tw (W) trec (W) W ten(OE) tdis (W) tdis(OE) DQ1~8 ten (W) DATA IN STABLE tsu (D) th (D) MITSUBISHI ELECTRIC 6 revision-K0.1e, ' 98.07.30 MITSUBISHI LSIs M5M5408BFP/TP/RT/KV/KR PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM Write cycle (S control mode) tCW A0~18 tsu (S) tsu (A) trec (W) S (Note5) W (Note4) (Note3) (Note3) tsu (D) DQ1~8 th (D) DATA IN STABLE Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during the overlap of a low S and a low W. Note 5: If W goes low simultaneously with or prior to S,the output remains in the high impedance state. Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode. MITSUBISHI ELECTRIC 7 revision-K0.1e, ' 98.07.30 MITSUBISHI LSIs M5M5408BFP/TP/RT/KV/KR PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Parameter Test conditions Min 2 Vcc (PD) Power down supply voltage Vcc(PD) ≥ 2.2V Chip select input S VI (S) 2.2V ≥ Vcc(PD) ≥ 2.0V -LW, -LI Icc (PD) Power down supply current -L Vcc=3.0V, S≥Vcc-0.2V, Other inputs=0 ~ Vcc -HW, -HI -H 2.2 - Limits Typ. Max - - V Vcc(PD) - V - 100 50 20 10 µA µA µA µA 0.4 0.4 Units V Typical value is for Ta=25°C (2) TIMING REQUIREMINTS Limits Symbol Parameter tsu (PD) trec (PD) Power down set up time Power down recovery time Test conditions Min Typ 0 5 Max Units ns ms (3) TIMING DIAGRAM S control mode Vcc tsu (PD) 4.5V 4.5V trec (PD) 2.2V S 2.2V S≥Vcc - 0.2V MITSUBISHI ELECTRIC 8 revision-K0.1e, ' 98.07.30 MITSUBISHI LSIs M5M5408BFP/TP/RT/KV/KR PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM Revision History Revision No. K0.1e History Date The first edition '98.7.30 MITSUBISHI ELECTRIC Preliminary 9