MITSUBISHI LSIs M5M5V4R08J-12,-15,-20 PRELIMINARY 1997.02.06 Rev.D Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM DESCRIPTION FEATURES • Fast access time M5M5V4R08J-12 •••• 12ns(max) M5M5V4R08J-15 •••• 15ns(max) M5M5V4R08J-20 •••• 20ns(max) • Low power dissipation Active •••••••••• 363mW(typ) Stand by ••••••• 3.3mW(typ) • Single +3.3V power supply • Fully static operation : No clocks, No refresh • Common data I/O • Easy memory expansion by S • Three-state outputs : OR-tie capability • OE prevents data contention in the I/O bus • Directly TTL compatible : All inputs and outputs PIN CONFIGURATION (TOP VIEW) A0 A1 address A2 inputs A3 A4 chip select S input data inputs/ DQ1 outputs DQ2 (3.3V) VCC (0V) GND data DQ3 inputs/ DQ4 outputs write control W input A5 A6 address A7 inputs A8 A9 1 36 2 35 3 34 4 33 5 32 M5M5V4R08J The M5M5V4R08J is a family of 524288-word by 8-bit static RAMs, fabricated with the high performance CMOS silicon gate process and designed for high speed application. The M5M5V4R08J is offered in a 36-pin plastic small outline J-lead package(SOJ). These device operate on a single 3.3V supply, and are directly TTL compatible. They include a power down feature as well. 6 7 8 9 10 11 12 13 PACKAGE High-speed memory units 36pin 400mil SOJ 30 29 28 27 26 25 24 14 23 15 22 16 21 17 20 18 19 Outline APPLICATION 31 NC A18 A17 address inputs A16 A15 output enable OE input data DQ8 inputs/ DQ7 outputs GND (0V) VCC (3.3V) DQ6 data inputs/ DQ5 outputs A14 A13 address A12 inputs A11 A10 NC 36P0K (SOJ) BLOCK DIAGRAM A3 3 4 A4 5 A5 14 A6 15 A7 16 A8 17 S W MEMORY ARRAY 512 ROWS 8192 COLUMNS COLUMN I/O CIRCUITS 6 13 COLUMN COLUMNADDRESS DECODERS ADDRESS DECODERS COLUMN INPUT BUFFERS OE 31 OUTPUT BUFFERS 2 DATA INPUT BUFFERS A1 A2 7 ROW ADDRESS DECODERS 1 ROW INPUT BUFFERS address inputs A0 DQ1 8 DQ2 11 DQ3 12 DQ4 25 DQ5 26 DQ6 29 DQ7 30 DQ8 data inputs/ outputs 9 27 10 28 VCC (3.3V) GND (0V) 18 20 21 22 23 24 32 33 34 35 A9 A10 A11 A12 A13 A14 A15 A16 A16 A17 address inputs MITSUBISHI ELECTRIC 1 MITSUBISHI LSIs M5M5V4R08J-12,-15,-20 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM FUNCTION The operation mode of the M5M5V4R08J is determined by a combination of the device control inputs S, W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S. The address must be set-up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W or S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and OE at a low level while S are in an active state (S=L). When setting S at high level, the chip is in a non-selectable mode in which both reading and writing are disable. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by S. Signal-S controls the power-down feature. When S goes high, power dissapation is reduced extremely. The access time from S is equivalent to the address access time. FUNCTION TABLE Mode Non selection DQ High-impedance Icc Stand by X Write Din L Read Dout Active Active High-impedance Active S H W X OE X L L L H L H H ABSOLUTE MAXIMUM RATINGS Symbol V cc VI Parameter Conditions Ratings Supply voltage -2.0 ~ 4.6 Input voltage VO Output voltage Pd Power dissipation T opr Operating temperature Unit * With respect to GND V * V * -2.0 ~ VCC+0.5 V 1000 mW -2.0 ~ VCC+0.5 Ta=25 C 0 ~ 70 C Tstg(bias) Storage temperature(bias) -10 ~ 85 C T stg -65 ~ 150 C Storage temperature *Pulse width ≤ 20ns, In case of DC:-0.5V DC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70 C, Vcc=3.3V Symbol VIH VIL VOH VOL II +10% -5% unless otherwise noted) Limits Condition Parameter I OZ High-level input voltage Low-level input voltage High-level output voltage IOH =-4mA Low-level output voltage IOL= 8mA Input current V I = 0~Vcc VI (S)= VIH Output current in off-state VO= 0~Vcc I CC1 Active supply current (TTL level) Min Typ I CC2 Stand by current (TTL level) VI (S)= VIH I CC3 Stand by current VI (S)= Vcc≥0.2V other inputs VI≤0.2V or VI≥Vcc-0.2V 12ns cycle AC 15ns cycle 20ns cycle DC 12ns cycle AC 15ns cycle 20ns cycle DC 110 1 Unit 0.4 2 V V V V µA 10 µA Vcc+0.3 0.8 2.0 -0.3* 2.4 VI (S)= VIL other inputs VIH or VIL Output-open(duty 100%) Max 170 160 150 120 85 80 75 60 10 mA mA mA *Pulse width ≤ 20ns, in case of AC :-3.0V MITSUBISHI ELECTRIC 2 MITSUBISHI LSIs M5M5V4R08J-12,-15,-20 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM CAPACITANCE (Ta=0 ~ 70 C, Vcc=3.3V Symbol +10% -5% unless otherwise noted) Parameter Test Condition Min Limit Typ Max Unit CI Input capacitance V I =GND, V I =25mVrms,f=1MHz 7 pF CO Output capacitance V O=GND, VO =25mVrms,f=1MHz 8 pF Note 1: Direction for current flowing into an IC is positive (no mark). 2: Typical value is Vcc=5V,Ta=25 C 3: CI,CO are periodically sampled and are not 100% tested. AC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70 C, Vcc=3.3V +10% -5% unless otherwise noted) (1)MEASUREMENT CONDITION Input pulse levels •••••••••••••••••••••••• VIH =3.0V, V IL =0.0V Input rise and fall time •••••••••••••••••••••••••••••••••••••• 3ns Input timing reference levels •••••••••••• V IH =1.5V, VIL =1.5V Output timing reference levels •••••••••• VOH =1.5V, VOL =1.5V Output loads •••••••••••••••••••••••••••••••••••••••••• Fig1,Fig2 Vcc OUTPUT Z0=50Ω 480Ω DQ 255Ω RL=50Ω 5pF (including scope and JIG) VL=1.5V Fig.1 Output load Fig.2 Output load for ten , t dis MITSUBISHI ELECTRIC 3 MITSUBISHI LSIs M5M5V4R08J-12,-15,-20 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM (2)READ CYCLE Limits Symbol Parameter M5M5V4R08J -12 Max Min M5M5V4R08J -15 Max Min M5M5V4R08J -20 Min Unit Max tCR Read cycle time ta(A) Address access time 12 15 20 ns ta(S) Chip select access time 12 15 Output enable access time 6 8 20 10 ns ta(OE) tdis(S) Output disable time after S high 0 6 0 7 0 8 ns tdis (OE) Output disable time after OE high 0 6 0 7 0 8 ns ten(S) Output enable time after S low 0 0 0 ns ten (OE) Output enable time after OE low 0 0 0 ns tv(A) Data valid time after address change 3 3 3 ns tPU Power-up time after chip selection 0 0 0 ns tPD Power-down time after chip selection 12 15 12 20 15 ns 20 ns ns (3)WRITE CYCLE Limits Symbol Parameter M5M5V4R08J -12 Min Max M5M5V4R08J -15 Min Max M5M5V4R08J -20 Min Unit Max tCW Write cycle time 12 15 20 ns tw(W) Write pulse width 10 12 15 ns tsu (A)1 Address setup time(W) 0 0 0 ns tsu (A)2 Address setup time(S) 0 0 0 ns tsu(S) Chip select setup time 10 12 15 ns tsu (D) Data setup time 6 7 8 ns th(D) Data hold time 0 0 0 ns trec(W) Write recovery time 0 0 0 ns tdis (W) Output disable time after W low 0 6 0 7 0 8 ns tdis Output disable time after OE high 0 6 0 7 0 8 ns ten (W) Output enable time after W high 0 0 0 ns ten (OE) Output enable time after OE low 0 0 0 ns tsu(A-WH) Address to W High 10 12 15 ns (OE) MITSUBISHI ELECTRIC 4 MITSUBISHI LSIs M5M5V4R08J-12,-15,-20 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM (4)TIMING DIAGRAMS Read cycle 1 A 0~18 t CR VIH VIL ta(A) tv (A) tv (A) DQ1~8 VOH PREVIOUS DATA VALID VOL UNKNOWN DATA VALID W=H S=L OE=L Read cycle 2 (Note 4) t CR VIH S VIL tdis(S) ta(S) (Note 5) ten (S) DQ1~8 VOH UNKNOWN DATA VALID VOL tPU ICC1 Icc (Note 5) tPD 50% ICC2 50% W=H OE=L Note 4. Addresses valid prior to or coincident with S transition low. 5. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2. Read cycle 3 (Note 6) t CR VIH OE VIL ta (OE) (Note 5) DQ1~8 VOH tdis(OE) (Note 5) ten (OE) UNKNOWN DATA VALID VOL W=H S=L Note 6. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE)) MITSUBISHI ELECTRIC 5 MITSUBISHI LSIs M5M5V4R08J-12,-15,-20 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM Write cycle ( W control mode ) t CW A 0~18 S VIH VIL tsu(S) VIH VIL (Note7) (Note7) tsu (A-WH) OE VIH VIL tsu(A) W tw(W) trec (W) VIH VIL tsu(D) th(D) DQ1~8 (Input Data) VIH DATA STABLE VIL tdis(W) (Note 5) ten(OE) ten(W) tdis(OE) DQ1~8 (Output Data) (Note 5) VOH VOL Hi-Z Write cycle (S control mode ) t CW A 0~18 VIH VIL tsu(A) tsu (S) trec (W) VIH S VIL tw(W) VIH W VIL (Note7) (Note7) tsu (D) DQ1~8 (Input Data) VIH th (D) DATA STABLE VIL tdis(W) DQ1~8 (Output Data) VOH VOL ten (S) (Note5) (Note5) Hi-Z (Note8) Note 7: Hatching indicates the state is don't care. 8: When the falling edge of W is simultaneous or prior to the falling edge of S, the output is maintained in the high impedance. 9: ten,tdis are periodically sampled and are not 100% tested. MITSUBISHI ELECTRIC 6