revision-K1.0e, ' 98.09.07 MITSUBISHI LSIs M5M5V408BFP/TP/RT/KV/KR 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM FEATURES DESCRIPTION The M5M5V408B is a family of low voltage 4-Mbit static RAMs organized as 524,288-words by 8-bit, fabricated by Mitsubishi's highperformance 0.25µm CMOS technology. The M5M5V408B is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives. M5M5V408B is packaged in 32-pin plastic SOP, 32-pin plastic TSOP and 32-pin 8mm x 13.4mm STSOP packages. Two types of TSOPs and two types of STSOPs are available, M5M5V408BTP (normal-lead-bend TSOP), M5M5V408BRT (reverse-lead-bend TSOP), M5M5V408BKV (normal-lead-bend STSOP) and M5M5V408BKR (reverse-lead-bend STSOP). These two types TSOPs and two types STSOPs are suitable for a surface mounting on double-sided printed circuit boards. From the point of operating temperature, the family is divided into three versions; "Standard", "W-version", and "I-version". Those are summarized in the part name table below. • Single +2.7~+3.6V power supply • Small stand-by current: 0.3µA(3V,typ.) • No clocks, No refresh • Data retention supply voltage=2.0V to 3.6V • All inputs and outputs are TTL compatible. • Easy memory expansion by S • Common Data I/O • Three-state outputs: OR-tie capability • OE prevents data contention in the I/O bus • Process technology: 0.25µm CMOS • Package: M5M5V408BFP: 32 pin 525 mil SOP M5M5V408BTP/RT: 32 PIN 400mil TSOP(ll) M5M5V408BKV/KR: 32 pin 8mm x13.4mm STSOP PART NAME TABLE Version, Operating temperature Part name (## stands for "FP","TP", "RT","KV"or"KR") Power Supply M5M5V408B## -85L Standard 0 ~ +70°C M5M5V408B## -10L M5M5V408B## -85H 2.7 ~ 3.6V 2.7 ~ 3.6V M5M5V408B## -10H M5M5V408B## -10LW M5M5V408B## -85HW M5M5V408B## -10HW 2.7 ~ 3.6V 2.7 ~ 3.6V M5M5V408B## -85LI I-version -40 ~ +85°C M5M5V408B## -10LI 2.7 ~ 3.6V M5M5V408B## -85HI M5M5V408B## -10HI Stand-by current Icc(PD), Vcc=3.0V typical * Ratings (max.) max. 25°C 40°C 25°C 40°C 70°C 85°C 85ns 100ns 85ns --- --- 0.3µA 1µA --- --- 20µA --- 1µA 3µA 10µA --- 100ns M5M5V408B## -85LW W-version -20 ~ +85°C Access time 2.7 ~ 3.6V 85ns 100ns 85ns 100ns 85ns 100ns 85ns --- --- 0.3µA 1µA --- --- 0.3µA 1µA --- --- 20µA 40µA 1µA 3µA 10µA 20µA --- --- 20µA 40µA 1µA 3µA 10µA 20µA Active current Icc1 (3.0V, typ.) 30mA (10MHz) 5mA (1MHz) 100ns * "typical" parameter is sampled, not 100% tested. MITSUBISHI ELECTRIC 1 revision-K1.0e, ' 98.09.07 MITSUBISHI LSIs M5M5V408BFP/TP/RT/KV/KR 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM PIN CONFIGURATION (TOP VIEW) A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 GND 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 Outline A11 A9 A8 A13 W A18 A15 Vcc A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VCC A15 A17 W A13 A8 A9 A11 OE A10 S DQ8 DQ7 DQ6 DQ5 DQ4 VCC A15 A17 W A13 A8 A9 A11 OE A10 S DQ8 DQ7 DQ6 DQ5 DQ4 32P2M-A (FP) 32P3Y-H (TP) M5M5V408BKV Outline 32P3K-B 32 1 31 2 30 3 29 4 28 5 27 6 26 7 25 8 24 9 23 10 22 11 21 12 20 13 19 14 18 15 17 16 Outline 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 S DQ8 DQ7 DQ6 DQ5 DQ4 GND DQ3 DQ2 DQ1 A0 A1 A2 A3 A4 A5 A6 A7 A12 A14 A16 A17 Vcc A15 A18 W A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 GND 32P3Y-J (RT) M5M5V408BKR 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 DQ1 DQ2 DQ3 GND DQ4 DQ5 DQ6 DQ7 DQ8 S A10 OE Outline 32P3K-C MITSUBISHI ELECTRIC 2 revision-K1.0e, ' 98.09.07 MITSUBISHI LSIs M5M5V408BFP/TP/RT/KV/KR 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM FUNCTION The M5M5408BFP,TP,RT,KV,KR is organized as 524,288words by 8-bit. These devices operate on a single +2.7~3.6V power supply, and are directly TTL compatible to both input and output. Its fully static circuit needs no clocks and no refresh, and makes it useful. A write operation is executed during the S low and W low overlap time. The address(A0~A18) must be set up before the write cycle A read operation is executed by setting W at a high level and OE at a low level while S are in an active state(S=L). When setting S at a high level, the chips are in a nonselectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips. Setting the OE at a high level,the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. The power supply current is reduced as low as 0.3µA(25°C, typical), and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode. Pin FUNCTION TABLE A0 ~ A18 S W OE H L X L X X L L H H L H Mode Non selection Icc DQ Function Address input DQ1 ~ DQ8 Data input / output Chip select input High-impedance Standby S Read High-impedance W OE Vcc Write control input Read Data input (D) Data output (Q) Active GND Ground supply Write Active Active Output inable input Power supply BLOCK DIAGRAM M5M5V408B FP/TP/RT M5M5V408BKV/KR M5M5V408B FP/TP/RT M5M5V408BKV/KR A4 A5 8 16 7 15 21 13 A6 A7 6 14 22 14 5 13 23 15 A12 4 12 25 17 A14 A16 3 11 26 18 2 10 27 19 A17 A18 30 9 28 20 1 6 29 21 A15 31 7 A10 23 31 A11 25 1 A9 A8 26 2 27 3 A13 28 4 5 29 W 30 22 S 32 24 OE 8 32 VCC 24 16 GND A0 12 20 A1 11 19 A2 A3 10 18 9 17 MEMORY ARRAY 524288 WORDS x 8 BITS DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 CLOCK GENERATOR (3V) (0V) MITSUBISHI ELECTRIC 3 revision-K1.0e, ' 98.09.07 MITSUBISHI LSIs M5M5V408BFP/TP/RT/KV/KR 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI VO Pd Ta Tstg Parameter Conditions Supply voltage With respect to GND Input voltage With respect to GND Output voltage With respect to GND Power dissipation Operating temperature Ratings Ta=25°C Standard (-L, -H) W-version (-LW, -HW) I-version (-LI, -HI) Units -0.5* ~ +4.6 -0.5* ~ Vcc + 0.5 0 ~ Vcc 700 0 ~ +70 -20 ~ +85 -40 ~ +85 -65 ~150 Storage temperature V mW °C °C * -3.0V in case of AC (Pulse width ≤ 30ns) DC ELECTRICAL CHARACTERISTICS Symbol VIH VIL VOH1 VOH2 VOL II ( Vcc=2.7 ~ 3.6V, unless otherwise noted) Limits Parameter Conditions Min High-level input voltage 2.2 Low-level input voltage -0.3 * 2.4 High-level output voltage 1 IOH= -0.5mA High-level output voltage 2 IOH= -0.05mA IOL=2mA VI =0 ~ Vcc S=VIH or OE=VIH, VI/O=0 ~ Vcc Icc1 Active supply current ( AC,MOS level ) S ≤0.2V Output-open Other inputs ≤0.2V or ≥Vcc-0.2V f= 10MHz f= 1MHz Icc2 Active supply current ( AC,TTL level ) Output-open S=VIL Other inputs=VIH or VIL f= 10MHz f= 1MHz IO - -LW, -LI +70 ~ +85°C +70°C Icc3 ( AC,MOS level ) -HW, -HI +70 ~ +85°C +40 ~ +70°C -H, -HW, -HI Other inputs=0~Vcc +25 ~ +40°C -H 0 ~ +25°C S ≥Vcc-0.2V -HW -20 ~ +25°C -HI Icc4 Stand by supply current ( AC,TTL level ) CAPACITANCE CI CO Parameter Input capacitance Output capacitance -40 ~ +25°C S=V ,Other inputs= 0 ~ Vcc Note 1: Direction for current flowing into IC is indicated as positive (no mark) Note 2: Typical value is for Vcc=3.0V and Ta=25°C Symbol Units Vcc+0.3V 0.6 V 0.4 ±1 ±1 -L, -LW, -LI Stand by supply current Max Vcc-0.5V Input leakage current Output leakage current Low-level output voltage Typ - 30 5 30 5 - 40 7 40 7 48 24 24 12 - 1 0.3 0.3 0.3 3.6 1.2 1.2 1.2 - - 0.5 µA mA µA mA * -3.0V in case of AC (Pulse width ≤ 30ns) (Vcc=2.7 ~ 3.6V, unless otherwise noted) Conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz Min MITSUBISHI ELECTRIC Limits Typ Max 8 10 Units pF 4 revision-K1.0e, ' 98.09.07 MITSUBISHI LSIs M5M5V408BFP/TP/RT/KV/KR 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (Vcc=2.7 ~ 3.6V, unless otherwise noted) (1) TEST CONDITIONS Supply voltage Input pulse Input rise time and fall time 2.7V~3.6V VIH=2.4V,VIL=0.4V 5ns 1TTL DQ CL VOH=VOL=1.5V Reference level Including scope and jig capacitance Transition is measured ±500mV from steady state voltage.(for ten,tdis) Fig.1,CL=30pF CL=5pF (for ten,tdis) Output loads Fig.1 Output load (2) READ CYCLE Limits Parameter Symbol tCR ta(A) ta(S) ta(OE) tdis(S) tdis(OE) ten(S) ten(OE) tV(A) M5M5V408B FP,TP,RT,KV,KR-85 M5M5V408B FP,TP,RT,KV,KR-10 Min Min Max 85 Read cycle time Address access time Chip select access time 100 85 85 45 30 30 Output enable access time Output disable time after S high Output disable time after OE high Output enable time after S low 10 Output enable time after OE low Data valid time after address 5 10 Units Max 100 100 50 35 35 10 5 10 ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE Limits Symbol M5M5V408B FP,TP,RT,KV,KR-85 Parameter Min tCW tw(W) tsu(A) tsu(A-WH) tsu(S) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) Write cycle time Write pulse width Address set up time Address set up time with respect to W high Chip select set up time Data set up time Data hold time Write recovery time 100 75 0 70 70 35 0 85 85 40 0 0 5 5 35 35 5 5 MITSUBISHI ELECTRIC Units Max 0 30 30 Output disable time after OE high Output enable time after OE low Min 85 60 0 Output disable time after W low Output enable time after W high Max M5M5V408B FP,TP,RT,KV,KR-10 ns ns ns ns ns ns ns ns ns ns ns ns 5 revision-K1.0e, ' 98.09.07 MITSUBISHI LSIs M5M5V408BFP/TP/RT/KV/KR 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM (4)TIMING DIAGRAMS Read cycle tCR A0~18 ta(A) tv (A) ta(S) S tdis (S) (Note3) (Note3) ta (OE) OE (Note3) ten (OE) W = "H" level (Note3) ten (S) tdis (OE) DQ1~8 VALID DATA Write cycle ( W control mode ) tCW A0~18 tsu (S) S (Note3) (Note3) tsu (A-WH) OE tsu (A) tw (W) trec (W) W ten(OE) tdis (W) tdis(OE) DQ1~8 ten (W) DATA IN STABLE tsu (D) th (D) MITSUBISHI ELECTRIC 6 revision-K1.0e, ' 98.09.07 MITSUBISHI LSIs M5M5V408BFP/TP/RT/KV/KR 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM Write cycle (S control mode) tCW A0~18 tsu (S) tsu (A) trec (W) S (Note5) W (Note4) (Note3) (Note3) tsu (D) DQ1~8 th (D) DATA IN STABLE Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during the overlap of a low S and a low W. Note 5: If W goes low simultaneously with or prior to S,the output remains in the high impedance state. Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode. MITSUBISHI ELECTRIC 7 revision-K1.0e, ' 98.09.07 MITSUBISHI LSIs M5M5V408BFP/TP/RT/KV/KR 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Parameter Test conditions Min Vcc (PD) Power down supply voltage Chip select input S VI (S) -LW, -LI +70 ~ +85°C -L, -LW, -LI +70°C -HW, -HI +70 ~ +85°C Icc (PD) Power down supply current Vcc=3.0V, S≥Vcc-0.2V, Other inputs=0 ~ Vcc -H, -HW, -HI +40 ~ +70°C - - 1 0.3 0.3 0.3 0 ~ +25°C -20 ~ +25°C -HW -HI -40 ~ +25°C Max Units V 2.0 2.0 - +25 ~ +40°C -H Limits Typ V 40 20 20 10 3 1 1 1 µA µA µA µA µA µA µA µA Typical value is for Ta=25°C (2) TIMING REQUIREMINTS Symbol Parameter Test conditions tsu (PD) trec (PD) Power down set up time Power down recovery time Limits Min Typ 0 5 Max Units ns ms (3) TIMING DIAGRAM S control mode Vcc tsu (PD) 2.7V 2.7V trec (PD) 2.2V S 2.2V S≥Vcc - 0.2V MITSUBISHI ELECTRIC 8 revision-K1.0e, ' 98.09.07 MITSUBISHI LSIs M5M5V408BFP/TP/RT/KV/KR 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM Revision History Revision No. K0.1e K0.2e K1.0e History Date The first edition Added M5M5V408BFP/TP/RT The first product version '98.3.05 '98.7.30 '98.9.7 MITSUBISHI ELECTRIC Preliminary Preliminary 9 E HE 1 32 b EIAJ Package Code SOP32-P-525-1.27 D e JEDEC Code – y 16 17 Weight(g) 1.29 A Lead Material Alloy 42 L1 32P2M-A A2 c Detail F F A1 e1 L b2 b2 e1 I2 A A1 A2 b c D E e HE L L1 y Symbol Mar.’98 Dimension in Millimeters Min Nom Max – – 3.05 0 0.1 0.2 – 2.75 – 0.35 0.4 0.5 0.13 0.15 0.2 20.55 20.75 20.95 11.3 11.4 11.5 – 1.27 – 13.8 14.1 14.4 0.6 0.8 1.0 – 1.35 – – – 0.15 0° – 8° – 0.76 – – 13.34 – – 1.27 – Recommended Mount Pad e Plastic 32pin 525mil SOP I2 E HE 1 32 e EIAJ Package Code TSOPII 32-P-400-1.27 D JEDEC Code – y Weight(g) 0.53 b 16 17 F Lead Material Alloy 42 L1 32P3Y-H c A1 Detail F A2 A L ME b2 ME I2 b2 A A1 A2 b c D E e HE L L1 y Symbol Mar.’98 Dimension in Millimeters Min Nom Max – – 1.2 0.125 0.2 0.05 – – 1.0 0.35 0.4 0.5 0.105 0.125 0.175 20.85 20.95 21.05 10.16 10.26 10.06 – 1.27 – 11.76 11.56 11.96 0.5 0.4 0.6 0.8 – – – – 0.1 – 0° 10° 10.36 – – – – 0.9 – – 0.76 Recommended Mount Pad e Plastic 32pin 400mil TSOP ( ) I2 E HE 32 1 e EIAJ Package Code TSOPII 32-P-400-1.27 D JEDEC Code – y Weight(g) 0.53 b 17 16 F Lead Material Alloy 42 L1 32P3Y-J Detail F A2 A c A1 L ME b2 ME I2 b2 A A1 A2 b c D E e HE L L1 y Symbol Mar.’98 Dimension in Millimeters Min Nom Max – – 1.2 0.125 0.2 0.05 – – 1.0 0.35 0.4 0.5 0.105 0.125 0.175 20.85 20.95 21.05 10.16 10.26 10.06 – 1.27 – 11.76 11.56 11.96 0.5 0.4 0.6 0.8 – – – – 0.1 – 0° 10° 10.36 – – – – 0.9 – – 0.76 Recommended Mount Pad e Plastic 32pin 400mil TSOP ( ) I2 E 16 1 EIAJ Package Code – D HD F JEDEC Code – 17 32 Weight(g) A 32P3K-B Lead Material Alloy 42 A2 A1 e Detail F b L L1 y b2 I2 MD A A1 A2 b c D E e HD L L1 y Symbol Mar.’98 Dimension in Millimeters Min Nom Max – – 1.2 0.05 0.125 0.2 – 1.0 – 0.15 0.2 0.3 0.13 0.15 0.2 11.7 11.8 11.9 7.9 8.0 8.1 – 0.5 – 13.2 13.4 13.6 0.4 0.5 0.6 – 0.8 – – – 0.1 0° – 10° – 0.225 – 0.9 – – 12.0 – – Recommended Mount Pad l2 MD Plastic 32pin 8✕13.4mm TSOP( ) e b2 c E 17 32 EIAJ Package Code – D HD F JEDEC Code – 16 1 Weight(g) A 32P3K-C Detail F L L1 Lead Material Alloy 42 A2 A1 e b y e b2 c b2 I2 MD A A1 A2 b c D E e HD L L1 y Symbol Mar.’98 Dimension in Millimeters Min Nom Max – – 1.2 0.05 0.125 0.2 – 1.0 – 0.15 0.2 0.3 0.13 0.15 0.2 11.7 11.8 11.9 7.9 8.0 8.1 – 0.5 – 13.2 13.4 13.6 0.4 0.5 0.6 – 0.8 – – – 0.1 0° – 10° – 0.225 – 0.9 – – 12.0 – – Recommended Mount Pad l2 MD Plastic 32pin 8✕13.4mm TSOP( )