Revised March 2005
74AC541 • 74ACT541
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
Features
The 74AC541 and 74ACT541 are octal buffer/line drivers
designed to be employed as memory and address drivers,
clock drivers and bus oriented transmitter/receivers.
■ ICC and IOZ reduced by 50%
These devices are similar in function to the 74AC244 and
74ACTC244 while providing flow-through architecture
(inputs on opposite side from outputs). This pinout arrangement makes these devices especially useful as an output
port for microprocessors, allowing ease of layout and
greater PC board density.
■ 3-STATE outputs
■ Inputs and outputs opposite side of package, allowing
easier interface to microprocessors
■ Output source/sink 24 mA
■ 74AC541 is a non-inverting option of the 74AC540
■ 74ACT541 has TTL-compatible inputs
Ordering Code:
Order Number
Package
Package Description
Number
74AC541SC
M20B
74AC541SJ
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC541MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC541MTCX_NL
(Note 1)
MTC20
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74AC541PC
N20A
74ACT541SC
M20B
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT541MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT541MTCX_NL
(Note 1)
MTC20
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT541PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDED J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
FACT¥ is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009967
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74AC541 • 74ACT541 Octal Buffer/Line Driver with 3-STATE Outputs
November 1988
74AC541 • 74ACT541
Logic Symbol
Connection Diagram
IEEE/IEC
Truth Table
Inputs
H
HIGH Voltage Level
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X
Immaterial
Outputs
OE1
OE2
I
L
L
H
H
H
X
X
Z
X
H
X
Z
L
L
L
L
L
LOW Voltage Level
2
Z
High Impedance
Recommended Operating
Conditions
0.5V to 7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI
VI
0.5V
VCC 0.5V
Supply Voltage (VCC)
20 mA
20 mA
0.5V to VCC 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO
0.5V
VO
VCC 0.5V
DC Output Voltage (VO)
20 mA
20 mA
0.5V to VCC 0.5V
AC
2.0V to 6.0V
ACT
4.5V to 5.5V
Input Voltage (VI)
0V to VCC
Output Voltage (VO)
0V to VCC
VCC @ 3.3V, 4.5V, 5.5V
r 50 mA
ACT:VIN from 0.8V to 2.0V
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
VCC @ 4.5V, 5.5V
r 50 mA
65qC to 150qC
Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met,
without exception, to ensure that the system design is reliable over its
power supply, temperature, and output/input loading variables. Fairchild
does not recommend operation of FACT¥ circuits outside databook specifications.
Junction Temperature (TJ)
140qC
PDIP
125 mV/ns
AC: VIN from 30% to 70% of VCC
DC Output Source
or Sink Current (IO)
40qC to 85qC
Operating Temperature (TA)
Minimum Input Edge Rate ('V/'t)
DC Electrical Characteristics for AC
Symbol
Parameter
VCC
(V)
VIH
VIL
VOH
VOL
25qC
TA
Typ
TA
40qC to 85qC
Minimum HIGH Level
3.0
1.5
2.1
2.1
Input Voltage
4.5
2.25
3.15
3.15
5.5
2.75
3.85
3.85
Maximum LOW Level
3.0
1.5
0.9
0.9
Input Voltage
4.5
2.25
1.35
1.35
1.65
5.5
2.75
1.65
Minimum HIGH Level
3.0
2.99
2.9
2.9
Output Voltage
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
3.0
2.56
2.46
4.5
3.86
3.76
5.5
4.86
4.76
0.1
0.1
Maximum LOW Level
Output Voltage
3.0
Units
Conditions
Guaranteed Limits
0.002
VOUT
V
0.1V
or VCC 0.1V
VOUT
0.1V
V
or VCC 0.1V
V
IOUT
50 PA
V
VIL or VIH
12 mA
IOH
24 mA
IOH
24 mA (Note 3)
50 PA
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
3.0
0.36
0.44
4.5
0.36
0.44
5.5
0.36
0.44
5.5
r 0.1
r 1.0
PA
VI
Leakage Current
5.5
r0.25
r2.5
PA
VI
IOLD
Minimum Dynamic
5.5
75
mA
VOLD
IOHD
Output Current (Note 4)
5.5
75
mA
VOHD
ICC (Note 5) Maximum Quiescent Supply Current
5.5
40.0
PA
VIN
IIN (Note 5)
Maximum Input Leakage Current
IOZ
Maximum 3-STATE
V
VIN
IOH
V
IOUT
VIN
VIL or VIH
IOL
12 mA
IOL
24 mA
IOL
24 mA (Note 3)
V CC, GND
VI (OE)
VO
4.0
V IL, VIH
VCC, GND
VCC, GND
1.65V Max
3.85V Min
VCC or GND
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
3
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74AC541 • 74ACT541
Absolute Maximum Ratings(Note 2)
74AC541 • 74ACT541
AC Electrical Characteristics for AC
Symbol
tPLH
tPHL
tPZH
tPZL
Parameter
25qC
CL
50 pF
TA
40qC to 85qC
CL
Min
Units
Typ
Propagation Delay
3.3
2.0
5.5
8.0
1.5
9.0
Data to Output
5.0
1.5
4.0
6.0
1.0
6.5
Propagation Delay
3.3
2.0
5.5
8.0
1.5
8.5
Data to Output
5.0
1.5
4.0
6.0
1.0
6.5
Output Enable Time
3.3
3.0
8.0
11.5
3.0
12.5
5.0
2.0
6.0
8.5
1.5
9.5
3.3
2.5
7.0
10.0
2.5
11.5
5.0
1.5
5.5
7.5
1.0
8.5
3.3
3.5
9.0
12.5
2.5
14.0
5.0
2.0
7.0
9.5
1.0
10.5
3.3
2.5
6.5
9.5
2.0
10.5
5.0
2.0
5.5
7.5
1.0
8.5
Output Disable Time
Max
50 pF
Min
Output Disable Time
tPLZ
TA
(V)
(Note 6)
Output Enable Time
tPHZ
VCC
Max
ns
ns
ns
ns
ns
ns
Note 6: Voltage Range 3.3 is 3.3V r 0.3V
Voltage Range 5.0 is 5.0V r 0.5V
DC Electrical Characteristics for ACT
Symbol
VIH
VIL
VOH
VOL
Parameter
VCC
TA
(V)
Typ
25qC
TA
40qC to 85qC
Guaranteed Limits
Minimum HIGH Level
4.5
1.5
2.0
2.0
Input Voltage
5.5
1.5
2.0
2.0
Maximum LOW Level
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
0.8
Minimum HIGH Level
3.0
2.99
2.9
2.9
Output Voltage
4.5
4.49
4.4
4.4
4.5
3.86
3.76
5.5
4.86
4.76
Units
V
V
V
V
Conditions
VOUT
0.1V
or VCC 0.1V
VOUT
0.1V
or VCC 0.1V
50 PA
IOUT
VIN
VIL or VIH
IOH
24 mA
IOH
24 mA (Note 7)
50 PA
Maximum LOW Level
3.0
0.002
0.1
0.1
Output Voltage
4.5
0.001
0.1
0.1
4.5
0.36
0.44
VIN
VIL or VIH
5.5
0.36
0.44
V
IOH
24 mA
5.5
r 0.1
r 1.0
PA
VI
V CC, GND
5.5
r0.25
r2.5
VI
V IL, VIH
V
IOUT
IOH
IIN
Maximum Input
24 mA (Note 7)
Leakage Current
IOZ
Maximum 3-STATE
Leakage Current
ICCT
Maximum ICC/Input
5.5
IOLD
Minimum Dynamic
IOHD
Output Current (Note 8)
ICC
Maximum Quiescent
5.5
0.6
VO
VCC, GND
VCC 2.1V
1.5
mA
VI
5.5
75
mA
VOLD
5.5
75
mA
VOHD
40.0
PA
VIN
4.0
Supply Current
Note 7: All outputs loaded; thresholds on input associated with output under test.
Note 8: Maximum test duration 2.0 ms, one output loaded at a time.
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PA
4
1.65V Max
3.85V Min
VCC or GND
Symbol
Parameter
V CC
TA
25qC
(V)
CL
50 pF
(Note 9)
tPLH
Propagation Delay
tPHL
Data to Output
tPZH
Output Enable Time
5.0
5.0
tPZL
Output Disable Time
tPHZ
5.0
tPLZ
TA
40qC to 85qC
CL
Min
50 pF
Min
Typ
Max
2.0
4.5
7.0
2.0
7.5
2.0
5.5
7.0
2.0
7.5
2.0
5.0
9.0
2.0
9.5
2.0
6.5
9.0
2.0
9.5
1.5
5.5
7.5
1.5
8.0
1.5
5.5
7.5
1.5
8.0
Units
Max
ns
ns
ns
Note 9: Voltage Range 5.0 is 5.0V r 0.5V
Capacitance
Typ
Units
CIN
Symbol
Input Capacitance
Parameter
4.5
pF
VCC
OPEN
CPD
Power Dissipation Capacitance for AC
30.0
Power Dissipation Capacitance for ACT
70.0
pF
VCC
5.0V
5
Conditions
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74AC541 • 74ACT541
AC Electrical Characteristics for ACT
74AC541 • 74ACT541
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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6
74AC541 • 74ACT541
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7
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74AC541 • 74ACT541
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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8
74AC541 • 74ACT541 Octal Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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9
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