MITSUBISHI ICs (TV) M64898GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M64898GP is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR /PC. 1 20 Xin CRYSTAL OSCILLATOR GND GND 2 19 ENA ENABLE INPUT SUPPLY VOLTAGE 1 SUPPLY VOLTAGE 2 VCC1 3 18 DATA DATA INPUT VCC2 4 17 CLK CLOCK INPUT BS4 5 BS3 6 BS2 7 BS1 DC-DCSUPPLY VDC VOLTAGE PEACK CURRENT lpk DETECT 8 13 Vtu 9 12 +B 10 11 SWE PRESCALER INPUT and DC-DC converter for Tuning voltage. FEATURES • • • • • • • • • Built-in DC-DC converter for Tuning voltage 4 integrated PNP band drivers (Io=30mA, Vsat=0.2V typ@VCC1 to 10V ) Built-in prescaler with input amplifier (max=1.3GHz) PLL lock/unlock status display out put (Built-in pull up resistor) X’tal 4MHz is used to realize 3 type of tuning steps (Divider ratio 1/512, 1/640, 1/1024) Software compatible with M64892/M64893 Automatick switching of tuning step according to the number of data bits (62.5kHz at 18bits , 32.25kHz at 19bits) Built-in Power on reset system Small Package(SSOP) BAND SWITCHING OUTPUTS M64898GP fin It contains the prescaler with operating up to1.3GHz,4 band drivers 16 LD/ftest LD/ftest OUTPUT 15 CONT fREF SWITCHING FILTER INPUT 14 Vin TUNING OUTPUT SUPPLY VOLTAGE SWITCHING OUTPUT Outline 20P2E-A RECOMMENDED OPERATING CONDITION APPLICATION Supply voltage range..............................................V CC1=4.5 to 5.5V PC, TV, VCR tuners VCC2=VCC1 to 10V Rated supply voltage...........................................................V CC1=5V VCC2=VCC1 BLOCK DIAGRAM VCC1 CNT VDC lpk 3 15 9 10 S Q Xin 20 f REF DIVIDER OSC DIV. SELECTER R 11 SWE 2 LATCH fin 1 1/8 AMP LATCH 15 + Vreg 12 +B 1/32,1/33 15bit PROGRAMMABLE DIVIDER PHASE DETECTOR CHARGE PUMP CP CLK 17 LOCK DETECTOR 18/19-bit SHIFT REGISTER CONTROL DATA 18 13 Vtu OS TEST LATCH 14 Vin 5 ENA 19 16 LD/ftest 4 BAIS / BAND SWITCH DRIVER Power On Reset 4 VCC2 1 5 BS4 6 BS3 7 BS2 8 BS1 2 GND MITSUBISHI ICs (TV) M64898GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC DESCRIPTION OF PIN Pin No. Symbol Pin name Function 1 f in Prescaler input Input for the VCO frequency. 2 GND GND Ground to 0V. Power supply voltage terminal. 5.0V±0.5V Power supply for band switching, Vcc1 to 10V 3 VCC1 Power supply voltage 1 4 VCC2 Power supply voltage 2 5 BS4 6 BS3 Band switching 7 BS2 outputs 8 BS1 9 VDC 10 Ipk 11 SWE 12 +B 13 Vtu DC-DC power supply voltage Peack current PNP open collector method is used. When the band switching data is "H", the output is ON. When it is "L", the output is OFF. DC-DC power supply voltage terminal. 5.0V ±0.5V detect When potential difference with VDC terminal becomes more than 0.33V by current limiting detector of DC-DC converter, the listing rises with off. Switching output DC-DC converter oscillator output. Power supply voltage Tuning output Power supply voltage for turning voltage. This supplies the tuning voltage. This is the output terminal for the LPF input and charge pump output. When the phase of the programmable divider output (f 1/N) is ahead compared to the reference 14 Vin Filter input (Charge pump output) frequency (fREF), the "source" current state becomes active. If it is behind, the "sink" current becomes active. If the phases are the same, the high impedance state becomes active. Lock detector output. When loop of phase locked loop locked it, it rises with "H" level in "L" level or unlock. 15 LD/ftest Lock detect /Test port 16 CONT fREF Switchi In "L" level, set it up in 1/640(19Bit) in setting "opening" in 1/1024(19Bit) or 1/512 (18Bit). 17 CLOCK Clock input Data is read into the shift register when the clock signal falls. 18 DATA Data input Input for band SW and programmable freq. divider set up. 19 ENABLE Enable input This is normally at a "L". When this is at "H", data and clock signals are received. Data is read into the latch when the enable signal after the 18th signal of the clock signal falls or when the 19th pulse of the clock signal falls. 20 X in This is connected to the crystal oscillator. 4.0MHz crystal oscillator is connected. In control byte data input, the programmabule freq. divider output and reference freq. output is selected by the test mode. Set up reference frequency divider ratio. ABSOLUTE MAXIMUM RATINGS (Ta=-20°C to +75°C, unless otherwise noted) Symbol VCC1 VCC2 VI VO VBSOFF IBSON tBSON Pd Topr Tstg Parameter Supply voltage 1 Supply voltage 2 Input voltage Output voltage Voltage applied when Conditions Pin3 Pin4 Not to exceed Vcc1 fREF output the band output is OFF Band output current ON the time when the per 1 band output circuit 40mA per 1 band output circuit band output is ON Power dissipation Operating temperature Storage temperature 3circuits are pn at same time, Ta=75°C Ratings 6.0 10.8 6.0 6.0 Unit V V V V 10.8 V 40.0 mA 10 sec 255 -20 to +75 -40 to +125 mW °C °C 2 MITSUBISHI ICs (TV) M64898GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC RECOMMENDED OPERATING CONDITIONS (Ta=-20°C to +75°C, unless otherwise noted) Symbol VCC1 VCC2 fopr1 fopr2 Parameter Supply voltage 1 Supply voltage 2 Operating frequency (1) Operating frequency (2) IBDL Band output current 5 to 8 Conditions Pin3 Pin4 Crystal oscillation circuit Ratings 4.5 to 5.5 VCC1 to 10.0 4.0 80 to 1300 Unit V V V MHz 0 to 30 mA Normally 1 circuit is on. 2 circuits on at the same time is max. It is prohibited to have 3 or more circuits turned on at the same time. ELECTRICAL CHARACTERISTICS (Ta=-20°C to +75°C, unless otherwise noted, Vcc1=5.0V, Vcc2=9.0V) Symbol VIH VIL1 VIL2 IIH IIL1 IIL2 IIL3 VOH VOL VBS Input terminals Lock output Iolk1 Band SW VtoH VtoL Tuning output Icpo IcpLK ICC1 ICC2A Charge pump ICC2B Parameter Test pin “H” input voltage “L” input voltage “L” input voltage “H” input current “L” input current “L” input current “L” input current “H” output voltage “L” output voltage Output voltage 17 to 19 15 17 to 19 17 to 19 15 17, 19 18 16 16 5 to 8 Leak current − -10 Unit V V V µA µA µA µA V V V µA − − V 4 − − − − − 0.2 ±270 − 20 − 0.4 ±370 ±50 30 0.3 V µA nA mA mA 4 VCC2=9V − 4.0 6.0 mA 13 14 14 3 ICC2C DC-DC Converter ICCdc Supply current (action) 4 VCC2=9V, Io=-30mA − 34.0 36.0 mA 9 VCC1=5.5V Vdo fOSC Vipk 12 11 10 VCC1=5.5V VCC1=5.5V VCC1=5.5V − 28 − − 1.3 31 571 330 3.0 35 − − mA V kHz mV Output voltage OSC frequency Current limit detect voltage The typical values are at VCC1=5.0V, VCC2=9.0V, Ta=+25°C. 3 − Limits Typ. Max. VCC1+0.3 − − 0.4 − 1.5 − 10 -50 -80 -6 -10 -18 -30 − − 0.3 0.5 11.8 - 30.5 13 Output voltage “L” “H” output current 4 circuits OFF 1 circuits ON, Output open Output current 30mA VCC1=5.5V, Vi=4.0V VCC1=5.5V, Vi=0V VCC1=5.5V, Vi=0.5V VCC1=5.5V, Vi=0.5V VCC1=5.5V VCC1=5.5V VCC2=9V, Io=-30mA VCC2=9V, Band SW is OFF Vo=0V +B=31V Min. 3.0 − − − − − − 5.0 − 11.6 +B=31V VCC1=5.0V, Vo=2.5V VCC1=5.0V, Vo=2.5V VCC1=5.5V VCC2=9V Output voltage “H” Leak current Supply current 1 Supply current 2 5 to 8 Test conditions MITSUBISHI ICs (TV) M64898GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC SWITCHING CHARACTERISTICS (Ta=-20°C to +75°C, unless otherwise noted, Vcc1=5.0V, Vcc2=9.0V) Symbol Parameter Test pin fopr Prescaler operating frequency 1 Vin Operating input voltage 1 tPWC Clock pulse width Data setup time Data hold time Enable setup time Enable hold time Enable data interval time Rise time Fall time Next enable prohibit time Next clock prohibit time tSU (D) tH (D) tSU (E) tH (E) tINT tr tf tBT tBCL 17 18 18 18 18 19, 18 Test conditions VCC1=4.5 to 5.5V Vin=Vinmin to Vinmax 80 to 100MHz VCC1=4.5 100 to 950MHz to 5.5V 950 to 1300MHz VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V 17, 18, 19 VCC1=4.5 to 5.5V 17, 18, 19 VCC1=4.5 to 5.5V 19 VCC1=4.5 to 5.5V 17, 19 VCC1=4.5 to 5.5V Min. Limits Typ. Max. 80 − 1300 MHz -24 -27 -15 − − − 4 4 4 dBm 1 2 1 3 3 1 − − 5 − − − − − − − − − − − − − − − − µs µs µs µs µs µs µs µs µs 5 − − µs 1 1 Unit 4 MITSUBISHI ICs (TV) M64898GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC METHOD OF SETTING DATA The programmable divider ratio uses 15bits. Setting up the band Automatic judgment facility comes being it, and, as for Shift resister, switching output uses 4bits. CONT terminal rises by 18/19 bits at the time of "L". At the time of The test mode data uses 8bits. The total bits used is 27bits. Data is data of 18 bits, M9 bit of Programable divider is done reset of, and read in when the enable signal is "H" and the clock signal falls. it is established in reference frequency divider ratio 1/512. The band switching data is read in at the 4th pulse of the clock At the time of 19 bits,reference frequency divider ratio is established signal. The programmable counter data is read into the latch by the in 1/1024. fall of the enable signal after the 18th pulse of the clock signal or the When reference frequency divider ratio was established in 1/640 by fall of the 19th pulse of the clock signal. When the enable signal 19 bits at the time of "opening" CONT terminal, and it became "L" goes to "L" before the 18th pulse of the enable signal, only the band before 19 pulse enable signal, only band SW data are renewed, and SW data is updated and other data is ignored. other data are ignored. (1) Transfer of the 18th bit data (CONT terminal is "L" ) Data is latched by the fall of the enable signal after the 18th clock signal. At this time, the divider of the 1/512 of the reference frequency is used. ENA BS4 BS3 BS2 BS1 DATA 28 27 26 25 24 23 22 21 20 24 23 22 21 20 M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0 CLK BAND SW DATA M COUNTER DIVIDER RATIO SETTING S COUNTER DIVIDER RATIO SETTING READ INTO LATCH READ INTO LATCH (2) Transfer of the 19th bit data (CONT terminal is "L" or "open") The data is latched at the 19th pulse of the clock signal. Invalid the clock signal after 19th pulse. Reference frequency divider ratio is established in 1/1024 in case of Notice) When CONT terminal is "L", to change reference frequency, "L" CONT terminal at this time. set up as ENA in "L" after 19th pulse of clock signal by all means. Reference frequency divider ratio is established in 1/640 in case of "opening" CONT terminal. ENA BS4 BS3 BS2 DATA BS1 29 28 27 26 25 24 23 22 21 20 24 23 22 21 20 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0 CLK BAND SW DATA M COUNTER DIVIDER RATIO SETTING READ INTO LATCH 5 S COUNTER DIVIDER RATIO SETTING READ INTO LATCH MITSUBISHI ICs (TV) M64898GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC HOW TO SET THE DIVIDING RATIO OF THE PROGRAMMABLE DIVIDER (1) Transfer of the 18th bit data (CONT terminal is "L" ) Therefore, the range of divider N is 8,192 to 262,136. Total divider N is given by the following formulas in addition to the The tuning frequency fVCO is given in the following equations. fVCO=fREF×N prescaler used in the previous stage. N=8 • (32M+S) M : 9 bit main counter divider =3.90625×8×(32M+S) S : 5 bit swallow counter divider =31.25×(32M+S) [kHz] The M and S counters are binary the possible ranges of divider are Therefore, the tuning frequency range is 32MHz to 1023.96875 as follows. MHz. 32≤M≤511 0≤S≤31 (3) Transfer of the 19th bit data (CONT terminal is "open") Therefore, the range of divider N is 8,192 to 131,064. Total divider N is given by the following formulas in addition to the The tuning frequency fVCO is given in the following equations. prescaler used in the previous stage. fVCO=fREF×N N=8 • (32M+S) M : 10 bit main counter divider =7.8125×8×(32M+S) S : 5 bit swallow counter divider =62.5×(32M+S) [kHz] The M and S counters are binary the possible ranges of divider are Therefore, the tuning frequency range is 64MHz to 1023.9375MHz. as follows. 32≤M≤1023 (2) Transfer of the 19th bit data (CONT terminal is "L" ) 0≤S≤31 Total divider N is given by the following formulas in addition to the Therefore, the range of divider N is 8,192 to 262,136. prescaler used in the previous stage. The tuning frequency fVCO is given in the following equations. N=8 • (32M+S) M : 10 bit main counter divider S : 5 bit swallow counter divider The M and S counters are binary the possible ranges of divider are as follows. fVCO=fREF×N =6.25×8×(32M+S) =50.0×(32M+S) [kHz] But, the tuning frequency range is 51.2MHz to 1300MHz from the 32≤M≤1023 maxmum prescaler operating frequency. 0≤S≤31 TEST MODE DATA SET UP METHOD The data for the test mode uses 20 to 27bits. Data is latched when the 27th clock signal falls. (1) When transferring 3-wire 27 bit data ENA 1 19 20 S COUNTER DIVIDER RATIO SETTING X 27 CLK BAND SW DATA M COUNTER DIVIDER RATIO SETTING X T2 T1 T0 RSa RSb 0S TEST DATA SETTING READ INTO LATCH (2) Test Mode Bit Set Up X :Random, 0 or 1.normal "0" T0, T1,&T2 :Set up test modes RSa, Rsa :Set the frequency divider of the reference OS :Set up the tuning amplifier frequency 6 MITSUBISHI ICs (TV) M64898GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC Setting up for the test mode T2 0 0 1 1 1 1 T1 0 1 1 1 0 0 T0 X X 0 1 0 1 Charge pump Normal operation High impedance Sink Source High impedance High impedance Set up the tuning amplifier 12 pin output LD LD LD LD fREF f1/N Mode OS 0 1 Normal operation Test mode Test mode Test mode Test mode Test mode RSb 1 1 0 Mode Normal Test Power on reset operation (Initial state the power is turned ON) Set up for the reference Frequency divider ratio RSa 1 0 X Tuning voltage output ON OFF Divider ratio 1/512 1/1024 1/640 BS4 to BS1 : OFF Charge pump : High impedance Tuning amplifier : OFF Charge pump current : 270µA ∗ Frequency divider ratio : 1/1024 Lock detect :H ∗ Charge pump current is replaced by 70µA when locks it by automatic change facility. TIMING DIAGRAM tr tf 90% 1.5V ENABLE VIH 90% 10% 10% tINT tINT 90% 1.5V DATA 10% VIL tBT VIH 90% 10% VIL tr 1.5V 10% 10% VIL tPWC tSU(D) tr tH(D) tSU(E) CRYSTAL OSCILLATOR CONNECTION DIAGRAM 16 Crystal oscillator characteristics Actual resistance : less then 300Ω Load capacitance : 20pF 18pF 4MHz 7 VIH 90% 90% CLOCK tf tf tH(E) tBCL MITSUBISHI ICs (TV) M64898GP PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC APPLICATION EXAMPLE BUILT-IN PLL TUNER IF AGC IF AGC VHF 4-BAND TUNER AFT Note) Filter constant is for reference. ∗ Add a capacitor to stabilize the filter circuit. UHF +B BS4 BS3 BS2 BS1 LO VT 33µH 0.1µF 0.01µF - 56k 1000pF VCC1 to 9V ∗100pF 56k 680pF 43 22k 68µH 0.1µF M64898GP 4 5 6 7 8 1 13 14 9 10 11 POWER ON RESET BIAS CIRCUIT AMP Q S BAND DRIVER R 1/8 CHARGE PUMP 4 + - 1/32 1/33 PHASE DETECTOR 3 +5V Vreg 1.5µF SELECTER MAIN COUNTER 12 SWALLOW COUNTER 5 18/19 bit SHIFT RESISTER DATA LATCH LOCK DETECTOR VCC1=5V OSC DIVIDER 9/10 2 15 18pF 20 - 19 17 18 4MHz 15 1000pF DATA CLK ENA LD/ftest MCU Units Resistance : Ω Capacitance : F 8