M64897GP PLL Frequency Synthesizer with DC/DC Converter for PC REJ03F0167-0200 Rev.2.00 Jun 14, 2006 Description The M64897GP is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR/PC using I2C BUS control. It contains the prescaler with operating up to 1.3 GHz, 4 band drivers and DC/DC converter for Tuning voltage. Features • • • • • • • • Built-in DC/DC converter for Tuning voltage 4 integrated PNP band drivers (IO = 30 mA, Vsat = 0.2 V Typ.@VCC1 to 10 V) Built-in prescaler with input amplifier (f max = 1.3 GHz) PLL lock/unlock status display out put (Built-in pull up resistor) X’tal 4 MHz is used to realize 3 type of tuning steps (Divider ratio 1/512, 1/640, 1/1024) Software compatible with M64894 Built-in Power on reset system Small Package (SSOP) Application PC, TV, VCR tuners Recommended Operating Condition • Supply voltage range VCC1 = 4.5 to 5.5 V VCC2 = VCC1 to 10 V • Rated supply voltage VCC1 = 5 V VCC2 = VCC1 Rev.2.00 Jun 14, 2006 page 1 of 13 M64897GP Block Diagram VCC1 3 VDC 9 Ipk 10 S Q Xin 20 OSC Selector fREF Divider R DIV. 11 SWE Latch fin 1 AMP 2 – 1/8 Latch 15 + Phase Detector 15-bit Programmable Divider 1/32, 1/33 Vreg Charge Pump CP 1 SCL 17 Bus Controller Address Select SDA 18 4 Bias/Band Switch Driver Latch 1 5-level ADC Power-on Reset 6 BS3 Rev.2.00 Jun 14, 2006 page 2 of 13 7 BS2 OS TEST 14 Vin Lock Detector 3 5 BS4 13 Vtu 5 ADS 19 4 VCC2 12 +B 8 BS1 2 GND 15 ADC 16 LD/ftest M64897GP Pin Arrangement M64897GP fin 1 20 Xin GND 2 19 ADS VCC1 3 18 SDA VCC2 4 17 SCL BS4 5 16 LD/ftest BS3 6 15 ADC BS2 7 14 Vin BS1 8 13 Vtu VDC 9 12 +B Ipk 10 11 SWE (Top view) Outline: PLSP0020JA-A (20P2E-A) Rev.2.00 Jun 14, 2006 page 3 of 13 M64897GP Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 Symbol fin GND VCC1 VCC2 BS4 BS3 BS2 BS1 VDC Ipk Pin name Prescaler input GND Power supply voltage 1 Power supply voltage 2 Band switching outputs Function Input for the VCO frequency. Ground to 0 V. Power supply voltage terminal.5.0 V ± 0.5 V Power supply for band switching, VCC1 to 10 V DC/DC power supply voltage Peak current detect DC/DC power supply voltage terminal.5.0 V ± 0.5 V 11 12 13 14 SWE +B Vtu Vin Switching output Power supply voltage Tuning output Filter input (Charge pump output) 15 LD/ftest Lock detect/Test port 16 17 ADC SCL AD converter input Clock input 18 SDA Data input 19 20 ADS Xin Address switching input This is connected to the crystal oscillator Rev.2.00 Jun 14, 2006 page 4 of 13 PNP open collector method is used. When the band switching data is “H”, the output is ON. When it is “L”, the output is OFF. When potential difference with VDC terminal becomes more than 0.33 V by current limiting detector of DC/DC converter, the listing rises with off. DC/DC converter oscillator output. Power supply voltage for tuning voltage. This supplies the tuning voltage. This is the output terminal for the LPF input and charge pump output. When the phase of the programmable divider output (f 1/N) is ahead compared to the reference frequency (fREF), the “source” current state becomes active. If it is behind, the “sink” current becomes active. If the phases are the same, the high impedance state becomes active. Lock detector output. When loop of phase locked loop locked it, it rises with “H” level in “L” level or unlock. In control byte data input, the programmable freq. divider output and reference freq. output is selected by the test mode. A/D conversion of the input voltage. Data is read into the shift register when the clock signal falls.. Input for band SW and programmable freq. divider set up. In lead mode, it outputs lock detector output and power down flag and a state of 5 level A/D converter. Chip address sets it up with the input condition of terminal. 4.0 MHz crystal oscillator is connected. M64897GP Absolute Maximum Ratings (Ta = −20°C to +75°C, unless otherwise noted) Item Supply Voltage 1 Supply voltage 2 Input voltage Output voltage Symbol VCC1 VCC2 VI VO Ratings 6.0 10.8 6.0 6.0 10.8 Unit V V V V V Condition Pin 3 Pin 4 Not to exceed VCC1 fREF output Voltage applied when the band output is OFF Band output current VBSOFF mA s Per 1 band output circuit tBSON 40.0 10 ON the time when the band output is ON Power dissipation Operating temperature Storage temperature Pd Topr Tstg 255 −20 to +75 −40 to +125 mW °C °C IBSON 40 mA per 1 band output circuit 3 circuits are pn at same time. Ta = 75°C Recommended Operating Conditions (Ta = −20°C to +75°C, unless otherwise noted) Item Supply voltage 1 Supply voltage 2 Operating frequency (1) Operating frequency (2) Band output current 5 to 8 Symbol VCC1 VCC2 fopr1 fopr2 IBDL Rev.2.00 Jun 14, 2006 page 5 of 13 Ratings 4.5 to 5.5 VCC1 to 10.0 4.0 80 to 1300 0 to 30 Unit V V V MHz mA Conditions Pin 3 Pin 4 Crystal oscillation circuit Normally 1 circuit is on. 2 circuits on at the same time is max. It is prohibited to have 3 or more circuits turned on at the same time. M64897GP Electrical Characteristics (Ta = −20°C to +75°C, unless otherwise noted, VCC1 = 5.0 V, VCC2 = 9.0 V) Item Input termina ls SDA output Lock output Band SW Tuning output Charge pump Symbol Test Pin Min. Limits Typ. Max. Unit V — — –4/–14 — — — VCC1 + 0.3 1.5 10 −10/−30 0.4 10 — V µA µA µA µA V — 11.6 — 0.3 11.8 — 0.5 — –10 V V µA “H” input voltage VIH 17 to 18 3.0 — “L” input voltage “H” input current VIL IIH “L” input current “L” output voltage IIL VOL Leak current ILO VOH 17 to 18 17 to 18 17, 18 18 18 16 — — — — — 5.0 Test Conditions VCC1 = 5.5V, Vi = 4.0V VCC1 = 5.5V, Vi = 0.4V VCC1 = 5.5V, IC = 3mA VCC1 = 5.5V, VO = 5.5V VCC1 = 5.5V “H” output voltage “L” output voltage Output voltage VOL VBS Leak current Iolk1 16 5 to 8 5 to 8 Output voltage “H” VtoH 13 30.5 — — V VCC2 = 9V, Band SW is OFF VO = 0V +B = 31V Output voltage “L” VtoL 13 — 0.2 0.4 V +B = 31V ICPO 14 — 270 370 µA VCC1 = 5.0V, VO = 2.5V ICPLK ICC1 ICC2A ICC2B 14 3 4 4 — — — — — 20 — 4.0 50 30 0.3 6.0 nA mA mA mA VCC1 = 5.0V, VO = 2.5V VCC1 = 5.5V VCC2 = 9V VCC2 = 9V 36.0 mA VCC2 = 9V, IO = −30mA 3.0 35 — — mA V kHz mV VCC1 = 5.5V VCC1 = 5.5V VCC1 = 5.5V VCC1 = 5.5V “H” output current Leakage current Supply current 1 4 circuits OFF Supply current 1 circuits ON, 2 Output open 4 — 34.0 Output current 30 ICC2C mA DC/DC Converter Supply current (action) ICCdc 9 — 1.3 Output voltage Vdo 12 28 31 OSC frequency fOSC 11 — 571 Current limit detect voltage Vipk 10 — 330 Note: The typical values are at VCC1 = 5.0 V, VCC2 = 9.0 V, Ta = +25°C. Rev.2.00 Jun 14, 2006 page 6 of 13 VCC1 = 5.5V VCC2 = 9V, IO = −30mA M64897GP Switching Characteristics (Ta = −20°C to +75°C, unless otherwise noted, VCC1 = 5.0 V, VCC2 = 9.0 V) Min. Limits Typ. Max. Unit Prescaler operating frequency fopr 1 80 — 1300 MHz VCC1 = 4.5 to 5.5V Vin = Vinmin to Vinmax Operation input voltage Vin 1 4 4 4 100 — — — — — — — 1000 300 — VCC1 = 4.5 to 5.5V fSCL tBUF tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tR tF tSUSTO — — — — — — — — — — — — — — dBm Clock pulse frequency Bus free time Data hold time SCL low hold time SCL high hold time Set up time Data hold time Data set up time Rise time Fall time Set up time −24 −27 −15 0 4.7 4 4.7 4 4.7 0 250 — — 4 Item Symbol Rev.2.00 Jun 14, 2006 page 7 of 13 Test Pin 17 18 17 17 17 17, 18 17, 18 17, 18 17, 18 17, 18 17, 18 kHz µs µs µs µs µs s ns ns ns µs Test Conditions 850 to 100MHz 100 to 950MHz 950 to 1300MHz VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V M64897GP Method of Setting Data The input information to consist of 2 or data of 4 bytes to lead to chip address is received in I2C bus receiver. It shows a definition of bus protocol admitted in the following. 1_STA CA CB 2_STA CA D1 3_STA CA CB 4_STA CA D1 STA : Start condition STO : Stop condition CA : Chip address CB : Control data byte BB : Band SW data byte D1 : Divider data byte D2 : Divider data byte BB D2 BB D2 STO STO D1 CB D2 BB STO STO The information of 5 bytes necessary for circuit operation is chip address and control data, band SW data of 2 bytes and divider byte of 2 bytes. After the chip address input, 2 or data of 4 bytes are received. Function bit is contained the first and the third data byte to distinguish between divider data and control data, band data, and “0” goes ahead of divider data, and “1” goes ahead of control data, band SW data. SDA SCL S STA 1-7 8 9 1-7 Address CA 0 ACK 8 1-7 9 Data ACK 8 Data 9 ACK P STO Write Mode Format Byte Address byte Divider byte 1 Divider byte 2 Control byte 1 Band SW byte MSB 1 0 N7 1 X 1 N14 N6 X X 0 N13 N5 T2 X 0 N12 N4 T1 X 0 N11 N3 T0 BS4 MA1 N10 N2 RSa BS3 MA0 N9 N1 RSb BS2 0 N8 N0 OS BS1 LSB A A A A A 1 A0 LSB A A Read Mode Format Byte Address byte Status byte 1 MSB 1 POR Rev.2.00 Jun 14, 2006 page 8 of 13 1 FL 0 X 0 X 0 X MA1 A2 MA0 A1 M64897GP Data Cording Example Write Mode Format Example Byte Address byte Divider byte 1 Divider byte 2 Control byte 1 Band SW byte MSB 1 0 1 1 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 LSB 1 1 1 1 1 Condotion in Data Setting ADS input VCC1 Divider ratio N = 16544 fREF divider ratio 1/1024 BS4 output ON Note: fVCO = N • 8 • fREF = 16544 • 8 • (4 MHz/1024) = 517 MHz Read Mode Format Example (Loop locked) Byte Address byte MSB 1 1 0 0 0 1 1 1 LSB 1 0 1 1 1 1 0 1 1 1 Status byte Condotion in Data Setting ADS Applied voltage 0.9 VCC1 to VCC1 ADS Applied voltage 0.45 VCC1 to 0.6 VCC1 Use data input for “1” so that the data of Read mode and Write mode return ACK signal “0” to micro computer in 9 bits of each byte. Test Mode Data Set Up Method Test Mode Bit Set Up X MA1, MA0 : Random, 0 or 1. normal “0” : Programmable address bit Address Input Voltage MA1 0 to 0.1 VCC1 0 Always valid 0 0.4 VCC1 to 0.6 VCC1 1 0.9 VCC1 to VCC1 1 Note: N14 to N0: How to set dividing ratio of the programmable the divider Dividing ratio = N14 (214 = 16384) + +N0 (20 = 1) MA0 0 1 0 1 Therefore, the range of divider N is 1,024 to 32,768 Example) fVCO = fREF • 8 • N = 3.90625 • 8 • N = 31.25 • N (kHz) T2, T1, T0: Setting Up for The Test Mode T2 0 0 1 1 1 1 T1 0 1 1 1 0 0 T0 X X 0 1 0 1 Charge Pump Normal operation High impedance Sink Source High impedance High impedance Rev.2.00 Jun 14, 2006 page 9 of 13 Pin 12 Condition ADC input ADC input ADC input ADC input fREF output f1/N output Mode Normal operation Test mode Test mode Test mode Test mode Test mode M64897GP RSa, RSb: Set Up for The Reference Frequency Divider Ratio RSa 1 0 X RSb 1 1 0 Divider Ratio 1/512 1/1024 1/640 Tuning Voltage Output ON OFF Mode Normal Test OS: Set Up The Tuning Amplifier OS 0 1 POR : Power on reset flag. “1” output at reset FL : Lock detector flag. “1” output at locked, “0”output at unlocked A2, A1, A0: 5 Level A/D Converter Output Data ADC Input Voltage 0.6 ± VCC1 to VCC1 0.45 ± VCC1 to 0.6 ± VCC1 0.3 ± VCC1 to 0.45 ± VCC1 0.15 ± VCC1 to 0.3 ± VCC1 0 to 0.15 ± VCC1 A2 1 0 0 0 0 A1 0 1 1 0 0 Note: The voltage accuracy allowance range: 0.03 ± VCC1 (V) Power on Reset Operation (Initial state the power is turned ON) BS4 to BS1 Charge pump Tuning amplifier Charge pump current Frequency division ratio Lock detect : OFF : High impedance : OFF : 270 µA : 1/1024 :H Charge pump current is replaced by 70 µA when locks it by automatic change facility. Rev.2.00 Jun 14, 2006 page 10 of 13 A0 0 1 0 1 0 M64897GP Timing Diagram Start condition SDA tLOW tBUF tR tHDSTA tF SCL tHDSTA tHDDAT tHIGH Stop condition tSUDAT tSUSTO tSUSTA Start condition Crystal Oscillator Connection Diagram 20 18 pF 4 MHz Rev.2.00 Jun 14, 2006 page 11 of 13 Crystal oscillator characteristics Actual resistance: less than 300 Ω Load capacitance: 20 pF Stop condition M64897GP Application Example Built-in PLL Tuner IF AGC IF AGC VHF 4-Band Tuner UHF +B BS4 BS3 BS2 AFT BS1 Lo VT 33 H + 0.01 56 k 0.1 43 100 p VCC1 to 9 V 1000 p M64897GP 4 5 6 7 56 k 1500 p 8 0.1 14 1 22 k 68 H 13 9 10 11 Band Driver Q S 1/8 Charge Pump Power-on Reset 4 1/32 1/33 Phase Detector + Main Counter 10 Swallow Counter 2 I C Receiver Lock Detector 5 + Chip Select 19 VCC1 =5V 17 18 – Vreg 3 +5 V R OSC Divider Bias Circuit AMP 5-level ADC 51 k 12 1.5 2 18 p 20 15 4 MHz 18 VCC1 1000 p ADS SCL MCU Note: Filter constant is for reference. Add a capacitor to stabilize the filter circuit. Rev.2.00 Jun 14, 2006 page 12 of 13 SDA LD/ftest Units R: Ω C: F M64897GP Package Dimensions JEITA Package Code P-LSSOP20-4.4x6.5-0.65 RENESAS Code PLSP0020JA-A MASS[Typ.] 0.08g 11 *1 E 20 HE Previous Code 20P2E-A F 1 Index mark NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 10 c A2 A1 *2 D A L Reference Dimension in Millimeters Symbol *3 e y bp Detail F D E A2 A A1 bp c HE e y L Rev.2.00 Jun 14, 2006 page 13 of 13 Min 6.4 4.3 Nom Max 6.5 6.6 4.4 4.5 1.15 1.45 0 0.1 0.2 0.17 0.22 0.32 0.13 0.15 0.2 0° 10° 6.2 6.4 6.6 0.53 0.65 0.77 0.10 0.3 0.5 0.7 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. 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