MOTOROLA MC14034

SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 623
The MC14034B is a bidirectional 8–bit static parallel/serial, input/output
bus register. The device contains two sets of input/output lines which allows
the bidirectional transfer of data between two buses; the conversion of serial
data to parallel form, or the conversion of parallel data to serial form.
Additionally the serial data input allows data to be entered shift/right, while
shift/left can be accomplished by hard–wiring each parallel output to the
previous parallel bit input.
Other useful applications for this device include pseudo–random code
generation, sample and hold register, frequency and phase–comparator,
address or buffer register, and serial/parallel input/output conversions.
DW SUFFIX
SOIC
CASE 751E
•
•
•
•
Bidirectional Parallel Data Input
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
• Pin–for–Pin Replacement for CD4034B.
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MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
– 0.5 to + 18.0
V
Vin, Vout
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
lin, lout
Input or Output Current (DC or Transient),
per Pin
± 10
mA
PD
Power Dissipation, per Package†
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
260
_C
TL
Lead Temperature (8–Second Soldering)
P SUFFIX
PLASTIC
CASE 709
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
PIN ASSIGNMENT
B8
1
24
VDD
B7
2
23
A8
B6
3
22
A7
B5
4
21
A6
B4
5
20
A5
B3
6
19
A4
B2
7
18
A3
B1
8
17
A2
A ENABLE
9
16
A1
DS
10
15
C
A/B
11
14
A/S
VSS
12
13
P/S
REV 3
1/94
MOTOROLA
Motorola, Inc. 1995
CMOS LOGIC DATA
MC14034B
135
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
5.0
10
15
– 1.2
– 0.25
– 0.62
– 1.8
—
—
—
—
– 1.0
– 0.2
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
—
—
—
—
– 0.7
– 0.14
– 0.35
– 1.1
—
—
—
—
IOL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.010
0.020
0.030
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT
5.0
10
15
3–State Output Leakage Current
ITL
15
Vin = 0 or VDD
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
“1” Level
VIH
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
mAdc
IT = (2.2 µA/kHz) f + IDD
IT = (4.4 µA/kHz) f + IDD
IT = (6.6 µA/kHz) f + IDD
—
± 0.1
—
± 0.0001
± 0.1
µAdc
—
± 3.0
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
MC14034B
136
MOTOROLA CMOS LOGIC DATA
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
Output Rise Time A or B
tTLH = (3.0 ns/pF) CL + 30 ns
tTLH = (1.5 ns/pF) CL + 15 ns
tTLH = (1.1 ns/pF) CL + 10 ns
tTLH
Output Fall Time A or B
tTHL = (1.5 ns/pF) CL + 25 ns
tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL
Propagation Delay Time
A (B) Synchronous Parallel Data Input,
B (A) Parallel Data Output
tPLH, tPHL = (1.7 ns/pF) CL + 440 ns
tPHL, tPHL = (0.66 ns/pF) CL + 172 ns
tPLH, tPHL = (0.5 ns/pF) CL + 120 ns
tPLH,
tPHL
Propagation Delay Time
A (B) Asynchronous Parallel Data Input
B (A) Parallel Data Output
tPLH, tPHL = (1.7 ns/pF) CL + 420 ns
tPLH, tPHL = (0.66 ns/pF) CL + 147 ns
tPLH, tPHL = (0.5 ns/pF) CL + 105 ns
tPLH,
tPHL
Clock Pulse Width
VDD
Vdc
Min
Typ #
Max
5.0
10
15
—
—
—
180
90
65
360
180
130
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
ns
ns
5.0
10
15
Clock Pulse Frequency
Clock Pulse Rise
A, B Input Setup Time
High Level SE, P/S, A/S Pulse Width
Unit
—
—
—
525
205
145
1050
410
290
ns
5.0
10
15
—
—
—
505
180
130
1010
360
260
tWH
5.0
10
15
340
140
110
170
70
55
—
—
—
ns
fcl
5.0
10
15
—
—
—
2.5
6.0
8.0
1.2
3.0
4.0
MHz
tTLH, tTHL
5.0
10
15
—
—
—
—
—
—
15
5
4
µs
tsu
5.0
10
15
100
45
35
35
15
12
—
—
—
ns
tWH
5.0
10
15
600
270
200
200
90
80
—
—
—
ns
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
TRUTH TABLE
“A” Enable
P/S
A/B
A/S
Mode
0
0
0
X
Serial
Synchronous Serial data input, A and B Parallel data outputs disabled.
Operation†
0
0
1
X
Serial
Synchronous Serial data input, B–Parallel data output.
0
1
0
0
Parallel
B Synchronous Parallel data inputs, A–Parallel data outputs disabled.
0
1
0
1
Parallel
B Asynchronous Parallel data inputs, A–Parallel data outputs disabled.
0
1
1
0
Parallel
A–Parallel data inputs disabled, B–Parallel data outputs.
0
1
1
1
Parallel
A–Parallel data inputs disabled, B–Parallel data outputs.
1
0
0
X
Serial
Synchronous serial data input, A–Parallel data output.
1
0
1
X
Serial
Synchronous serial data input, B–Parallel data output.
1
1
0
0
Parallel
B–Synchronous Parallel data input, A–Parallel data output.
1
1
0
1
Parallel
B–Asynchronous Parallel data input, A–Parallel data output.
1
1
1
0
Parallel
A–Synchronous Parallel data input, B–Parallel data output.
1
1
1
1
Parallel
A–Asynchronous Parallel data input, B–Parallel data output.
X = Don’t Care
†Outputs change at positive transition of clock in the serial mode and when the A/S input is low in the parallel mode. During transfer from parallel
to serial operation, A/S should remain low in order to prevent DS transfer into flip–flops.
MOTOROLA CMOS LOGIC DATA
MC14034B
137
EXPANDED BLOCK DIAGRAM
A1
A2
DATA
A4
A5
A3
A6
A7
A8
SERIAL DATA INPUT
ENABLE A
A/B
PARALLEL/SERIAL P/S
CONTROL
LOGIC
8–BIT REGISTER
ASYN/SYN A/S
CLOCK
B1
B2
B3
B4
B5
DATA
B6
B7
B8
OPERATING CHARACTERISTICS
B; when low, the data flows from bus B to bus A.
P/S Input (Parallel/Serial) — This input controls the data
input mode (parallel or serial). When high, the data is transferred to the register in a parallel asynchronous mode or a
parallel synchronous mode (positive clock transition). When
low, the data is entered into the register in a serial synchronous mode (positive clock transition).
A/S Input (Asynchronous/Synchronous to the Clock)
— When this input is high, the data is transferred independently from the clock rate; when low, the clock is enabled and
the data is transferred synchronously.
The MC14034B is composed of eight register cells connected in cascade with additional control logic. Each register
cell is composed of one “D” master–slave flip–flop with separate internal clocks, and two data transfer gates allowing the
data to be transferred bi–directionally from bus A to bus B
and from bus B to bus A, and to be memorized. Besides the
single phase clock and the serial data inputs, the control logic provides four other features:
A Enable Input — When high, this input enables the bus A
data lines.
A/B Input (Data A or B) — This input controls the direction of data flow: when high, the data flows from bus A to bus
LOGIC DIAGRAM
A1
16
A2 A3 A4 A5 A6 A7
17 18 19 20 21 22
A8
23
VDD
VDD
A ENABLE
9
A/B 11
SERIAL DATA 10
*D
FLIP–
FLOP
*D FLIP FLOP
6 STAGES
(SAME AS
STAGE 1)
PARALLEL SERIAL 13
CM
ASYN/SYN 14
D Q
CM CS
CS
VDD
CLOCK 15
8
B1
MC14034B
138
7 6 5 4 3 2
B2 B3 B4 B5 B6 B7
1
B8
MOTOROLA CMOS LOGIC DATA
INPUT
A(B)
tsu
20 ns
20 ns
CLOCK
90%
10%
50%
tPLH
tPHL
OUTPUT
B(A)
tTLH
tTHL
Figure 1. Propagation Delay and Transition Times Waveforms
PROPAGATION AND TRANSITION TIME TEST CIRCUITS
VDD
VDD
CL
A1 A2 A3 A4 A5 A6 A7 A8
A1 A2 A3 A4 A5 A6 A7 A8
A ENABLE
A ENABLE
P/S
P/S
PROGRAMMABLE
PULSE
GENERATOR
PROGRAMMABLE
PULSE
GENERATOR
DS
A/B
DS
A/B
A/S
A/S
C
C
B1 B2 B3 B4 B5 B6 B7 B8
B1 B2 B3 B4 B5 B6 B7 B8
VSS
CL
Figure 2. A Synchronous Data Input, B Parallel
Data Output and Setup Time
MOTOROLA CMOS LOGIC DATA
VSS
Figure 3. B Synchronous Data Input, A Parallel
Data Output and Setup Time
MC14034B
139
VDD
20 ns
20 ns
A1 A2 A3 A4 A5 A6 A7 A8
90%
50%
CLOCK
AE
P/S
10%
VSS
tWH
DS
A/B
PROGRAMMABLE
PULSE
GENERATOR
VDD
tWL
DS
A/S
C
90%
10%
VSS
20 ns
B1 B2 B3 B4 B5 B6 B7 B8
VDD
50%
20 ns
1/f
tWH = tWL = 50% DUTY CYCLE
VSS
CL
CL
CL
CL
CL
CL
CL
CL
Figure 4. Power Dissipation Test Circuit and Waveforms
VDD
VDD
A1 A2 A3 A4 A5 A6 A7 A8
A ENABLE
A1 A2 A3 A4 A5 A6 A7 A8
A ENABLE
SERIAL
DATA
VDD
SERIAL
DATA
P/S
DS
A/B
MC14034B
VDD
P/S
DS
A/B
A/S
A/S
C B1 B2 B3 B4 B5 B6 B7 B8
C B1 B2 B3 B4 B5 B6 B7 B8
SERIAL
DATA
P/S
A/S
CLOCK
Figure 5. 16–Bit Parallel In/Parallel Out, Parallel In/Serial Out,
Serial In/Parallel Out, Serial In/Serial Out Register
MC14034B
140
MOTOROLA CMOS LOGIC DATA
SHIFT LEFT OUTPUT
A ENABLE
AE
P/S
SHIFT LEFT/
SHIFT RIGHT
SHIFT RIGHT
OUTPUT
A1
AE
SHIFT RIGHT
INPUT
REGISTER 1
MC14034B
A8
P/S
P/S
DS
A/B
DS
A/B
A/S
A/S
C B1
CLOCK
A1
AE
A8
REGISTER 2
MC14034B
CB1
B8
B8
SHIFT LEFT
INPUT*
A/S PARALLEL
ENTRY
A/S
COCK
AE
A1
AE
A1
AE
A8
P/S
P/S
DS
A/B
A8
REGISTER 3
MC14034B
DS
A/B
A/S
A/S
C B1
VDD
REGISTER 4
MC14034B
C B1
B8
B8
VDD
A “High” (“Low”) on the Shift Left/Shift Right input allows serial data on the Shift Left Input (Shift Right Input) to enter the register
on the positive transition of the lock signal. A “high” on the “A” Enable Input disables the “A” parallel data lines on Reg. 1 and 2
and enables the “A” data lines on registers 3 and 4 and allows parallel data into registers 1 and 2. Other logic schemes may be
used in place of registers 3 and 4 for parallel loading.
When parallel inputs are not used, Reg. 3 and 4 and associated logic are not required.
*Shift left input must be disabled during parallel entry.
Figure 6. Shift Right/Shift Left with Parallel Inputs
MOTOROLA CMOS LOGIC DATA
MC14034B
141
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 623–05
ISSUE M
24
NOTES:
1. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION (WHEN FORMED
PARALLEL).
13
B
1
12
DIM
A
B
C
D
F
G
J
K
L
M
N
A
F
SEATING
PLANE
C
L
N
D
G
INCHES
MIN
MAX
1.230
1.290
0.500
0.610
0.160
0.220
0.016
0.020
0.050
0.060
0.100 BSC
0.008
0.012
0.125
0.160
0.600 BSC
0_
15_
0.020
0.050
J
M
K
MILLIMETERS
MIN
MAX
31.24
32.77
12.70
15.49
4.06
5.59
0.41
0.51
1.27
1.52
2.54 BSC
0.20
0.30
3.18
4.06
15.24 BSC
0_
15 _
0.51
1.27
P SUFFIX
PLASTIC DIP PACKAGE
CASE 709–02
ISSUE C
24
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
13
B
1
12
A
L
C
N
K
H
F
G
MC14034B
142
D
SEATING
PLANE
M
J
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
31.37
32.13
13.72
14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.03
0.20
0.38
2.92
3.43
15.24 BSC
0_
15_
0.51
1.02
INCHES
MIN
MAX
1.235
1.265
0.540
0.560
0.155
0.200
0.014
0.022
0.040
0.060
0.100 BSC
0.065
0.080
0.008
0.015
0.115
0.135
0.600 BSC
0_
15_
0.020
0.040
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751E–04
ISSUE E
–A–
24
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
13
–B–
12X
P
0.010 (0.25)
1
M
B
M
12
24X
D
J
0.010 (0.25)
M
T A
S
B
S
F
R
C
–T–
SEATING
PLANE
M
22X
G
K
X 45 _
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
15.25
15.54
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.13
0.29
0_
8_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.601
0.612
0.292
0.299
0.093
0.104
0.014
0.019
0.016
0.035
0.050 BSC
0.009
0.013
0.005
0.011
0_
8_
0.395
0.415
0.010
0.029
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MOTOROLA CMOS LOGIC DATA
◊
*MC14034B/D*
MC14034B
MC14034B/D
143