MOTOROLA MC74HC589AN

SEMICONDUCTOR TECHNICAL DATA
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J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
High–Performance Silicon–Gate CMOS
The MC54/74HC589A is similar in function to the HC597, which is not a
3–state device. The device inputs are compatible with standard CMOS
outputs, with pullup resistors, they are compatible with LSTTL outputs.
This device consists of an 8–bit storage latch which feeds parallel data to
an 8–bit shift register. Data can also be loaded serially (see Function Table).
The shift register output, QH, is a three–state output, allowing this device to
be used in bus–oriented systems.
The HC589A directly interfaces with the Motorola SPI serial data port on
CMOS MPUs and MCUs.
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 526 FETs or 131.5 Equivalent Gates
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
1
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
16
1
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
LOGIC DIAGRAM
SERIAL
DATA
INPUT
SA
A
B
PARALLEL
DATA
INPUTS
C
D
E
F
G
H
LATCH CLOCK
SHIFT CLOCK
SERIAL SHIFT/
PARALLEL LOAD
OUTPUT ENABLE
PIN ASSIGNMENT
14
B
1
16
15
C
2
15
1
D
3
14
2
E
4
13
F
5
12
SA
SERIAL SHIFT/
PARALLEL LOAD
LATCH CLOCK
G
6
11
SHIFT CLOCK
H
7
10
OUTPUT ENABLE
GND
8
9
VCC = PIN 16
GND = PIN 8
3
4
5
DATA
LATCH
SHIFT
REGISTER
6
7
9
12
QH
SERIAL
DATA
OUTPUT
VCC
A
QH
11
13
10
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
10/95
 Motorola, Inc. 1995
1
REV 0
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MC54/74HC589A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 35
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
TSSOP Package†
750
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
TBD
500
400
ns
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
VOH
Vin = VIH or VIL |Iout|
|Iout|
|Iout|
VOL
Maximum Low–Level Output
Voltage
Vin = VIH
|Iout|
20 µA
Vin = VIH or VIL |Iout|
|Iout|
|Iout|
MOTOROLA
2.4 mA
6.0 mA
7.8 mA
2
2.4 mA
6.0 mA
7.8 mA
V
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC54/74HC589A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Symbol
Parameter
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
Unit
µA
IOZ
Maximum Three–State Leakage
Current
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
± 0.5
± 5.0
± 10
µA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0
4
40
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
– 55 to
25_C
85_C
125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 2 and 8)
2.0
3.0
4.5
6.0
6.0
TBD
30
35
4.8
TBD
24
28
4.0
TBD
20
24
MHz
tPLH,
tPHL
Maximum Propagation Delay, Latch Clock to QH
(Figures 1 and 8)
2.0
3.0
4.5
6.0
175
100
40
30
225
110
50
40
275
125
60
50
ns
tPLH,
tPHL
Maximum Propagation Delay, Shift Clock to QH
(Figures 2 and 8)
2.0
3.0
4.5
6.0
160
90
30
25
200
130
40
30
240
160
48
40
ns
tPLH,
tPHL
Maximum Propagation Delay, Serial Shift/Parallel Load to QH
(Figures 4 and 8)
2.0
3.0
4.5
6.0
160
90
30
25
200
130
40
30
240
160
48
40
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to QH
(Figures 3 and 9)
2.0
3.0
4.5
6.0
150
80
27
23
170
100
30
25
200
130
40
30
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to QH
(Figures 3 and 9)
2.0
3.0
4.5
6.0
150
80
27
23
170
100
30
25
200
130
40
30
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 8)
2.0
3.0
4.5
6.0
60
TBD
12
10
75
TBD
15
13
90
TBD
18
15
ns
Maximum Input Capacitance
—
10
10
10
pF
Maximum Three–State Output Capacitance (Output in
High–Impedance State)
—
15
15
15
pF
Cin
Cout
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
50
Power Dissipation Capacitance (Per Package)*
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC54/74HC589A
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
– 55 to
25_C
85_C
125_C
Unit
tsu
Minimum Setup Time, A–H to Latch Clock
(Figure 5)
2.0
3.0
4.5
6.0
100
TBD
20
17
125
TBD
25
21
150
TBD
30
26
ns
tsu
Minimum Setup Time, Serial Data Input SA to Shift Clock
(Figure 6)
2.0
3.0
4.5
6.0
100
TBD
20
17
125
TBD
25
21
150
TBD
30
26
ns
tsu
Minimum Setup Time, Serial Shift/Parallel Load to Shift Clock
(Figure 7)
2.0
3.0
4.5
6.0
100
TBD
20
17
125
TBD
25
21
150
TBD
30
26
ns
th
Minimum Hold Time, Latch Clock to A–H
(Figure 5)
2.0
3.0
4.5
6.0
25
TBD
5
5
30
TBD
6
6
40
TBD
8
7
ns
th
Minimum Hold Time, Shift Clock to Serial Data Input SA
(Figure 6)
2.0
3.0
4.5
6.0
5
5
5
5
5
5
5
5
5
5
5
5
ns
tw
Minimum Pulse Width, Shift Clock
(Figure 2)
2.0
3.0
4.5
6.0
75
TBD
15
13
95
TBD
19
16
110
TBD
23
19
ns
tw
Minimum Pulse Width, Latch Clock
(Figure 1)
2.0
3.0
4.5
6.0
80
TBD
16
14
100
TBD
20
17
120
TBD
24
20
ns
tw
Minimum Pulse Width, Serial Shift/Parallel Load
(Figure 4)
2.0
3.0
4.5
6.0
80
TBD
16
14
100
TBD
20
17
120
TBD
24
20
ns
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
TBD
500
400
1000
TBD
500
400
1000
TBD
500
400
ns
tr, tf
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC589A
FUNCTION TABLE
Inputs
Resulting Function
Output
Enable
Serial Shift/
Parallel Load
Latch
Clock
Shift
Clock
Serial
Input
SA
Parallel
Inputs
A–H
Data
Latch
Contents
Shift
Register
Contents
Output
QH
Force output into high
impedance state
H
X
X
X
X
X
X
X
Z
Load parallel data into
data latch
L
H
L, H,
X
a–h
a–h
U
U
Transfer latch contents to
shift register
L
L
L, H,
X
X
X
U
LRN → SRN
LRH
Contents of input latch
and shift register are
unchanged
L
H
L, H,
L, H,
X
X
U
U
U
Load parallel data into
data latch and shift
register
L
L
X
X
a–h
a–h
a–h
h
Shift serial data into shift
register
L
H
D
X
*
SRA = D,
SRN → SRN+1
SRG → SRH
Load parallel data in data
latch and shift serial data
into shift register
L
H
D
a–h
a–h
SRA = D,
SRN → SRN+1
SRG → SRH
Operation
X
LR = latch register contents
SR = shift register contents
a–h = data at parallel data inputs A–H
D = data (L, H) at serial data input SA
High–Speed CMOS Logic Data
DL129 — Rev 6
U = remains unchanged
X = don’t care
Z = high impedance
* = depends on Latch Clock input
5
MOTOROLA
MC54/74HC589A
SWITCHING WAVEFORMS
tr
LATCH CLOCK
tf
1/fmax
VCC
90%
50%
10%
tw
tw
GND
SHIFT CLOCK
GND
tPLH
tPHL
tPLH
90%
50%
10%
QH
VCC
50%
QH
tTLH
tPHL
50%
tTHL
Figure 1. (Serial Shift/Parallel Load = L)
Figure 2. (Serial Shift/Parallel Load = H)
VCC
OUTPUT
ENABLE
50%
GND
tPZL
tPLZ
tPZH
QH
SERIAL SHIFT/
PARALLEL LOAD
HIGH
IMPEDANCE
50%
QH
tw
tPHZ
50%
10%
VOL
90%
VOH
QH
VCC
50%
50%
tPLH
tPHL
GND
50%
HIGH
IMPEDANCE
Figure 3.
Figure 4.
DATA VALID
A–H
DATA VALID
VCC
SA
50%
VCC
50%
GND
tsu
LATCH CLOCK
GND
th
tsu
th
SHIFT CLOCK
50%
Figure 5.
50%
Figure 6.
TEST POINT
SERIAL SHIFT/
PARALLEL LOAD
OUTPUT
VCC
DEVICE
UNDER
TEST
50%
GND
tsu
SHIFT CLOCK
CL*
50%
* Includes all probe and jig capacitance
Figure 7.
MOTOROLA
Figure 8. Test Circuit
6
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC589A
TEST CIRCUIT
TEST POINT
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 kΩ
OUTPUT
DEVICE
UNDER
TEST
CL*
* Includes all probe and jig capacitance
Figure 9.
PIN DESCRIPTIONS
DATA INPUTS
Shift Clock (Pin 11)
Parallel data inputs. Data on these inputs are stored in the
data latch on the rising edge of the Latch Clock input.
Serial shift clock. A low–to–high transition on this input
shifts data on the serial data input into the shift register and
data in stage H is shifted out QH, being replaced by the data
previously stored in stage G.
SA (Pin 14)
Latch Clock (Pin 12)
A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Data latch clock. A low–to–high transition on this input
loads the parallel data on inputs A–H into the data latch.
Serial data input. Data on this input is shifted into the shift
register on the rising edge of the Shift Clock input if Serial
Shift/Parallel Load is high. Data on this input is ignored when
Serial Shift/Parallel Load is low.
Output Enable (Pin 10)
Active–low output enable A high level applied to this pin
forces the QH output into the high impedance state. A low
level enables the output. This control does not affect the
state of the input latch or the shift register.
CONTROL INPUTS
Serial Shift/Parallel Load (Pin 13)
OUTPUT
Shift register mode control. When a high level is applied to
this pin, the shift register is allowed to serially shift data.
When a low level is applied to this pin, the shift register accepts parallel data from the data latch.
High–Speed CMOS Logic Data
DL129 — Rev 6
QH (Pin 9)
Serial data output. This pin is the output from the last stage
of the shift register. This is a 3–state output.
7
MOTOROLA
MC54/74HC589A
TIMING DIAGRAM
SHIFT CLOCK
SERIAL DATA
INPUT, SA
OUTPUT ENABLE
SERIAL SHIFT/
PARALLEL LOAD
LATCH CLOCK
PARALLEL
DATA
INPUTS
A
L
H
L
L
B
L
L
L
L
C
L
H
L
L
D
L
L
L
L
E
L
H
L
H
F
L
H
L
H
G
L
L
L
L
H
L
H
H
H
QH
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
HIGH IMPEDANCE
H
L
H
SERIAL SHIFT
RESET LATCH
LOAD LATCH PARALLEL LOAD
AND SHIFT REGISTER
SHIFT REGISTER
MOTOROLA
H
L
H
L
SERIAL SHIFT
LOAD LATCH
8
H
L
H
L
L
L
H
H H
SERIAL
SHIFT
SERIAL SHIFT
PARALLEL LOAD
SHIFT REGISTER
L
PARALLEL LOAD, LATCH
AND SHIFT REGISTER
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC589A
LOGIC DETAIL
OUTPUT ENABLE
SA
SHIFT CLOCK
10
14
11
SERIAL SHIFT/ 13
PARALLEL LOAD
LATCH CLOCK
A
12
15
STAGE A
D
Q
C
D
S
C Q
R
STAGE B
B
1
D
Q
C
D
S
C Q
R
PARALLEL
DATA
INPUTS
C
D
E
F
G
2
STAGE C*
3
STAGE D*
4
STAGE E*
5
STAGE F*
6
STAGE G*
STAGE H
H
7
D
VCC
Q
C
D
S
C Q
R
9
QH
*NOTE: Stages C thru G (not shown in detail) are identical to stages A and B above.
High–Speed CMOS Logic Data
DL129 — Rev 6
9
MOTOROLA
MC54/74HC589A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
–A
–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
–B
–
L
C
DIM
A
B
C
D
E
F
G
J
K
L
M
N
–T
K
N
SEATING
–
PLANE
E
M
F
J 16 PL
0.25 (0.010)
G
D 16 PL
0.25 (0.010)
T A
M
9
1
8
T B
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
–A
–
16
M
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T
–
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
M
M
J
G
T A
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
16
1
P 8 PL
0.25 (0.010)
8
M
B
M
G
K
F
R X 45°
C
–T
SEATING
–
PLANE
MOTOROLA
J
M
D 16 PL
0.25 (0.010)
M
T
B
S
A
S
10
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
6.35
0.250 0.270
6.85
3.69
0.145 0.175
4.44
0.39
0.015 0.021
0.53
1.02
0.040 0.070
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.21
0.008 0.015
0.38
2.80
0.110 0.130
3.30
7.50
0.295 0.305
7.74
0°
0°
10°
10°
0.020 0.040
0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B
–
MILLIMETERS
MIN
MAX
19.05 19.93
6.10
7.49
—
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
15°
0°
1.01
0.51
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
S
S
INCHES
MIN
MAX
0.750 0.785
0.240 0.295
—
0.200
0.015 0.020
0.050 BSC
0.055 0.065
0.100 BSC
0.008 0.015
0.125 0.170
0.300 BSC
15°
0°
0.020 0.040
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0°
7°
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC589A
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
ÉÉ
ÇÇ
ÇÇ
ÉÉ
ÇÇ
ÉÉ
ÇÇ
ÉÉ
S
S
K
K1
2X
L/2
16
9
J1
B
–U–
L
SECTION N–N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
–V–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
M
N
F
DETAIL E
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
H
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
G
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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High–Speed CMOS Logic Data
DL129 — Rev 6
◊
CODELINE
*MC54/74HC58A9/D*
11
MC54/74HC58A9/D
MOTOROLA