MOTOROLA MC54HC595AJ

SEMICONDUCTOR TECHNICAL DATA
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High–Performance Silicon–Gate CMOS
The MC54/74HC595A is identical in pinout to the LS595. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC595A consists of an 8–bit shift register and an 8–bit D–type latch
with three–state parallel outputs. The shift register accepts serial data and
provides a serial output. The shift register also provides parallel data to the
8–bit latch. The shift register and latch have independent clock inputs. This
device also has an asynchronous reset for the shift register.
The HC595A directly interfaces with the Motorola SPI serial data port on
CMOS MPUs and MCUs.
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 328 FETs or 82 Equivalent Gates
• Improvements over HC595
— Improved Propagation Delays
— 50% Lower Quiescent Power
— Improved Input Noise and Latchup Immunity
16
1
A
1
SHIFT
REGISTER
LATCH
SHIFT 11
CLOCK
10
RESET
1
1
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
QA
1
QB
2
QC
3
QD
4
QE
5
QF
6
QG
7
QH
SQH
PARALLEL
DATA
OUTPUTS
SERIAL
DATA
OUTPUT
VCC = PIN 16
GND = PIN 8
10/95
 Motorola, Inc. 1995
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
16
Ceramic
Plastic
SOIC
TSSOP
PIN ASSIGNMENT
9
LATCH 12
CLOCK
OUTPUT 13
ENABLE
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
15
14
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
LOGIC DIAGRAM
SERIAL
DATA
INPUT
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
REV 6
QB
1
16
VCC
QC
2
15
QA
QD
3
14
A
QE
4
13
OUTPUT ENABLE
QF
5
12
LATCH CLOCK
QG
6
11
SHIFT CLOCK
QH
7
10
RESET
GND
8
9
SQH
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MC54/74HC595A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 35
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
TSSOP Package†
750
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
DC Supply Voltage (Referenced to GND)
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
DC Input Voltage, Output Voltage
(Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
Minimum High–Level Output
Voltage, QA – QH
Vin = VIH or VIL
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
VOH
Vin = VIH or VIL |Iout|
|Iout|
VOL
Maximum Low–Level Output
Voltage, QA – QH
6.0 mA
7.8 mA
Vin = VIH or VIL
|Iout|
20 µA
Vin = VIH or VIL |Iout|
|Iout|
6.0 mA
7.8 mA
V
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC54/74HC595A
DC ELECTRICAL CHARACTERISTICS (Continued)
Guaranteed Limit
Symbol
VOH
Parameter
Test Conditions
Minimum High–Level Output
Voltage, SQH
Vin = VIH or VIL
IIoutI
20 µA
Vin = VIH or VIL IIoutI
IIoutI
VOL
Maximum Low–Level Output
Voltage, SQH
4.0 mA
5.2 mA
Vin = VIH or VIL
IIoutI
20 µA
Vin = VIH or VIL IIoutI
IIoutI
4.0 mA
5.2 mA
VCC
V
– 55 to
25_C
85_C
125_C
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
Unit
V
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
IOZ
Maximum Three–State Leakage
Current, QA – QH
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
± 0.5
± 5.0
± 10
µA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
lout = 0 µA
6.0
4.0
40
160
µA
VCC
V
– 55 to
25_C
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
85_C
125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH,
tPHL
Maximum Propagation Delay, Shift Clock to SQH
(Figures 1 and 7)
2.0
4.5
6.0
140
28
24
175
35
30
210
42
36
ns
tPHL
Maximum Propagation Delay, Reset to SQH
(Figures 2 and 7)
2.0
4.5
6.0
145
29
25
180
36
31
220
44
38
ns
tPLH,
tPHL
Maximum Propagation Delay, Latch Clock to QA – QH
(Figures 3 and 7)
2.0
4.5
6.0
140
28
24
175
35
30
210
42
36
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to QA – QH
(Figures 4 and 8)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to QA – QH
(Figures 4 and 8)
2.0
4.5
6.0
135
27
23
170
34
29
205
41
35
ns
tTLH,
tTHL
Maximum Output Transition Time, QA – QH
(Figures 3 and 7)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tTLH,
tTHL
Maximum Output Transition Time, SQH
(Figures 1 and 7)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Cin
Cout
Maximum Input Capacitance
—
10
10
10
pF
Maximum Three–State Output Capacitance (Output in
High–Impedance State), QA – QH
—
15
15
15
pF
Symbol
Parameter
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
300
pF
2
* Used to determine the no–load dynamic power consumption: PD = CPD VCC f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Package)*
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC54/74HC595A
TIMING REQUIREMENTS (Input tr = tf = 6.0 ns)
Guaranteed Limit
VCC
V
25_C to
– 55_C
85_C
125_C
tsu
Minimum Setup Time, Serial Data Input A to Shift Clock
(Figure 5)
2.0
4.5
6.0
50
10
9.0
65
13
11
75
15
13
ns
tsu
Minimum Setup Time, Shift Clock to Latch Clock
(Figure 6)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
th
Minimum Hold Time, Shift Clock to Serial Data Input A
(Figure 5)
2.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
trec
Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 2)
2.0
4.5
6.0
50
10
9.0
65
13
11
75
15
13
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tw
Minimum Pulse Width, Shift Clock
(Figure 1)
2.0
4.5
6.0
50
10
9.0
65
13
11
75
15
13
ns
tw
Minimum Pulse Width, Latch Clock
(Figure 6)
2.0
4.5
6.0
50
10
9.0
65
13
11
75
15
13
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
Symbol
Parameter
Unit
FUNCTION TABLE
Inputs
Operation
Reset
Serial
Input
A
Shift
Clock
X
Resulting Function
L, H,
L
L
U
Serial
Output
SQH
L
L, H,
L
D → SRA;
SRN → SRN+1
U
SRG → SRH
U
L, H,
L
U
U
U
U
L
U
SRN → LRN
U
SRN
L
*
U
*
U
X
L
*
**
*
Enabled
X
H
*
**
*
Z
Latch
Clock
Reset shift register
L
X
Shift data into shift
register
H
D
Shift register remains
unchanged
H
X
L, H,
Transfer shift register
contents to latch register
H
X
L, H,
Latch register remains
unchanged
X
X
X
L, H,
Enable parallel outputs
X
X
X
Force outputs into high
impedance state
X
X
X
SR = shift register contents
LR = latch register contents
MOTOROLA
D = data (L, H) logic level
U = remains unchanged
Output
Enable
Shift
Register
Contents
Latch
Register
Contents
X = don’t care
Z = high impedance
4
Parallel
Outputs
QA – QH
U
* = depends on Reset and Shift Clock inputs
** = depends on Latch Clock input
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC595A
PIN DESCRIPTIONS
INPUTS
Latch Clock (Pin 12)
A (Pin 14)
Storage Latch Clock Input. A low–to–high transition on this
input latches the shift register data.
Serial Data Input. The data on this pin is shifted into the
8–bit serial shift register.
Output Enable (Pin 13)
Active–low Output Enable. A low on this input allows the
data from the latches to be presented at the outputs. A high
on this input forces the outputs (QA–QH) into the high–
impedance state. The serial output is not affected by this
control unit.
CONTROL INPUTS
Shift Clock (Pin 11)
Shift Register Clock Input. A low– to–high transition on this
input causes the data at the Serial Input pin to be shifted into
the 8–bit shift register.
OUTPUTS
QA – QH (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Noninverted, 3–state, latch outputs.
Reset (Pin 10)
SQH (Pin 9)
Active–low, Asynchronous, Shift Register Reset Input. A
low on this pin resets the shift register portion of this device
only. The 8–bit latch is not affected.
Noninverted, Serial Data Output. This is the output of the
eighth stage of the 8–bit shift register. This output does not
have three–state capability.
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
MC54/74HC595A
SWITCHING WAVEFORMS
tr
SHIFT
CLOCK
tw
tf
VCC
VCC
90%
50%
10%
tw
GND
GND
tPHL
1/fmax
tPLH
50%
OUTPUT
SQH
tPHL
90%
50%
10%
OUTPUT
SQH
50%
RESET
trec
VCC
SHIFT
CLOCK
tTLH
50%
GND
tTHL
Figure 1.
LATCH
CLOCK
Figure 2.
OUTPUT
ENABLE
VCC
50%
GND
tPLH
VCC
50%
GND
tPZL
tPHL
OUTPUT Q
OUTPUT Q
tTLH
VOL
90%
VOH
HIGH
IMPEDANCE
Figure 4.
SHIFT
CLOCK
VCC
tsu
GND
LATCH
CLOCK
th
VCC
50%
VCC
50%
GND
50%
LATCH
CLOCK
10%
tTHL
VALID
tsu
tPHZ
50%
Figure 3.
SERIAL
INPUT A
HIGH
IMPEDANCE
50%
tPZH
90%
QA–QH 50%
OUTPUTS 10%
tPLZ
VCC
50%
GND
tw
GND
Figure 6.
Figure 5.
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
* Includes all probe and jig capacitance
CL*
* Includes all probe and jig capacitance
Figure 7.
MOTOROLA
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 kΩ
Figure 8.
6
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC595A
EXPANDED LOGIC DIAGRAM
OUTPUT
ENABLE
13
LATCH
CLOCK
12
SERIAL
DATA
INPUT A
14
D
D
Q
SRA
Q
15
QA
LRA
R
Q
D
D
SRB
Q
1
QB
LRB
R
Q
D
D
SRC
Q
2
QC
LRC
R
Q
D
D
SRD
Q
3
QD
LRD
PARALLEL
DATA
OUTPUTS
R
Q
D
D
SRE
Q
4
QE
LRE
R
Q
D
D
SRF
Q
5
QF
LRF
R
Q
D
D
SRG
Q
6
QG
LRG
R
SHIFT
CLOCK
Q
D
11
D
SRH
Q
7
QH
LRH
R
RESET
10
High–Speed CMOS Logic Data
DL129 — Rev 6
9
7
SERIAL
DATA
OUTPUT SQH
MOTOROLA
MC54/74HC595A
TIMING DIAGRAM
SHIFT
CLOCK
SERIAL DATA
INPUT A
RESET
LATCH
CLOCK
OUTPUT
ENABLE
QA
QB
QC
QD
QE
QF
QG
QH
SERIAL DATA
OUTPUT SQH
NOTE:
MOTOROLA
implies that the output is in a high–impedance
state.
8
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC595A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
–A
–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
–B
–
L
C
DIM
A
B
C
D
E
F
G
J
K
L
M
N
–T
K
N
SEATING
–
PLANE
E
M
F
J 16 PL
0.25 (0.010)
G
D 16 PL
0.25 (0.010)
T A
M
9
1
8
T B
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
–A
–
16
M
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T
–
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
M
M
J
G
T A
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
16
1
P 8 PL
0.25 (0.010)
8
M
B
M
G
K
F
R X 45°
C
–T
SEATING
–
PLANE
J
M
D 16 PL
0.25 (0.010)
High–Speed CMOS Logic Data
DL129 — Rev 6
M
T
B
S
A
S
9
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
6.35
0.250 0.270
6.85
3.69
0.145 0.175
4.44
0.39
0.015 0.021
0.53
1.02
0.040 0.070
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.21
0.008 0.015
0.38
2.80
0.110 0.130
3.30
7.50
0.295 0.305
7.74
0°
0°
10°
10°
0.020 0.040
0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B
–
MILLIMETERS
MIN
MAX
19.05 19.93
6.10
7.49
—
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
15°
0°
1.01
0.51
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
S
S
INCHES
MIN
MAX
0.750 0.785
0.240 0.295
—
0.200
0.015 0.020
0.050 BSC
0.055 0.065
0.100 BSC
0.008 0.015
0.125 0.170
0.300 BSC
15°
0°
0.020 0.040
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0°
7°
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019
MOTOROLA
MC54/74HC595A
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
ÉÉ
ÇÇ
ÇÇ
ÉÉ
ÇÇ
ÉÉ
ÇÇ
ÉÉ
S
S
K
K1
2X
L/2
16
9
J1
B
–U–
L
SECTION N–N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
–V–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
M
N
F
DETAIL E
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
H
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
G
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CODELINE
*MC54/74HC595A/D*
10
MC54/74HC595A/D
High–Speed CMOS Logic Data
DL129 — Rev 6