SEMICONDUCTOR TECHNICAL DATA L SUFFIX CERAMIC CASE 620 The MC14582B is a CMOS look–ahead carry generator capable of anticipating a carry across four binary adders or groups of adders. The device is cascadable to perform full look–ahead across n–bit adders. Carry, generate–carry, and propagate–carry functions are provided as enumerated in the pin designation table shown below. • • • • • • Expandable to any Number of Bits All Buffered Outputs Low Power Dissipation Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low–power TTL Loads or One Low–Power Schottky TTL Load over the Rated Temperature Range ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages Referenced to VSS) Parameter Symbol VDD DC Supply Voltage Value Unit – 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient), per Pin ± 10 mA PD Power Dissipation, per Package† 500 mW Tstg Storage Temperature – 65 to + 150 _C 260 _C TL P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC TA = – 55° to 125°C for all packages. PIN ASSIGNMENT Lead Temperature (8–Second Soldering) * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C LOGIC EQUATIONS Cn+x = G0 + (P0 Cn) Cn+y = G1 + (P1 G0) + (P1 P0 Cn) G1 1 16 VDD P1 2 15 P2 G0 3 14 G2 P0 4 13 Cin G3 5 12 Cn+x P3 6 11 Cn+y P 7 10 G VSS 8 9 Cn+z Cn+z = G2 + (P2 G1) + (P2 P1 G0) + (P2 P1 P0 Cn) G = G3 + (P3 G2) + (P3 P2 G1) + (P1 P2 P3 G0) P = P3 P2 P1 P0 PIN DESIGNATIONS Designation Pin No’s Function G0, G1, G2, G3 3, 1, 14, 5 Active–Low Carry–Generate Inputs P0, P1, P2, P3 4, 2, 15, 6 Active–Low Carry–Propagate Inputs Cn 13 Carry Input Cn+x, Cn+y Cn+z 12, 11, 9 Carry Outputs G 10 Active–Low Group Carry–Generate Output P 7 Active–Low Group Carry–Propagate Output REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14582B 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol – 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.0 10 15 — — — 4.95 9.95 14.95 — — — Vdc 5.0 10 15 — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — 5.0 5.0 10 15 – 3.0 – 0.64 – 1.6 – 4.2 — — — — – 2.4 – 0.51 – 1.3 – 3.4 – 4.2 – 0.88 – 2.25 – 8.8 — — — — – 1.7 – 0.36 – 0.9 – 2.4 — — — — IOL 5.0 10 15 0.64 1.6 4.2 — — — 0.51 1.3 3.4 0.88 2.25 8.8 — — — 0.36 0.9 2.4 — — — mAdc Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) IDD 5.0 10 15 — — — 5.0 10 20 — — — 0.005 0.010 0.015 5.0 10 20 — — — 150 300 600 µAdc IT 5.0 10 15 Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL “1” Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vdc Vdc IOH Source Sink Total Supply Current**† (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) mAdc IT = (1.4 µA/kHz) f + IDD IT = (2.8 µA/kHz) f + IDD IT = (4.3 µA/kHz) f + IDD µAdc #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. ** The formulas given are for the typical characteristics only at 25_C. ā †To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.005. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. MC14582B 2 MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time tPLH, tPHL = (1.7 ns/pF) CL + 260 ns tPLH, tPHL = (0.66 ns/pF) CL + 107 ns tPLH, tPHL = (0.5 ns/pF) CL + 85 ns tPLH, tPHL VDD Min Typ # Max 5.0 10 15 — — — 100 50 40 200 100 80 5.0 10 15 — — — 345 140 110 690 280 220 Unit ns ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. VDD Cin G0 20 ns PULSE GENERATOR 10% V SS VARIABLE WIDTH CL G3 Vin CL Cn+y G2 VDD 90% 50% Vin Cn+x G1 20 ns Cn+z P0 CL P P1 CL P2 G P3 CL Figure 1. Dynamic Power Dissipation Test Circuit and Waveform Vout = VOH VDD 16 Cin G0 16 Cin G0 Cn+x G1 G3 Cn+z P0 P2 IOH 8 VSS Cn + z P0 G P3 EXTERNAL POWER SUPPLY IOL P P2 Figure 2. Source Current Test Circuit MOTOROLA CMOS LOGIC DATA G3 P1 G P3 Cn + y G2 P P1 Cn + x G1 Cn+y G2 Vout = VOL VDD 8 VSS EXTERNAL POWER SUPPLY Figure 3. Sink Current Test Circuit MC14582B 3 TEST TABLE AC Paths VDD VSS Output To VSS P0 P To VDD Remaining G’s P’s, Cn P’s, Cn Remaining G’s G0 G Cn Cn+x, Cn+y, Cn+z Vout Cin G0 G1 G2 G3 P0 P1 P2 P3 SEE TEST TABLE PULSE GENERATOR DC Data Input Cn+x Cn+y CL Cn+z G’s P’s 20 ns P 20 ns 90% 50% Vin G tPLH VDD 10% tPHL VSS VOH Vout VOL tTHL tTLH Figure 4. Switching Time Test Circuit and Waveforms TYPICAL APPLICATIONS MC14581B Cn Cn+4 Cn Cn+4 Cn Cn+4 Cn Cn+4 16–BIT ALU, RIPPLE CARRY MC14581B Cn Cn G P G0 P0 Cn+x Cn Cn G P Cn Cn+4 G P G P G1 P1 Cn+y G2 P2 Cn+z MC14582B G3 P3 G P 16–BIT ALU, TWO LEVEL LOOK–AHEAD MC14581B Cn G P Cn G0 P0 Cn+x Cn G P Cn Cn G P G1 P1 Cn+y G2 P2 Cn+z MC14582B Cn+4 G P Cn G3 P3 Cn G P G P Cn G0 P0 Cn+x G P Cn Cn Cn+4 G P G P G1 P1 Cn+y G2 P2 Cn+z MC14582B G3 P3 G P 32–BIT ALU, TWO LEVEL LOOK–AHEAD OVER 16–BIT GROUPS MC14581B Cn Cn+4 Cn+4 Cn Cn G P G0 P0 Cn+x Cn Cn G P G1 P1 G P Cn Cn+4 G P Cn+y G2 P2 Cn+z MC14582B Cn Cn+4 Cn G3 P3 G P Cn G P G0 P0 Cn+x G1 P1 Cn MC14582B G P Cn+y COMBINED TWO–LEVEL LOOK–AHEAD AND RIPPLE CARRY ALU MC14581B Cn G P G0 P0 Cn+x Cn Cn G P Cn G P Cn G1 P1 Cn+y G2 P2 Cn+z MC14582B Cn G P G3 P3 G0 P0 Cn+x Cn G P G0 P0 Cn G P Cn G P Cn Cn G P G1 P1 Cn+y G2 P2 Cn+z MC14582B Cn+x Cn+4 G P Cn G0 P0 Cn+x Cn MC14582B G3 P3 G P G1 P1 G P Cn+y MC14582B 64–BIT ALU, FULL–CARRY LOOK–AHEAD IN THREE LEVELS. A AND B INPUTS AND F OUTPUTS ARE NOT SHOWN (MC14581B). MC14582B 4 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D J 16 PL 0.25 (0.010) MOTOROLA CMOS LOGIC DATA M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MC14582B 5 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE M D 16 PL 0.25 (0.010) M T B S A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MC14582B 6 ◊ *MC14582B/D* MOTOROLA CMOS LOGIC DATA MC14582B/D