Revised August 2003 74LCXH32245 Low Voltage 32-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs with Bushold General Description Features The LCXH32245 contains thirty-two non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The device is byte controlled. Each byte has separate control inputs which could be shorted together for full 32-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. ■ 5V tolerant inputs and outputs The LCXH32245 data inputs include bushold, eliminating the need for external pull-up/down resistors to hold unused inputs. The LCXH32245 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. ■ 2.3V to 3.6V VCC specifications provided ■ 4.5 ns tPD max (VCC = 3.3V), 20 µA ICC max ■ Power-off high impedance inputs and outputs ■ Bushold on inputs eliminates the need for external pull-up/down resistors ■ Supports live insertion/withdrawal (Note 1) ■ ±24 mA output drive (VCC = 3.0V) ■ Uses patented noise/EMI reduction circuitry ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human body model > 2000V Machine model > 200V ■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Note 1: To ensure the high-impedance state during power-up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number 74LCXH32245G (Note 2) (Note 3) BGA96A Package Description 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Note 2: Ordering Code “G” indicates Trays. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol © 2003 Fairchild Semiconductor Corporation DS500727 www.fairchildsemi.com 74LCXH32245 Low Voltage 32-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs with Bushold April 2002 74LCXH32245 Connection Diagram Pin Descriptions Pin Names Description OEn Output Enable Input (Active LOW) T/Rn Transmit/Receive Input A0–A31 Side A Inputs/3-STATE Outputs B0–B31 Side B Inputs/3-STATE Outputs FBGA Pin Assignments (Top Thru View) 1 2 A B1 B0 B B3 B2 C B5 B4 D B7 E F 3 4 5 6 T/R1 OE1 A0 A1 GND GND A2 A3 VCC1 VCC1 A4 A5 B6 GND GND A6 A7 B9 B8 GND GND A8 A9 B11 B10 VCC1 VCC1 A10 A11 G B13 B12 GND GND A12 A13 H B14 B15 T/R2 OE2 A15 A14 J B17 B16 T/R3 OE3 A16 A17 K B19 B18 GND GND A18 A19 L B21 B20 VCC2 VCC2 A20 A21 M B23 B22 GND GND A22 A23 N B25 B24 GND GND A24 A25 P B27 B26 VCC2 VCC2 A26 A27 R B29 B28 GND GND A28 A29 T B30 B31 T/R4 OE4 A31 A30 Truth Tables Inputs OE1 Inputs T/R1 Outputs OE3 T/R3 Outputs L L Bus B0–B7 Data to Bus A0–A7 L L Bus B16–B23 Data to Bus A16–A23 L H Bus A0–A7 Data to Bus B0–B7 L H Bus A16–A23 Data to Bus B16–B23 H X HIGH–Z State on A0–A7,B0–B7 H X HIGH–Z State on A16–A23,B16–B23 Inputs OE2 Inputs T/R2 Outputs OE4 T/R4 Outputs L L Bus B8–B15 Data to Bus A8–A15 L L Bus B24–B31 Data to Bus A24–A31 L H Bus A8–A15 Data to Bus B8–B15 L H Bus B24–A31 Data to Bus B24–B31 H X HIGH–Z State on A8–A15,B8–B15 H X HIGH–Z State on A24–A31,B24–B31 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance www.fairchildsemi.com 2 74LCXH32245 Logic Diagrams Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74LCXH32245 Absolute Maximum Ratings(Note 4) Symbol Parameter Value VCC Supply Voltage −0.5 to +7.0 VI T/R, OE −0.5 to +7.0 I/O Ports −0.5 to VCC + 0.5 VO Conditions V V −0.5 to +7.0 DC Output Voltage Units Output in 3-STATE −0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 5) IIK DC Input Diode Current −50 VI < GND IOK DC Output Diode Current −50 VO < GND +50 VO > VCC V mA mA IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current per Supply Pin ±100 mA IGND DC Ground Current per Ground Pin ±100 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions (Note 6) Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage IOH/IOL Output Current TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Min Max Operating 2.0 3.6 Data Retention 1.5 3.6 0 VCC HIGH or LOW State 0 VCC 3-STATE 0 5.5 VCC = 3.0V − 3.6V ±24 VCC = 2.7V − 3.0V ±12 VCC = 2.3V − 2.7V ±8 Units V V V mA −40 85 °C 0 10 ns/V Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Floating or unused control inputs must be HIGH or LOW. DC Electrical Characteristics Symbol VIH Parameter Conditions HIGH Level Input Voltage VIL LOW Level Input Voltage VOH HIGH Level Output Voltage VCC TA = −40°C to +85°C (V) Min 2.3 − 2.7 1.7 2.7 − 3.6 2.0 2.3 − 2.7 VOL LOW Level Output Voltage www.fairchildsemi.com 2.3 − 3.6 0.8 V VCC − 0.2 IOH = −8 mA 2.3 1.8 IOH = −12 mA 2.7 2.2 IOH = −18 mA 3.0 2.4 IOH = −24 mA 3.0 2.2 IOL = 100 µA 2.3 − 3.6 0.2 IOL = 8 mA 2.3 0.6 IOL = 12 mA 2.7 0.4 IOL = 16 mA 3.0 0.4 IOL = 24 mA 3.0 0.55 4 Units V 0.7 2.7 − 3.6 IOH = −100 µA Max V V Symbol (Continued) Parameter VCC Conditions TA = −40°C to +85°C (V) II Input Leakage Current 0 ≤ VI ≤ 5.5V II(HOLD) Bushold Input Minimum VIN = 0.7V Drive Hold Current VIN = 1.7V 2.3 − 3.6 2.3 VIN = 0.8V 3.0 VIN = 2.0V II(OD) Bushold Input Over-Drive (Note 7) Current to Change State (Note 8) 2.7 (Note 7) 3.6 (Note 8) IOZ 3-STATE I/O Leakage Min 0 ≤ VO ≤ 5.5V VI = V IH or VIL Units Max ±5.0 45 µA -45 75 −75 300 −300 µA 450 −450 2.3 − 3.6 ±5.0 µA µA IOFF Power-Off Leakage Current VI or VO = 5.5V 0 10 ICC Quiescent Supply Current VI = V CC or GND 2.3–3.6 20 3.6V ≤ VI, VO ≤ 5.5V (Note 9) 2.3–3.6 ±20 ∆ICC Increase in ICC per Input VIH = VCC −0.6V 2.3–3.6 500 µA µA Note 7: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 8: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 9: Outputs disabled or 3-STATE only. AC Electrical Characteristics TA = −40°C to +85°C, RL = 500Ω Symbol Parameter VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V CL = 50 pF CL = 50 pF CL = 30 pF Min Max Min Max Min Max tPHL Propagation Delay 1.0 4.5 1.0 5.2 1.0 5.4 tPLH An to Bn or Bn to An 1.0 4.5 1.0 5.2 1.0 5.4 tPZL Output Enable Time 1.0 6.5 1.0 7.2 1.0 8.5 1.0 6.5 1.0 7.2 1.0 8.5 1.0 6.4 1.0 6.9 1.0 7.7 1.0 6.4 1.0 6.9 1.0 7.7 VCC TA = 25°C (V) Typical CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.8 CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 0.6 CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 −0.8 CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 −0.6 tPZH tPLZ Output Disable Time tPHZ Units ns ns ns Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions Units V V Capacitance Typical Units CIN Symbol Input Capacitance Parameter VCC = Open, VI = 0V or VCC Conditions 7 pF CI/O Input/Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 20 pF 5 www.fairchildsemi.com 74LCXH32245 DC Electrical Characteristics 74LCXH32245 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V, and 2.7V VCC x 2 at VCC = 2.5 ± 0.2V tPZH , tPHZ GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic trise and tfall 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol www.fairchildsemi.com VCC 3.3V ± 0.3V 2.7V 2.5V ± 0.2V Vmi 1.5V 1.5V VCC/2 Vmo 1.5V 1.5V VCC/2 Vx VOL + 0.3V VOL + 0.3V VOL + 0.15V Vy VOH − 0.3V VOH − 0.3V VOH − 0.15V 6 74LCXH32245 Schematic Diagram Generic for LCX Family 7 www.fairchildsemi.com 74LCXH32245 Low Voltage 32-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs with Bushold Physical Dimensions inches (millimeters) unless otherwise noted 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA96A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8