MOTOROLA MC74HC299DW

SEMICONDUCTOR TECHNICAL DATA
# !# $!"
# "#! %# ! High–Performance Silicon–Gate CMOS
The MC74HC299 is identical in pinout to the LS299. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
The HC299 features a multiplexed parallel input/output data port to
achieve full 8–bit handling in a 20 pin package. Due to the large output drive
capability and the 3–state feature, this device is ideally suited for interface
with bus lines in a bus–oriented system.
Two Mode–Select inputs and two Output Enable inputs are used to
choose the mode of operation as listed in the Function Table. Synchronous
parallel loading is accomplished by taking both Mode–Select lines, S1 and
S2, high. This places the outputs in the high–impedance state, which permits
data applied to the data port to be clocked into the register. Reading out of
the register can be accomplished when the outputs are enabled. The
active–low asynchronous Reset overrides all other inputs.
20
1
1
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXDW
SA (SHIFT RIGHT) 11
SH (SHIFT LEFT) 18
CLOCK 12
RESET
MODE S1
SELECT S2
OUTPUT OE1
ENABLES OE2
9
1
19
2
3
3–STATE
PARALLEL DATA PORT
(INPUTS/OUTPUTS)
SERIAL DATA
OUTPUTS
PIN 20 = VCC
PIN 10 = GND
10/95
 Motorola, Inc. 1995
S1
1
20
VCC
OE1
2
19
S2
OE2
3
18
SH
PG/QG
4
17
QH′
PE/QE
5
16
PH/QH
PC/QC
6
15
PF/QF
PA/QA
7
14
PD/QD
QA′
8
13
PB/QB
RESET
9
12
CLOCK
10
11
SA
GND
PA/QA
PB/QB
PC/QC
PD/QD
PE/QE
PF/QF
PG/QG
PH/QH
QA′
QH′
3–1
Plastic
SOIC
PIN ASSIGNMENT
LOGIC DIAGRAM
SERIAL
DATA
INPUTS
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
• Output Drive Capability: 15 LSTTL Loads for QA through QH
10 LSTTL Loads for QA′ and QH′
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates
7
13
6
14
5
15
4
16
8
17
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
REV 6
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MC74HC299
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
Vout
Iin
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
ICC
PD
DC Output Current, per Pin
± 35
mA
DC Supply Current, VCC and GND Pins
± 75
mA
Power Dissipation in Still Air
750
500
mW
Tstg
TL
Storage Temperature
– 65 to + 150
_C
VCC
Vin
DC Supply Voltage (Referenced to GND)
Plastic DIP†
SOIC Package†
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus.
v
v
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Vin, Vout
TA
Min
Max
Unit
2.0
6.0
V
0
V
– 55
VCC
+ 125
0
0
0
1000
500
400
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
_C
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
Guaranteed Limit
– 55 to
25_C
85_C
125_C
1.5
1.5
1.5
3.15
3.15
3.15
4.2
4.2
4.2
Symbol
VIH
Parameter
Minimum High–Level Input
Voltage
Test Conditions
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
6.0 mA (P/Q)
7.8 mA (P/Q)
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
4.0 mA (Q′)
5.2 mA (Q′)
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
6.0 mA (P/Q)
7.8 mA (P/Q)
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
4.0 mA (Q′)
5.2 mA (Q′)
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
6.0
± 0.1
± 1.0
± 1.0
µA
6.0
± 0.5
± 5.0
± 10
µA
VOH
Vin = VIH or VIL |Iout|
|Iout|
Vin = VIH or VIL |Iout|
|Iout|
VOL
Maximum Low–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
Vin = VIH or VIL |Iout|
|Iout|
Vin = VIH or VIL |Iout|
|Iout|
Iin
IOZ
Maximum Input Leakage Current
Maximum Three–State Leakage
Current (QA thru QH)
Vin = VCC or GND
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
2.0
4.5
6.0
Unit
V
V
Vin = VCC or GND
6.0
8
80
160
µA
Iout = 0 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ICC
Maximum Quiescent Supply
Current (per Package)
MOTOROLA
3–2
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC74HC299
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 5)
2.0
4.5
6.0
5.0
25
29
4.0
20
24
3.4
17
20
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to QA′ or QH′
(Figures 1 and 5)
2.0
4.5
6.0
170
34
29
215
43
37
255
51
43
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock to QA thru QH
(Figures 1 and 5)
2.0
4.5
6.0
160
32
27
200
40
34
240
48
41
ns
tPHL
Maximum Propagation Delay, Reset to QA or QH
(Figures 2 and 5)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPHL
Maximum Propagation Delay, Reset to QA′ thru QH′
(Figures 2 and 5)
2.0
4.5
6.0
190
38
32
240
48
41
285
57
48
ns
tPLZ,
tPHZ
Maximum Propagation Delay, OE1, OE2, S1, or S2 to QA thru QH
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tPZL,
tPZH
Maximum Propagation Delay, OE1, OE2, S1, or S2 to QA thru QH
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tTLH,
tTHL
Maximum Output Transition Time, QA thru QH
(Figures 1 and 5)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tTLH,
tTHL
Maximum Output Transition Time, QA′ or QH′
(Figures 1 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Maximum Three–State Output Capacitance
(Output in High–Impedance State), QA thru QH
—
15
15
15
pF
Symbol
Cin
Cout
Parameter
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*, Outputs Enabled
240
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3
MOTOROLA
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MC74HC299
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
tsu
Minimum Setup Time, Mode Select S1 or S2 to Clock
(Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tsu
Minimum Setup Time, Data Inputs SA, SH, PA thru PH to Clock
(Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
th
Minimum Hold Time, Clock to Mode Select S1 or S2
(Figure 4)
2.0
4.5
6.0
120
24
20
150
30
26
180
36
31
ns
th
Minimum Hold Time, Clock to Data Inputs, SA, SH, PA thru PH
(Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
Symbol
trec
tf, tf
Parameter
Unit
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
3–4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC299
FUNCTION TABLE
Inputs
Mode
Select
Mode
Response
Output
Enables
Serial
Inputs
PF/QF
PG/QG
PH/QH
QA′
QH′
L
L
L
L
L
L
L
L
L
L
L
L
Shift Right: QA through QH = Z; DA
FA; FA
FB; etc.
Shift Right: QA through QH = Z; DA
FA; FA
FB; etc.
Shift Right: DA
FA = QA; FA
FB = QB; etc.
D
D
D
QG
QG
QG
Shift Left: QA through QH = Z; DH
FH; FH
FG; etc.
Shift Left: QA through QH = Z; DH
FH; FH
FG; etc.
Shift Left: DH
FH = QH; FH
FG = QG; etc.
QB
QB
QB
D
D
D
PA
PH
PA
PA
PA
PH
PH
PH
Reset
S2
S1
OE1†
OE2†
Clock
DA
DH
PA/QA
PB/QB
PC/QC
Reset
L
L
L
X
L
H
L
X
H
L
L
X
L
L
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
Shift
Right
H
H
H
L
L
L
H
H
H
H
X
L
X
H
L
D
D
D
X
X
X
Shift
Left
H
H
H
H
H
H
L
L
L
H
X
L
X
H
L
X
X
X
D
D
D
Parallel
Load
H
H
H
X
X
X
X
Hold
H
H
H
L
L
L
L
L
L
H
X
L
X
H
L
X
X
X
X
X
X
X
X
X
PD/QD
PE/QE
L
L
L
L
QA through QH = Z
³
³
³
³
³
³
³
³
Parallel Load: PN
³
³
³
³
³ FN
Hold: QA through QH = Z; FN = FN
Hold: QA through QH = Z; FN = FN
Hold: QN = QN
Z = high impedance
D = data on serial input
F = flip–flop (see Logic Diagram)
†When one or both output controls are high the eight input/output terminals are disabled to the high impedance state, however, sequential
operation or clearing of the register is not affected.
PIN DESCRIPTIONS
DATA INPUTS
both output enables are high, the outputs are forced to the
high–impedance state; however, sequential operation or
clearing of the register is not affected.
SA (Pin 11)
Serial data input (Shift Right). Data on this input is shifted
into the shift register on the rising edge of Clock when S2 is
low and S1 is high (shift right mode).
Reset (Pin 9)
Active–low reset. A low on this pin resets all stages of the
register to a low level. The reset operation is asynchronous.
SH (Pin 18)
Serial data input (Shift Left). Data on this input is shifted
into the shift register on the rising edge of Clock when S2 is
high and S1 is low (shift left mode).
S1, S2 (Pins 1, 19)
Mode select inputs. The levels present at these pins determine the shift register’s mode of operation:
PA through PH (Pins 7, 13, 6, 14, 5, 15, 4, 16)
Parallel data port inputs. Data on these pins can be parallel loaded into the shift register on the rising edge of Clock
when both S1 and S2 are high. For any other combination of
S1 and S2, these pins serve as the outputs of the shift
register.
OUTPUTS
CONTROL INPUTS
QA′, QH′ (Pins 8, 17)
Clock (Pin 12)
Serial data outputs. These are the outputs of the first and
last stages of the shift register, respectively. These outputs
are not 3–state outputs and have standard drive capabilities.
S1 = S2 = Low. Hold.
S1 = Low, S2 High. Shift left.
S1 = High, S2 Low. Shift right.
S1 = S2 = High. Parallel load.
Clock input. A low–to–high transition on this pin shifts the
data at each stage to the next stage (shift right or left mode)
or loads the data at the parallel data inputs into the shift register (parallel load mode).
QA through QH (Pins 7, 13, 6, 14, 5, 15, 4, 16)
Parallel data port outputs. Shifted data is present at these
pins when OE1 and OE2 are low. For all other combinations
of OE1 and OE2 these outputs are in the high–impedance
state.
OE1, OE2 (Pins 2, 3)
Active–low output enables. When both OE1 and OE2 are
low, the Outputs QA through QH are enabled. When one or
High–Speed CMOS Logic Data
DL129 — Rev 6
3–5
MOTOROLA
MC74HC299
SWITCHING WAVEFORMS
tr
CLOCK
tw
tf
VCC
VCC
90%
50%
10%
GND
GND
tPHL
tw
1/fmax
tPLH
QA′, QH′,
QA–QH
50%
RESET
QA′, QH′,
QA–QH
tPHL
50%
trec
90%
50%
10%
CLOCK
tTLH
VCC
50%
tTHL
GND
Figure 1.
Figure 2.
VCC
S1 OR S2
GND
VCC
VCC
OE1 OR OE2
50%
GND
tPZL
tPLZ
GND
HIGH
IMPEDANCE
50%
10%
VOL
90%
VOH
50%
tPZL
tPLZ
tPZH
tPHZ
HIGH
IMPEDANCE
50%
tPZH tPHZ
QA–QH
50%
S2 OR S1
QA–QH
HIGH
IMPEDANCE
10%
VOL
90%
VOH
50%
Figure 3a.
HIGH
IMPEDANCE
Figure 3b.
TEST POINT
OUTPUT
VALID
MODE SELECT
OR DATA
CLOCK
VCC
50%
tsu
DEVICE
UNDER
TEST
GND
CL*
th
VCC
50%
GND
* Includes all probe and jig capacitance
Figure 5. Test Circuit
Figure 4.
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
* Includes all probe and jig capacitance
Figure 6. Test Circuit
MOTOROLA
3–6
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC299
EXPANDED LOGIC DIAGRAM
SA
11
8
SR
H
DEMUX O
CLOCK
RESET
12
CLK
LD SL
CLK
SR
9
H
DEMUX O
R
LD SL
SR
SR
H
H
DEMUX O
LD SL
A
CLK CLK
Q
D FA
Q
R
7
CLK CLK
Q
D FB
Q
R
13
CLK CLK
Q
D FC
Q
R
6
CLK CLK
Q
D FD
Q
R
14
CLK CLK
Q
D FE
Q
R
5
CLK CLK
Q
D FF
Q
R
15
CLK CLK
Q
D FG
Q
R
4
CLK CLK
Q
D FH
Q
R
16
QA′
PA/QA
PB/QB
PC/QC
B
SR
O
H
C
DEMUX O
D
LD SL
SR
LD
SL
H
DEMUX O
DETAIL OF DEMULTILPLEXER
LD SL
SR
A
H
DEMUX O
S1
S2
1
19
B
LD
SL
C
SR
H
DEMUX O
D
OE1
OE2
SH
2
SL
SR
H
DEMUX O
3
LD
18
High–Speed CMOS Logic Data
DL129 — Rev 6
LD
SL
17
3–7
PD/QD
PE/QE
PF/QF
PG/QG
PH/QH
QH′
MOTOROLA
MC74HC299
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
–A–
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
–T–
DIM
A
B
C
D
E
F
G
J
K
L
M
N
K
SEATING
PLANE
M
N
E
G
F
J
D
0.25 (0.010)
M
T A
11
–B–
10X
1
M
B
M
10
20X
D
0.010 (0.25)
M
T A
B
S
J
S
F
R X 45 _
C
–T–
18X
G
SEATING
PLANE
K
T B
M
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
P
0.010 (0.25)
M
M
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
–A–
20
20 PL
0.25 (0.010)
20 PL
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
M
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
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CODELINE
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*MC74HC299/D*
MC74HC299/D
High–Speed CMOS Logic Data
DL129 — Rev 6