SEMICONDUCTOR TECHNICAL DATA "! ! ! "!# ! ! ! !! "!"! 1 High–Performance Silicon–Gate CMOS The MC54/74HC354 is identical in pinout to the LS354. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC354 selects one of eight latched binary Data Inputs, as determined by the Address Inputs. The information at the Data Inputs is stored in the transparent 8–bit Data Latch when the Data–Latch Enable pin is held high. The Address information may be stored in the transparent Address Latch, which is enabled by the active–high Address–Enable pin. The device outputs are placed in high–impedance states when Output Enable 1 is high, Output Enable 2 is high, or Output Enable 3 is low. The HC354 has a clocked Data Latch that is not transparent. • • • • • • • J SUFFIX CERAMIC PACKAGE CASE 732–03 20 N SUFFIX PLASTIC PACKAGE CASE 738–03 20 1 20 1 DW SUFFIX SOIC PACKAGE CASE 751D–04 ORDERING INFORMATION MC54HCXXXJ MC74HCXXXN MC74HCXXXDW Output Drive Capability: 15 LSTTL Loads Ceramic Plastic SOIC Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2 to 6V Pinout: 20–Lead Package (Top View) Low Input Current: 1µA High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7A Requirements D7 1 20 VCC Chip Complexity: 326 FETs or 81.5 Equivalent Gates D6 2 19 Y D5 3 18 Y D4 4 17 OE3 D3 5 16 OE2 D2 6 15 OE1 D1 7 14 A0 D0 8 13 A1 Data–Latch 9 Enable 12 A2 LOGIC DIAGRAM DATA INPUTS 8 D0 7 D1 6 D2 5 D3 4 D4 3 D5 2 D6 1 D7 8–BIT DATA LATCH (TRANS– PARENT) 8–BIT MULTI– PLEXER 3–STATE OUTPUT CONTROL 19 18 Y Y 3–STATE DATA OUTPUTS GND 10 DATA–LATCH 9 ENABLE A0 ADDRESS INPUTS 14 13 A1 12 A2 ADDRESS–LATCH 11 ENABLE OE1 OUTPUT ENABLES OE2 OE3 ADDRESS LATCH (TRANS– PARENT) PIN 20 = VCC PIN 10 = GND 15 16 17 10/95 Motorola, Inc. 1995 1 REV 7 11 Address–Latch Enable ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MC54/74HC354 MAXIMUM RATINGS* Symbol VCC Parameter DC Supply Voltage (Referenced to GND) Value Unit – 0.5 to + 7.0 V V Vin DC Input Voltage (Referenced to GND) – 1.5 to VCC + 1.5 Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V DC Input Current, per Pin ± 20 mA Iout DC Output Current, per Pin ± 35 mA ICC DC Supply Current, VCC and GND Pins ± 75 mA PD Power Dissipation in Still Air, Plastic or Ceramic DIP† SOIC Package† 750 500 mW Tstg Storage Temperature Range – 65 to + 150 _C Iin TL This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v _C Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP or SOIC Package Ceramic DIP 260 300 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature Range, All Package Types tr, tf Input Rise/Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min Max Unit 2.0 6.0 V 0 VCC V – 55 + 125 _C 0 0 0 1000 500 400 ns DC CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Condition Guaranteed Limit VCC V –55 to 25°C ≤85°C ≤125°C Unit VIH Minimum High–Level Input Voltage Vout = 0.1V or VCC –0.1V |Iout| ≤ 20µA 2.0 4.5 6.0 1.50 3.15 4.20 1.50 3.15 4.20 1.50 3.15 4.20 V VIL Maximum Low–Level Input Voltage Vout = 0.1V or VCC – 0.1V |Iout| ≤ 20µA 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V Minimum High–Level Output Voltage Vin = VIH or VIL |Iout| ≤ 20µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 4.5 6.0 0.26 0.26 0.33 0.33 0.40 0.40 6.0 ±0.1 ±1.0 ±1.0 VOH |Iout| ≤ 6.0mA |Iout| ≤ 7.8mA Vin =VIH or VIL VOL Maximum Low–Level Output Voltage Vin = VIH or VIL |Iout| ≤ 20µA |Iout| ≤ 6.0mA |Iout| ≤ 7.8mA Vin = VIH or VIL Iin MOTOROLA Maximum Input Leakage Current Vin = VCC or GND 2 V µA High–Speed CMOS Logic Data DL129 — Rev 6 MC54/74HC354 DC CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Condition Guaranteed Limit VCC V –55 to 25°C ≤85°C ≤125°C Unit IOZ Maximum Three–State Leakage Current Output in High–Impedance State Vin = VIL or VIH Vout = VCC or GND 6.0 ±0.5 ±5.0 ±10.0 µA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0µA 6.0 8 80 160 µA NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Symbol Parameter Guaranteed Limit VCC V –55 to 25°C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, D0–D7 to Y or Y (Figures 2 and 6) 2.0 4.5 6.0 210 42 36 265 53 45 315 63 54 ns tPLH, tPHL Maximum Propagation Delay, Data–Latch Enable to Y or Y (Figures 3 and 6) 2.0 4.5 6.0 260 52 44 325 65 55 390 78 66 ns tPLH, tPHL Maximum Propagation Delay, A0–A2 to Y or Y (Figures 2 and 6) 2.0 4.5 6.0 270 54 46 340 68 58 405 81 69 ns tPLH, tPHL Maximum Propagation Delay, Address–Latch Enable to Y or Y (Figures 3 and 6) 2.0 4.5 6.0 270 54 46 340 68 58 405 81 69 ns tPLZ, tPHZ Maximum Propagation Delay, OE1–OE3 to Y or Y (Figures 4 and 7) 2.0 4.5 6.0 160 32 27 200 40 34 240 48 41 ns tPZL, tPZH Maximum Propagation Delay, OE1–OE3 to Y or Y (Figures 4 and 7) 2.0 4.5 6.0 125 25 21 155 31 26 190 38 32 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 6) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns Maximum Input Capacitance 10 10 10 pF Maximum Three–State Output Capacitance (Output in High Impedance State) 15 15 15 pF Cin Cout NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High– Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Package)* 48 pF * Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). High–Speed CMOS Logic Data DL129 — Rev 6 3 MOTOROLA MC54/74HC354 PIN DESCRIPTIONS D0–D7 (Pins 8–1) DATA INPUTS ADDRESS–LATCH ENABLE (Pin 11) These eight data bits are stored in a transparent latch when the Data–Latch Enable pin is active (high). Once enabled, changing inputs will not change the contents of the latch. The latch is transparent to A0, A1 and A2 when enable is inactive (low). The Address–Latch contents are unaffected when enable is held active (high). A0, A1, A2 (Pins 14,13,12) ADDRESS INPUTS OE1, OE2, OE3 (Pins 15,16,17) OUTPUT ENABLES Selects which data bit stored in the Data Latch is routed to the outputs Y and Y. Any of the output enable pins inactive (OE1=High or OE2=High or OE3=Low) causes the outputs (Y and Y) to be in high–impedance states. DATA–LATCH ENABLE (Pin 9) Y, Y (Pins 19,18) The latch is transparent to D0–D7 when enable is inactive (low). The Data–Latch contents are unaffected when enable is held active (high). These 3–state outputs (when not 3–stated) represent the data bit in the Data Latch selected by the Address Latch. TIMING REQUIREMENTS (Input tr = tf = 6 ns) Symbol Parameter Guaranteed Limit VCC V –55 to 25°C ≤85°C ≤125°C Unit tsu Minimum Setup Time, D0–D7 to Data–Latch Enable (Figure 5) 2.0 4.5 6.0 50 10 9 65 13 11 75 15 13 ns tsu Minimum Setup Time, A0–A2 to Address–Latch Enable (Figure 5) 2.0 4.5 6.0 50 10 9 65 13 11 75 15 13 ns th Minimum Hold Time, Data–Latch Enable to D0–D7 (Figure 5) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns th Minimum Hold Time, Address–Latch Enable to A0–A2 (Figure 5) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns tw Minimum Pulse Width, Data–Latch Enable (Figure 3) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns tw Minimum Pulse Width, Address–Latch Enable (Figure 3) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns 1000 500 400 1000 500 400 1000 500 400 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). MOTOROLA 4 High–Speed CMOS Logic Data DL129 — Rev 6 MC54/74HC354 FUNCTION TABLE Address Latch Contents # Inputs Outputs A2 A1 A0 Data–Latch Enable OE1 OE2 OE3 Y Y X X X X X X X X X X X X H X X X H X X X L Z Z Z Z Z Z L L L L H H H H L L H H L L H H L H L H L H L H L L L H D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 L L L L H H H H L L H H L L H H L H L H L H L H H L L H Description Outputs in High–Impedance States Data–Latch is Transparent D0n D0n New Data is Stored in Data–Latch and is D1n Not Alterable D1n D2n D2n D3n D3n D4n D4n D5n D5n D6n D6n D7n D7n # Represents bits in Address–Latch. See Address–Latch Enable pin description. X = Don’t Care; Z = High Impedance; D0–D7 = the data at inputs D0 through D7; D0n–D7n = the data present at inputs D0 through D7 when the Data–Latch Enable pin was taken high. SWITCHING WAVEFORMS tr tf VALID VCC 90% Any Input 10% D0–D7 A0–A2 GND VALID VCC 50% GND tPLH Y or Y 90% tPHL Y or Y 50% 10% tTLH tTHL Figure 1. Figure 2. OE1, OE2 VCC 50% tw Address– Latch Enable tPZL tPLZ High Impedance 50% Y or Y GND tPLH Y or Y GND OE3 VCC tPHL 50% 10% tPZH tPHZ 50% Y or Y 90% 50% VOL VOH High Impedance Figure 3. High–Speed CMOS Logic Data DL129 — Rev 6 Figure 4. 5 MOTOROLA MC54/74HC354 Valid VCC D0–D7 A0–A2 50% GND tsu th Data–Latch Enable VCC 50% GND Figure 5. TEST CIRCUITS TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance CL* *Includes all probe and jig capacitance Figure 6. MOTOROLA CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ and tPZH. 1kΩ Figure 7. 6 High–Speed CMOS Logic Data DL129 — Rev 6 MC54/74HC354 15 Output Enables OE1 16 OE2 OE3 A0 17 14 D Q LE Q Address Inputs A1 13 D Q LE Q A2 12 D Q LE Q Address– 11 Latch Enable D0 8 D LE Q D1 7 D LE Q D2 6 D LE Q D3 5 Data Inputs 19 Y D LE Q D4 4 3–State Data Outputs D LE Q D5 3 18 D Y LE Q D6 2 D LE Q D7 1 D LE Q Data–Latch 9 Enable Figure 8. Expanded Logic Diagram High–Speed CMOS Logic Data DL129 — Rev 6 7 MOTOROLA MC54/74HC354 OUTLINE DIMENSIONS 20 11 1 10 J SUFFIX CERAMIC PACKAGE CASE 732–03 ISSUE E NOTES: 1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONS A AND B INCLUDE MENISCUS. B A L C F DIM A B C D F G H J K L M N N H G D J K M MILLIMETERS MIN MAX 23.88 25.15 6.60 7.49 3.81 5.08 0.38 0.56 1.40 1.65 2.54 BSC 0.51 1.27 0.20 0.30 3.18 4.06 7.62 BSC 0_ 15 _ 0.25 1.02 INCHES MIN MAX 0.940 0.990 0.260 0.295 0.150 0.200 0.015 0.022 0.055 0.065 0.100 BSC 0.020 0.050 0.008 0.012 0.125 0.160 0.300 BSC 0_ 15_ 0.010 0.040 SEATING PLANE N SUFFIX PLASTIC PACKAGE CASE 738–03 ISSUE E –A– 20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B L C –T– K SEATING PLANE M N E G F J D M T A 11 –B– 10X P 0.010 (0.25) 1 M B M 10 20X D 0.010 (0.25) M T A B S J S F R X 45 _ C –T– 18X G K SEATING PLANE M T B M M DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D–04 ISSUE E –A– 20 20 PL 0.25 (0.010) 20 PL 0.25 (0.010) MOTOROLA DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 M 8 High–Speed CMOS Logic Data DL129 — Rev 6 MC54/74HC354 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] –TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 High–Speed CMOS Logic Data DL129 — Rev 6 ◊ CODELINE 9 *MC54/74HC354/D* MC54/74HC354/D MOTOROLA