MOTOROLA MC74HCT245ADW

SEMICONDUCTOR TECHNICAL DATA
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J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
High–Performance Silicon–Gate CMOS
1
The MC54/74HCT245A is identical in pinout to the LS245. This device
may be used as a level converter for interfacing TTL or NMOS outputs to
High Speed CMOS inputs.
The MC54/74HCT245A is a 3–state noninverting transceiver that is
used for 2–way asynchronous communication between data buses. The
device has an active–low Output Enable pin, which is used to place the
I/O ports into high–impedance states. The Direction control determines
whether data flows from A to B or from B to A.
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
20
1
1
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 304 FETs or 76 Equivalent Gates
A2
A3
A
DATA
PORT
A4
A5
A6
A7
A8
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
OUTPUT ENABLE
1
ORDERING INFORMATION
MC54HCTXXXAJ
Ceramic
MC74HCTXXXAN
Plastic
MC74HCTXXXADW
SOIC
MC74HCTXXXASD
SSOP
MC74HCTXXXADT
TSSOP
B2
B3
B4
PIN ASSIGNMENT
B
DATA
PORT
DIRECTION
1
20
VCC
A1
2
19
OUTPUT ENABLE
B7
A2
3
18
B1
B8
A3
4
17
B2
A4
5
16
B3
B5
B6
PIN 20 = VCC
PIN 10 = GND
19
Design Criteria
Value
Units
Internal Gate Count*
76
ea
Internal Gate Propagation Delay
1.0
ns
Internal Gate Power Dissipation
5.0
µW
0.005
pJ
Speed Power Product
A5
6
15
B4
A6
7
14
B5
A7
8
13
B6
A8
9
12
B7
10
11
B8
GND
FUNCTION TABLE
Control Inputs
Output
Enable
* Equivalent to a two–input NAND gate.
Direction
L
Data Transmitted from Bus B to Bus A
L
H
Data Transmitted from Bus A to Bus B
H
X
Buses Isolated (High–Impedance State)
10/95
3–1
Operation
L
X = Don’t Care
 Motorola, Inc. 1995
1
DT SUFFIX
TSSOP PACKAGE
CASE 948E–02
20
B1
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DIRECTION
1
SD SUFFIX
SSOP PACKAGE
CASE 940C–03
20
LOGIC DIAGRAM
A1
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
REV 6
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MC54/74HCT245A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 0.5
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 35
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
SSOP or TSSOP Package†
750
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
(Ceramic DIP)
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
SSOP or TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
Max
Unit
4.5
5.5
V
0
VCC
V
– 55
+ 125
_C
0
500
ns
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
Vin = VIH or VIL
|Iout|
6.0 mA
4.5
3.98
3.84
3.7
Vin = VIH or VIL
|Iout|
20 µA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL
|Iout|
6.0 mA
4.5
0.26
0.33
0.4
Vin = VCC or GND, Pins 1 or 19
5.5
± 0.1
± 1.0
± 1.0
VOH
VOL
Iin
MOTOROLA
Maximum Low–Level Output
Voltage
Maximum Input Leakage Current
3–2
V
µA
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC54/74HCT245A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
5.5
4.0
40
160
µA
IOZ
Maximum Three–State
Leakage Current
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND, I/O Pins
5.5
± 0.5
± 5.0
± 10
µA
Additional Quiescent Supply
Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 µA
Symbol
∆ICC
Parameter
Test Conditions
≥ –55_C
25_C to 125_C
2.9
2.4
5.5
Unit
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
– 55 to
25_C
Parameter
85_C
125_C
Unit
tPLH,
tPHL
Maximum Propagation Delay, A to B or B to A
(Figures 1 and 3)
22
28
33
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to A or B
(Figures 2 and 4)
30
36
42
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to A or 8
(Figures 2 and 4)
30
36
42
ns
tTLH,
tTHL
Maximum Output Transition Time. any Output
(Figures 1 and 3)
12
15
18
ns
Maximum Input Capacitance (Pin 1 or 19)
10
10
10
pF
Maximum Three–State I/O Capacitance, (I/O in High–Impedance State)
15
15
15
pF
Cin
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Enabled Output)*
97
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3
MOTOROLA
MC54/74HCT245A
SWITCHING WAVEFORMS
3.0 V
DIRECTION
1.3 V
1.3 V
GND
3.0 V
tr
tf
INPUT
A OR B
OUTPUT
ENABLE
3.0 V
2.7 V
1.3 V
0.3 V
GND
tPZL
tPHL
A OR B
90%
1.3 V
10%
HIGH
IMPEDANCE
1.3 V
tPZH
A OR B
tTHL
tTLH
10%
VOL
90%
VOH
HIGH
IMPEDANCE
Figure 2.
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
tPHZ
1.3 V
Figure 1.
OUTPUT
DEVICE
UNDER
TEST
CL*
* Includes all probe and jig capacitance
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
* Includes all probe and jig capacitance
Figure 3.
MOTOROLA
tPLZ
GND
tPLH
OUTPUT
B OR A
1.3 V
Figure 4. Test Circuit
3–4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HCT245A
EXPANDED LOGIC DIAGRAM
A1
2
18
A2
3
17
A3
A4
B
DATA
PORT
OUTPUT ENABLE
High–Speed CMOS Logic Data
DL129 — Rev 6
B7
9
11
DIRECTION
B6
8
12
A8
B5
7
13
A7
B4
6
14
A6
B3
5
15
A5
B2
4
16
A
DATA
PORT
B1
B8
1
19
3–5
MOTOROLA
MC54/74HCT245A
OUTLINE DIMENSIONS
20
11
1
10
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
ISSUE E
NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
B
A
L
C
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
N
H
G
D
J
K
M
MILLIMETERS
MIN
MAX
23.88
25.15
6.60
7.49
3.81
5.08
0.38
0.56
1.40
1.65
2.54 BSC
0.51
1.27
0.20
0.30
3.18
4.06
7.62 BSC
0_
15 _
0.25
1.02
INCHES
MIN
MAX
0.940
0.990
0.260
0.295
0.150
0.200
0.015
0.022
0.055
0.065
0.100 BSC
0.020
0.050
0.008
0.012
0.125
0.160
0.300 BSC
0_
15_
0.010
0.040
SEATING
PLANE
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
–A–
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
–T–
K
SEATING
PLANE
M
N
E
G
F
J
D
M
T A
11
–B–
10X
P
0.010 (0.25)
1
M
B
M
10
20X
D
0.010 (0.25)
M
T A
B
S
J
S
F
R X 45 _
C
–T–
18X
G
K
SEATING
PLANE
M
T B
M
M
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
–A–
20
20 PL
0.25 (0.010)
20 PL
0.25 (0.010)
MOTOROLA
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
M
3–6
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HCT245A
OUTLINE DIMENSIONS
SD SUFFIX
PLASTIC SSOP PACKAGE
CASE 940C–03
ISSUE B
K REF
0.12 (0.005)
20X
20
L/2
T U
M
S
V
0.25 (0.010)
S
N
M
11
N
B
L
F
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
DETAIL E
PIN 1
IDENT
1
10
K
–U–
A
–V–
0.20 (0.008)
J
T U
M
J1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION/INTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF K DIMENSION AT MAXIMUM MATERIAL
CONDITION. DAMBAR INTRUSION SHALL NOT
REDUCE DIMENSION K BY MORE THAN 0.07 (0.002)
AT LEAST MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE
ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
K1
S
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SECTION N–N
0.076 (0.003)
–T–
SEATING
PLANE
–W–
C
D
G
DETAIL E
H
20X
0.15 (0.006) T U
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
K REF
0.10 (0.004)
S
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
S
K
K1
2X
L/2
20
11
B
–U–
L
PIN 1
IDENT
J J1
SECTION N–N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
N
F
DETAIL E
–W–
C
D
G
H
DETAIL E
0.100 (0.004)
–T– SEATING
INCHES
MIN
MAX
0.278
0.288
0.205
0.212
0.068
0.078
0.002
0.008
0.024
0.037
0.026 BSC
0.023
0.030
0.003
0.008
0.003
0.006
0.010
0.015
0.010
0.013
0.301
0.311
0_
8_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
M
A
–V–
MILLIMETERS
MIN
MAX
7.07
7.33
5.20
5.38
1.73
1.99
0.05
0.21
0.63
0.95
0.65 BSC
0.59
0.75
0.09
0.20
0.09
0.16
0.25
0.38
0.25
0.33
7.65
7.90
0_
8_
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
PLANE
High–Speed CMOS Logic Data
DL129 — Rev 6
3–7
MOTOROLA
MC54/74HCT245A
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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*MC54/74HCT245A/D*
3–8
MC54/74HCT245A/D
High–Speed CMOS Logic Data
DL129 — Rev 6