MOTOROLA Order this document by MCM32515/D SEMICONDUCTOR TECHNICAL DATA Advance Information 512K x 32 Bit Fast Static RAM Module The MCM32515 is a 16M bit static random access memory module organized as 524,288 words of 32 bits. The module is offered in a 72–lead single in–line memory module (SIMM). Four MCM6246 fast static RAMs, packaged in 36–lead SOJ packages are mounted on a printed circuit board along with eight decoupling capacitors. The MCM6246 is a high–performance CMOS fast static RAM organized as 524,288 words of 8 bits. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM32515 is equipped with output enable (G) and four separate byte enable (E1 – E4) inputs, allowing for greater system flexibility. The G input, when high, will force the outputs to high impedance. Ex high will do the same for byte x. • • • • • • • • • Single 5 V ± 10% Power Supply Fast Access Times: 20/25 ns Three–State Outputs Fully TTL Compatible JEDEC Standard Pinout Power Requirement: 800/740 mA Maximum, Active AC High Board Density SIMM Package Byte Operation: Four Separate Chip Enables, One for Each Byte High Quality Six–Layer FR4 PWB with Separate Internal Power and Ground Planes • Incorporates Motorola’s State–of–the–Art Fast Static RAMs MCM32515 PIN ASSIGNMENT TOP VIEW 72 LEAD SIMM — CASE TBD NC 2 1 NC PD3 4 3 PD0 6 5 PD2 VSS DQ0 8 7 PD1 DQ1 10 9 DQ8 DQ2 12 11 DQ9 14 13 DQ10 16 15 DQ11 18 17 A0 A8 20 19 A1 A9 22 21 A2 24 23 DQ12 DQ5 26 25 DQ13 DQ6 28 27 DQ14 29 DQ15 31 VSS 33 A15 DQ3 VCC A7 DQ4 DQ7 W 30 32 A14 34 E1 36 35 E2 E3 38 37 E4 A16 40 39 A17 VSS 42 41 G DQ24 PIN NAMES DQ16 44 43 A0 – A18 . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Inputs W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Enable E1 – E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Enables DQ0 – DQ31 . . . . . . . . . . . . . . . . . . . . . . Data Input/Output VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground PD0 – PD3 . . . . . . . . . . . . . . . . . . . . . . . . Package Density NC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No Connect DQ17 46 45 DQ25 48 47 DQ26 DQ19 50 49 DQ27 A10 52 51 A3 A11 54 53 A4 A12 56 55 A5 58 57 DQ20 60 59 VCC A6 DQ21 62 61 DQ28 63 DQ29 65 DQ30 67 DQ31 69 A18 71 NC For proper operation of the device, VSS must be connected to ground. DQ18 A13 DQ22 64 DQ23 66 VSS 68 NC 70 NC 72 This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 2 4/7/97 Motorola, Inc. 1997 MOTOROLA FAST SRAM MCM32515 1 FUNCTIONAL BLOCK DIAGRAM 512K x 32 MEMORY MODULE 8 DQ0 – DQ7 DQ0 – DQ7 DQ16 – DQ23 8 A0 – A18 E1 G A0 – A18 E3 E W DQ0 – DQ7 G DQ24 – DQ31 A0 – A18 E2 E W MCM6246 8 DQ8 – DQ15 E W 8 MCM6246 DQ0 – DQ7 A0 – A18 E4 G DQ0 – DQ7 E W G MCM6246 MCM6246 W G VCC VSS A0 – A18 PD0 – PD2 MCM32515 2 GND OPEN MOTOROLA FAST SRAM TRUTH TABLE Ex G W Mode VCC Current Output Cycle H X X Not Selected ISB1 or ISB2 High–Z — L H H Read ICCA High–Z — L L H Read ICCA Dout Read Cycle L X L Write ICCA Din Write Cycle ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS = 0 V) Symbol Value Unit VCC – 0.5 to 7.0 V Voltage Relative to VSS Vin, Vout – 0.5 to VCC + 0.5 V Output Current (per I/O) Iout ± 30 mA Power Dissipation PD 4.0 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C Tstg – 25 to + 125 °C Rating Power Supply Voltage Storage Temperatrue The devices on this module contain circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high impedance circuits. These CMOS memory circuits have been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The module is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained. NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V) Symbol Min Typ Max Unit Supply Voltage (Operating Voltage Range) VCC 4.5 5.0 5.5 V Input High Voltage VIH 2.2 — VCC + 0.3* V Input Low Voltage VIL – 0.5** — 0.8 V Parameter * VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns) ** VIL (min) = – 3.0 V ac (pulse width ≤ 20 ns) DC CHARACTERISTICS Symbol Min Typ Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC) Parameter Ilkg(I) — — ±4 µA Output Leakage Current (G, Ex = VIH, Vout = 0 to VCC) Ilkg(O) — — ±4 µA ICCA — — 760 700 800 740 mA AC Standby Current (Ex = VIH, Cycle time ≥ tAVAV min) ISB1 — 220 240 mA CMOS Standby Current (Ex ≥ VCC – 0.2 V, All Inputs ≥ VCC – 0.2 V or ≤ 0.2 V) ISB2 — 40 60 mA Output Low Voltage (IOL = + 8.0 mA) VOL — — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — — V AC Active Supply Current (G, Ex = VIL, Iout = 0 mA, Cycle time ≥ tAVAV min) MCM32515–20: tAVAV = 20 ns MCM32515–25: tAVAV = 25 ns NOTE: Good decoupling of the local power supply should always be used. CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Characteristic Input Capacitance Input/Output Capacitance MOTOROLA FAST SRAM (All pins except DQ0 – DQ31, W, G, and E1 – E4) (E1 – E4) (W, G) (DQ0 – DQ31) Symbol Typ Max Unit Cin 16 10 20 24 14 32 pF Cout 8 9 pF MCM32515 3 AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Output Load . . . . . . . . . . . . . See Figure 1a Unless Otherwise Noted Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns READ CYCLE TIMING (See Notes 1 and 2) MCM32515–20 Parameter MCM32515–25 Symbol Min Max Min Max Unit Notes Read Cycle Time tAVAV 20 — 25 — ns 3 Address Access Time tAVQV — 20 — 25 ns Enable Access Time tELQV — 20 — 25 ns Output Enable Access Time tGLQV — 7 — 9 ns Output Hold from Address Change tAXQX 5 — 5 — ns Enable Low to Output Active tELQX 5 — 5 — ns 4,5,6 Output Enable to Output Active tGLQX 0 — 0 — ns 4,5,6 Enable High to Output High–Z tEHQZ 0 9 0 10 ns 4,5,6 Output Enable High to Output High–Z tGHQZ 0 9 0 10 ns 4,5,6 Power Up Time tELICCH 0 — 0 — ns Power Down Time tEHICCL — 20 — 25 ns NOTES: 1. W is high for read cycle. 2. E1 – E4 are represented by E in these timing specifications, any combination of Exs may be asserted. 3. All read cycle timing is referenced from the last valid address to the first transitioning address. 4. At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGHQX min, both for a given device and from device to device. 5. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b. 6. This parameter is sampled and not 100% tested. 7. Device is continuously selected (E = VIL, G = VIL). TIMING LIMITS +5V RL = 50 Ω OUTPUT 480 Ω OUTPUT Z0 = 50 Ω 255 Ω 5 pF VL = 1.5 V (a) (b) The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. Figure 1. Test Loads MCM32515 4 MOTOROLA FAST SRAM READ CYCLE 1 (See Note 7 Above) tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID DATA VALID tAVQV READ CYCLE 2 (See Note) tAVAV A (ADDRESS) tELQV Ex (BYTE ENABLE) tEHQZ tELQX G (OUTPUT ENABLE) tGLQV tGHQZ tGLQX Q (DATA OUT) DATA VALID tAVQV VCC SUPPLY CURRENT ICC tELICCH tEHICCL ISB NOTE: Addresses valid prior to or coincident with E going low. MOTOROLA FAST SRAM MCM32515 5 WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) MCM32515–20 Parameter Write Cycle Time MCM32515–25 Symbol Min Max Min Max Unit Notes tAVAV 20 — 25 — ns 3 Address Setup Time tAVWL 0 — 0 — ns Address Valid to End of Write tAVWH 15 — 17 — ns Write Pulse Width tWLWH, tWLEH 15 — 17 — ns Data Valid to End of Write tDVWH 10 — 10 — ns Data Hold Time tWHDX 0 — 0 — ns Write Low to Data High–Z tWLQZ 0 9 0 10 ns 4,5,6 Write High to Output Active tWHQX 5 — 5 — ns 4,5,6 Write Recovery Time tWHAX 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. E1 – E4 are represented by E in these timing specifications, any combination of Exs may be asserted. G is a don‘t care when W is low. 3. All write cycle timing is referenced from the last valid address to the first transitioning address. 4. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b. 5. This parameter is sampled and not 100% tested. 6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device. WRITE CYCLE 1 tAVAV A (ADDRESS) tAVWH tWHAX Ex (BYTE ENABLE) tWLWH W (WRITE ENABLE) tAVWL tDVWH DATA VALID D (DATA IN) tWLQZ Q (DATA OUT) MCM32515 6 tWHDX HIGH–Z tWHQX HIGH–Z MOTOROLA FAST SRAM WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) MCM32515–20 Parameter MCM32515–25 Symbol Min Max Min Max Unit Notes Write Cycle Time tAVAV 20 — 25 — ns 3 Address Setup Time tAVEL 0 — 0 — ns Address Valid to End of Write tAVEH 15 — 17 — ns Enable to End of Write tELEH 15 — 17 — ns Enable to End of Write tELWH 15 — 17 — ns Write Pulse Width tWLEH 15 — 17 — ns Data Valid to End of Write tDVEH 10 — 10 — ns Data Hold Time tEHDX 0 — 0 — ns 4,5 Write Recovery Time tEHAX 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. E1 – E4 are represented by E in these timing specifications, any combination of Exs may be asserted. G is a don’t care when W is low. 3. All write cycle timing is referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition. 5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition. WRITE CYCLE 2 tAVAV A (ADDRESS) tAVEH Ex (BYTE ENABLE) tELEH tELWH tAVEL tEHAX W (WRITE ENABLE) tWLEH tDVEH DATA VALID D (DATA IN) tEHDX HIGH–Z Q (DATA OUT) ORDERING INFORMATION (Order by Full Part Number) MCM 32515 XX XX Motorola Memory Prefix Speed (20 = 20 ns, 25 = 25 ns) Part Number Package (SG = Gold Pad SIMM) Full Part Numbers — MCM32515SG20 MCM32515SG25 MOTOROLA FAST SRAM MCM32515 7 Motorola reserves the right to make changes without further notice to any products herein. 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