MOTOROLA Order this document by MCM6949/D SEMICONDUCTOR TECHNICAL DATA Advance Information MCM6949 1M x 4 Bit Static Random Access Memory The MCM6949 is a 4,194,304 bit static random access memory organized as 1,048,576 words of 4 bits. Static design eliminates the need for external clocks or timing strobes. The MCM6949 is equipped with chip enable (E) and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems. Either input, when high, will force the outputs into high–impedance. The MCM6949 is available in a 400 mil, 32–lead surface–mount SOJ package. • • • • • • Single 3.3 V – 5%, + 10% Power Supply Fast Access Time: 8/10/12/15 ns Equal Address and Chip Enable Access Time All Inputs and Outputs are TTL Compatible Three–State Outputs Power Operation: 195/165/160/155 mA Maximum, Active AC YJ PACKAGE 400 MIL SOJ CASE 857A–02 PIN NAMES A0 – A19 . . . . . . . . . . . . . . . . Address Inputs W . . . . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . . . . Output Enable E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable DQ . . . . . . . . . . . . . . . . . . Data Input/Output NC . . . . . . . . . . . . . . . . . . . . . No Connection VCC . . . . . . . . . . . . . . + 3.3 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 4 4/2/98 Motorola, Inc. 1998 MOTOROLA FAST SRAM MCM6949 1 BLOCK DIAGRAM A A A A A A ROW DECODER MEMORY MATRIX A A A A COLUMN I/O DQ INPUT DATA CONTROL COLUMN DECODER DQ A A A A A A A A A A DQ E W G MCM6949 2 DQ MOTOROLA FAST SRAM PIN ASSIGNMENT MOTOROLA FAST SRAM A 1 32 A A 2 31 A A 3 30 A A 4 29 A A 5 28 A E 6 27 G DQ 7 26 DQ VCC 8 25 VSS VSS 9 24 VCC DQ 10 23 DQ W 11 22 A A 12 21 A A 13 20 A A 14 19 A A 15 18 A A 16 17 NC MCM6949 3 TRUTH TABLE (X = Don’t Care) E G W Mode I/O Pin Cycle Current H X X Not Selected High–Z — ISB1, ISB2 L H H Output Disabled High–Z — ICCA L L H Read Dout Read ICCA L X L Write High–Z Write ICCA ABSOLUTE MAXIMUM RATINGS (See Note) Symbol Value Unit VCC – 0.5 to + 5.0 V Vin, Vout – 0.5 to VCC + 0.5 V Output Current (per I/O) Iout ± 20 mA Power Dissipation PD 1.0 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C Tstg – 55 to + 150 °C Rating Power Supply Voltage Relative to VSS Voltage Relative to VSS for Any Pin Except VCC Storage Temperature — Plastic This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high–impedance circuits. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained. NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. MCM6949 4 MOTOROLA FAST SRAM DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 3.3 V – 5%, + 10%, TA = 0 to + 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Supply Voltage (Operating Voltage Range) VCC 3.0 3.3 3.465 V Input High Voltage VIH 2.2 — VCC + 0.3 V Input Low Voltage VIL – 0.5* — 0.8 V Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC) Ilkg(I) — ± 1.0 µA Output Leakage Current (E = VIH, Vout = 0 to VCC) Ilkg(O) — ± 1.0 µA * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns). DC CHARACTERISTICS Parameter Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V Symbol 0 to + 70°C – 40 to + 85°C Unit POWER SUPPLY CURRENTS Parameter AC Active Supply Current (Iout = 0 mA, VCC = Max) MCM6949–8: tAVAV = 8 ns MCM6949–10: tAVAV = 10 ns MCM6949–12: tAVAV = 12 ns MCM6949–15: tAVAV = 15 ns ICC 195 165 160 155 195 175 170 165 mA AC Standby Current (VCC = Max, E = VIH, No Other Restrictions on Other Inputs) MCM6949–8: tAVAV = 8 ns MCM6949–10: tAVAV = 10 ns MCM6949–12: tAVAV = 12 ns MCM6949–15: tAVAV = 15 ns ISB1 55 50 50 45 55 55 55 50 mA ISB2 15 15 mA Symbol Typ Max Unit All Inputs Except Clocks and DQs E, G, W Cin Cck 4 5 6 8 pF DQ CI/O 5 8 pF CMOS Standby Current (E ≥ VCC – 0.2 V, Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V) (VCC = Max, f = 0 MHz) CAPACITANCE (f = 1.0 MHz, dV = 3.3 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance Input/Output Capacitance MOTOROLA FAST SRAM MCM6949 5 AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 3.3 V – 5%, + 10%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 READ CYCLE TIMING (See Notes 1 and 2) MCM6949–8 P Parameter S b l Symbol MCM6949–10 Min Max Min MCM6949–12 Max Min MCM6949–15 Max Min Max U i Unit N Notes 3 Read Cycle Time tAVAV 8 — 10 — 12 — 15 — ns Address Access Time tAVQV — 8 — 10 — 12 — 15 ns Enable Access Time tELQV — 8 — 10 — 12 — 15 ns Output Enable Access Time tGLQV — 4 — 5 — 6 — 7 ns Output Hold from Address Change tAXQX 2 — 2 — 2 — 2 — ns Enable Low to Output Active tELQX 3 — 3 — 3 — 3 — ns 5, 6, 7 Output Enable Low to Output Active tGLQX 0 — 0 — 0 — 0 — ns 5, 6, 7 Enable High to Output High–Z tEHQZ 0 4 0 5 0 6 0 7 ns 5, 6, 7 Output Enable High to Output High–Z tGHQZ 0 4 0 5 0 6 0 7 ns 5, 6, 7 4 NOTES: 1. W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All read cycle timings are referenced from the last valid address to the first transitioning address. 4. Addresses valid prior to or coincident with E going low. 5. At any given voltage and temperature, tEHQZ max tELQX min, and tGHQZ max tGLQX min, both for a given device and from device to device. 6. Transition is measured ± 200 mV from steady–state voltage. 7. This parameter is sampled and not 100% tested. 8. Device is continuously selected (E ≤ VIL, G ≤ VIL). t t TIMING LIMITS RL = 50 Ω OUTPUT Z0 = 50 Ω VL = 1.5 V The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. Figure 1. AC Test Load MCM6949 6 MOTOROLA FAST SRAM READ CYCLE 1 (See Note 8) tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID DATA VALID tAVQV READ CYCLE 2 (See Note 4) tAVAV A (ADDRESS) tELQV E (CHIP ENABLE) tEHQZ tELQX G (OUTPUT ENABLE) tGLQV tGHQZ tGLQX Q (DATA OUT) HIGH–Z DATA VALID tAVQV SUPPLY CURRENT ICC ISB MOTOROLA FAST SRAM MCM6949 7 WRITE CYCLE 1 (W Controlled; See Notes 1, 2, and 3) MCM6949–8 P Parameter MCM6949–10 MCM6949–12 MCM6949–15 S b l Symbol Min Max Min Max Min Max Min Max U i Unit N Notes Write Cycle Time tAVAV 8 — 10 — 12 — 15 — ns 4 Address Setup Time tAVWL 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 8 — 9 — 10 — 12 — ns Address Valid to End of Write (G High) tAVWH 7 — 8 — 9 — 10 — ns Write Pulse Width tWLWH tWLEH 8 — 9 — 10 — 12 — ns Write Pulse Width (G High) tWLWH tWLEH 7 — 8 — 9 — 10 — ns Data Valid to End of Write tDVWH 5 — 5 — 6 — 7 — ns Data Hold Time tWHDX 0 — 0 — 0 — 0 — ns Write Low to Data High–Z tWLQZ 0 4 0 5 0 6 0 7 ns 5, 6, 7 Write High to Output Active tWHQX 3 — 3 — 3 — 3 — ns 5, 6, 7 Write Recovery Time tWHAX 0 — 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state. 4. All write cycle timings are referenced from the last valid address to the first transitioning address. 5. Transition is measured ± 200 mV from steady–state voltage. 6. This parameter is sampled and not 100% tested. 7. At any given voltage and temperature, tWLQZ max < tWHQX min, both for a given device and from device to device. WRITE CYCLE 1 (W Controlled; See Notes 1, 2, and 3) tAVAV A (ADDRESS) tAVWH tWHAX E (CHIP ENABLE) tWLWH tWLEH W (WRITE ENABLE) tAVWL tDVWH DATA VALID D (DATA IN) tWLQZ Q (DATA OUT) MCM6949 8 tWHDX HIGH–Z tWHQX HIGH–Z MOTOROLA FAST SRAM WRITE CYCLE 2 (E Controlled; See Notes 1, 2, and 3) MCM6949–8 P Parameter MCM6949–10 MCM6949–12 MCM6949–15 S b l Symbol Min Max Min Max Min Max Min Max U i Unit N Notes Write Cycle Time tAVAV 8 — 10 — 12 — 15 — ns 4 Address Setup Time tAVEL 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVEH 7 — 9 — 10 — 12 — ns Address Valid to End of Write (G High) tAVEH 7 — 8 — 9 — 10 — ns Enable Pulse Width tELEH, tELWH 8 — 9 — 10 — 12 — ns 5, 6 Enable Pulse Width (G High) tELEH, tELWH 7 — 8 — 9 — 10 — ns 5, 6 Data Valid to End of Write tDVEH 5 — 5 — 6 — 7 — ns Data Hold Time tEHDX 0 — 0 — 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state. 4. All write cycle timing is referenced from the last valid address to the first transitioning address. 5. If E goes low coincident with or after W goes low, the output will remain in a high–impedance condition. 6. If E goes high coincident with or before W goes high, the output will remain in a high–impedance condition. WRITE CYCLE 2 (E Controlled; See Notes 1, 2, and 3) tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL tELWH tEHAX W (WRITE ENABLE) tDVEH DATA VALID D (DATA IN) tEHDX HIGH–Z Q (DATA OUT) ORDERING INFORMATION (Order by Full Part Number) MCM 6949 XX XX XX Motorola Memory Prefix Shipping Method (R = Tape and Reel, Blank = Rails) Part Number Speed (8 = 8 ns, 10 = 10 ns, 12 = 12 ns, 15 = 15 ns) Package (YJ = 400 mil SOJ) Full Part Numbers — MCM6949YJ8 MCM6949YJ8R MOTOROLA FAST SRAM MCM6949YJ10 MCM6949YJ10R MCM6949YJ12 MCM6949YJ12R MCM6949YJ15 MCM6949YJ15R MCM6949 9 PACKAGE DIMENSIONS YJ PACKAGE 400 MIL SOJ CASE 857A–02 32 F 17 0.17 (0.007) N 1 32 PL 0.17 (0.007) S P 0.17 (0.007) L G T B DETAIL Z 16 -A- S D 32 PL T B S A S T A S NOTE 3 B S S -BE 0.10 (0.004) K DETAIL Z -T- SEATING PLANE R 0.25 (0.010) C S RADIUS S T A S B S NOTE 3 S A S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TO BE DETERMINED AT PLANE -T-. 4. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION A & B INCLUDE MOLD MISMATCH AND ARE DETERMINED AT THE PARTING LINE. 6. 857A-01 IS OBSOLETE, NEW STANDARD 857A-02. DIM A B C D E F G K L N P R S MILLIMETERS MIN MAX 20.83 21.08 10.03 10.29 3.75 3.26 0.50 0.41 2.48 2.24 0.81 0.67 1.27 BSC 1.14 0.89 0.64 BSC 1.14 0.76 11.30 11.05 9.52 9.27 1.01 0.77 INCHES MIN MAX 0.820 0.830 0.395 0.405 0.128 0.148 0.016 0.020 0.088 0.098 0.026 0.032 0.050 BSC 0.035 0.045 0.025 BSC 0.030 0.045 0.435 0.445 0.365 0.375 0.030 0.040 Motorola reserves the right to make changes without further notice to any products herein. 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