MOTOROLA Order this document by MCM6926A/D SEMICONDUCTOR TECHNICAL DATA MCM6926A Advance Information 128K x 8 Bit Fast Static Random Access Memory The MCM6926A is a 1,048,576 bit static random access memory organized as 131,072 words of 8 bits. Static design eliminates the need for external clocks or timing strobes. Output enable (G) is a special control feature that provides increased system flexibility and eliminates bus contention problems. This device meets JEDEC standards for functionality and revolutionary pinout, and is available in a 400 mil plastic small–outline J–leaded package. • • • • • • • Single 3.3 V Power Supply Fully Static — No Clock or Timing Strobes Necessary All Inputs and Outputs Are TTL Compatible Three State Outputs Fast Access Times: 8, 10, 12, 15 ns Center Power and I/O Pins for Reduced Noise Fully 3.3 V BiCMOS BLOCK DIAGRAM A VDD VSS A A A A MEMORY MATRIX 512 ROWS x 256 x 8 COLUMNS ROW DECODER A A WJ PACKAGE 400 MIL SOJ CASE 857A–02 PIN ASSIGNMENT A 1 32 A A 2 31 A A 3 30 A A 4 29 A E 5 28 G DQ 6 27 DQ DQ 7 26 DQ VDD 8 25 VSS VSS 9 24 VDD DQ 10 23 DQ DQ 11 22 DQ W 12 21 A A 13 20 A A 14 19 A A 15 18 A A 16 17 A A A PIN NAMES DQ COLUMN I/O COLUMN DECODER INPUT DATA CONTROL DQ A A A A A A A A A . . . . . . . . . . . . . . . . . . . . . . . Address Input E . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable W . . . . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . . . Output Enable DQ . . . . . . . . . . . . . . . . . Data Input/Output VDD . . . . . . . . . . . . . + 3.3 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . Ground E W G This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice. REV 1 2/25/97 Motorola, Inc. 1997 MOTOROLA FAST SRAM MCM6926A 1 TRUTH TABLE (X = Don’t Care) E G W Mode VDD Current Output Cycle H X X Not Selected ISB1, ISB2 High–Z — L H H Output Disabled IDDA High–Z — L L H Read IDDA Dout Read Cycle L X L Write IDDA High–Z Write Cycle ABSOLUTE MAXIMUM RATINGS (See Note) Symbol Rating Power Supply Voltage Value Unit VDD – 0.5 to + 4.6 V Vin, Vout – 0.5 to VDD + 0.5 V Output Current Iout ± 30 mA Power Dissipation PD 0.6 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C Tstg – 55 to + 125 °C Voltage Relative to VSS for Any Pin Except VDD Storage Temperature — Plastic NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high–impedance circuits. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained. DC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Supply Voltage (Operating Voltage Range) VDD 3.135 3.3 3.6 V Input High Voltage VIH 2.2 — VDD + 0.3** V Input Low Voltage VIL – 0.5* — 0.8 V Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VDD) Ilkg(I) — ± 1.0 µA Output Leakage Current (E = VIH, Vout = 0 to VDD) Ilkg(O) — ± 1.0 µA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA. ** VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA. DC CHARACTERISTICS Parameter MCM6926A 2 MOTOROLA FAST SRAM POWER SUPPLY CURRENTS (See Note 1) 6926A–8 6926A–10 6926A–12 6926A–15 P Parameter S b l Symbol Typ Max Typ Max Typ Max Typ Max U i Unit N Notes AC Active Supply Current (Iout = 0 mA) (VDD = max, f = fmax) IDDA — 150 — 130 — 120 — 110 mA 2, 3, 4 Active Quiescent Current (E = VIL, VDD = max, f = 0 MHz) IDD2 — 80 — 80 — 80 — 80 mA AC Standby Current (E = VIH, VDD = max, f = fmax) ISB1 — 50 — 45 — 40 — 35 mA CMOS Standby Current (VDD = max, f = 0 MHz, E ≥ VDD – 0.2 V, Vin ≤ VSS + 0.2 V, or ≥ VDD – 0.2 V) ISB2 — 20 — 20 — 20 — 20 mA 2, 3, 4 NOTES: 1. Typical current = 25°C @ 3.3 V. 2. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V). 3. All address transition simultaneously low (LSB) and then high (MSB). 4. Data states are all zero. CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Parameter Symbol Typ Max Unit Address Input Capacitance Cin — 6 pF Control Pin Input Capacitance Cin — 6 pF Input/Output Capacitance CI/O — 8 pF MOTOROLA FAST SRAM MCM6926A 3 AC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V + 10%, – 5%, TA = 0 to +70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 READ CYCLE TIMING (See Notes 1 and 2) 6926A–8 P Parameter 6926A–10 6926A–12 6926A–15 S b l Symbol Min Max Min Max Min Max Min Max U i Unit N Notes Read Cycle Time tAVAV 8 — 10 — 12 — 15 — ns 3 Address Access Time tAVQV — 8 — 10 — 12 — 15 ns Enable Access Time tELQV — 8 — 10 — 12 — 15 ns Output Enable Access Time tGLQV — 4 — 5 — 6 — 7 ns Output Hold from Address Change tAXQX 3 — 3 — 3 — 3 — ns Enable Low to Output Active tELQX 3 — 3 — 3 — 3 — ns 4, 5, 6 Output Enable Low to Output Active tGLQX 0 — 0 — 0 — 0 — ns 4, 5, 6 Enable High to Output High–Z tEHQZ — 4 — 5 — 6 — 7 ns 4, 5, 6 Output Enable High to Output High–Z tGHQZ — 4 — 5 — 6 — 7 ns 4, 5, 6 NOTES: 1. W is high for read cycle. 2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles. 3. All read cycle timings are referenced from the last valid address to the first transitioning address. 4. At any given voltage and temperature, tEHQZ max < tELQX min, and tGHQZ max < tGLQX min, both for a given device and from device to device. 5. Transition is measured 200 mV from steady–state voltage. 6. This parameter is sampled and not 100% tested. 7. Device is continuously selected (E = VIL, G = VIL). 8. Addresses valid prior to or coincident with E going low. TIMING LIMITS RL = 50 Ω OUTPUT Z0 = 50 Ω VL = 1.5 V The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. Figure 1. AC Test Load MCM6926A 4 MOTOROLA FAST SRAM READ CYCLE 1 (See Note 7) tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID DATA VALID tAVQV READ CYCLE 2 (See Note 8) tAVAV A (ADDRESS) tAVQV tELQV E (CHIP ENABLE) tEHQZ tELQX G (OUTPUT ENABLE) tGLQV tGHQZ tGLQX Q (DATA OUT) MOTOROLA FAST SRAM DATA VALID MCM6926A 5 WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) 6926A–8 P Parameter 6926A–10 6926A–12 6926A–15 S b l Symbol Min Max Min Max Min Max Min Max U i Unit N Notes Write Cycle Time tAVAV 8 — 10 — 12 — 15 — ns 3 Address Setup Time tAVWL 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 8 — 9 — 10 — 12 — ns Address Valid to End of Write, G High tAVWH 7 — 8 — 9 — 10 — ns Write Pulse Width tWLWH, tWLEH 8 — 9 — 10 — 12 — ns Write Pulse Width, G High tWLWH, tWLEH 7 — 8 — 9 — 10 — ns Data Valid to End of Write tDVWH 4 — 5 — 6 — 7 — ns Data Hold Time tWHDX 0 — 0 — 0 — 0 — ns Write Low to Data High–Z tWLQZ — 4 — 5 — 6 — 7 ns 4,5,6 Write High to Output Active tWHQX 3 — 3 — 3 — 3 — ns 4,5,6 Write Recovery Time tWHAX 0 — 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles. 3. All write cycle timings are referenced from the last valid address to the first transitioning address. 4. Transition is measured 200 mV from steady–state voltage. 5. This parameter is sampled and not 100% tested. 6. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device. WRITE CYCLE 1 tAVAV A (ADDRESS) tAVWH tWHAX E (CHIP ENABLE) tWLEH tWLWH W (WRITE ENABLE) tDVWH tAVWL D (DATA IN) tWHDX DATA VALID tWLQZ Q (DATA OUT) HIGH–Z HIGH–Z tWHQX MCM6926A 6 MOTOROLA FAST SRAM WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) 6926A–8 P Parameter 6926A–10 6926A–12 6926A–15 S b l Symbol Min Max Min Max Min Max Min Max U i Unit N Notes Write Cycle Time tAVAV 8 — 10 — 12 — 15 — ns 3 Address Setup Time tAVEL 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVEH 7 — 8 — 9 — 10 — ns Enable to End of Write tELEH, tELWH 7 — 8 — 9 — 10 — ns Data Valid to End of Write tDVEH 4 — 5 — 6 — 7 — ns Data Hold Time tEHDX 0 — 0 — 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — 0 — 0 — ns 4,5 NOTES: 1. A write occurs during the overlap of E low and W low. 2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles. 3. All write cycle timings are referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition. 5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition. WRITE CYCLE 2 tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL tELWH tEHAX W (WRITE ENABLE) tDVEH D (DATA IN) Q (DATA OUT) MOTOROLA FAST SRAM tEHDX DATA VALID HIGH–Z MCM6926A 7 PACKAGE DIMENSIONS 32–LEAD 400 MIL SOJ CASE 857A–02 F 32 PL 0.17 (0.007) T B S S A S N 32 D 32 PL 0.17 (0.007) S 17 1 T B A S S NOTE 3 DETAIL Z 16 0.17 (0.007) -A- S T A S B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TO BE DETERMINED AT PLANE -T-. 4. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION A & B INCLUDE MOLD MISMATCH AND ARE DETERMINED AT THE PARTING LINE. S P L G -BE C 0.10 (0.004) K DETAIL Z -T- SEATING PLANE S RADIUS R 0.25 (0.010) S T A S B S NOTE 3 DIM A B C D E F G K L N P R S INCHES MIN MAX 0.820 0.830 0.395 0.405 0.128 0.148 0.016 0.020 0.088 0.098 0.026 0.032 0.050 BSC 0.035 0.045 0.025 BSC 0.030 0.045 0.435 0.445 0.365 0.375 0.030 0.040 MILLIMETERS MIN MAX 20.83 21.08 10.03 10.29 3.75 3.26 0.50 0.41 2.48 2.24 0.81 0.67 1.27 BSC 1.14 0.89 0.64 BSC 1.14 0.76 11.05 11.30 9.52 9.27 1.01 0.77 ORDERING INFORMATION (Order by Full Part Number) MCM 6926A WJ XX X Motorola Memory Prefix Shipping Method (R = Tape and Reel, Blank = Rails) Part Number Speed (8 = 8 ns, 10 = 10 ns, 12 = 12 ns, 15 = 15 ns) Package (WJ = 400 mil SOJ) Full Part Numbers — MCM6926AWJ8 MCM6926AWJ8R MCM6926AWJ10 MCM6926AWJ10R MCM6926AWJ12 MCM6926AWJ12R MCM6926AWJ15 MCM6926AWJ15R Motorola reserves the right to make changes without further notice to any products herein. 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