MOTOROLA Order this document by MCM6206BB/D SEMICONDUCTOR TECHNICAL DATA MCM6206BB Product Preview 32K x 8 Bit Fast Static RAM The MCM6206BB is a 262,144 bit static random access memory organized as 32,768 words of 8 bits. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. This device meets JEDEC standards for functionality and pinout, and is available in plastic small–outline J–leaded packages. • • • • • Single 5 V ± 10% Power Supply Fully Static — No Clock or Timing Strobes Necessary Fast Access Times: 12/15/20/25 ns Equal Address and Chip Enable Access Times Output Enable (G) Feature for Increased System Flexibility and to Eliminate Bus Contention Problems • Low Power Operation: 125 – 140 mA Maximum AC • Fully TTL Compatible — Three State Output PIN ASSIGNMENT BLOCK DIAGRAM A VCC A VSS A A ROW DECODER A MEMORY MATRIX A J PACKAGE 300 MIL SOJ CASE 810B–03 A 1 28 V CC A 2 27 W A 3 26 A A 4 25 A A 5 24 A A 6 23 A A 7 22 G A 8 21 A A 9 20 E A 10 19 DQ DQ 11 18 DQ DQ 12 17 DQ DQ 13 16 DQ VSS 14 15 DQ A A PIN NAMES A DQ INPUT DATA CONTROL DQ E W G .. . A . . . . . . . . . . . . . . . . . . . . Address Input DQ . . . . . . . . . . Data Input/Data Output W . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . Output Enable E . . . . . . . . . . . . . . . . . . . . . . Chip Enable VCC . . . . . . . . . . . Power Supply (+ 5 V) VSS . . . . . . . . . . . . . . . . . . . . . . . Ground COLUMN I/O COLUMN DECODER A A A A A A CIRCUIT CONTROL This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 6/4/97 Motorola, Inc. 1997 MOTOROLA FAST SRAM MCM6206BB 1 TRUTH TABLE (X = Don’t Care) E G W Mode VCC Current Output Cycle ISB1, ISB2 ICCA High–Z – High–Z – ICCA ICCA Dout High–Z Read Cycle H X X Not Selected L H H Output Disabled L L H Read L X L Write Write Cycle ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit VCC – 0.5 to + 7.0 V Vin, Vout – 0.5 to VCC + 0.5 V Output Current Iout ± 20 mA Power Dissipation PD 1.0 W Tbias – 10 to + 85 °C TA 0 to + 70 °C Power Supply Voltage Voltage Relative to VSS For Any Pin Except VCC Temperature Under Bias Ambient Temperature This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained. Storage Temperature—Plastic Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ±10%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Supply Voltage (Operating Voltage Range) VCC 4.5 5.0 5.5 V Input High Voltage VIH 2.2 — VCC + 0.3** V Input Low Voltage VIL – 0.5* — 0.8 V Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC) Ilkg(I) — ±1 µA Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC) Ilkg(O) — ±1 µA Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V Output Low Voltage (IOL = 8.0 mA) VOL — 0.4 V * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) DC CHARACTERISTICS Parameter POWER SUPPLY CURRENTS Parameter Symbol – 12 – 15 – 20 – 25 Unit AC Active Supply Current (Iout = 0 mA, VCC = Max, f = fmax) ICCA 140 135 130 125 mA AC Standby Current (E = VIH, VCC = Max, f = fmax) ISB1 40 35 35 30 mA CMOS Standby Current (VCC = Max, f = 0 MHz, E ≥ VCC – 0.2 V Vin ≤ VSS + 0.2 V, or ≥ VCC – 0.2 V) ISB2 10 10 10 10 mA CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25°C, Periodically sampled rather than 100% tested) Symbol Max Unit Address Input Capacitance Cin 6 pF Control Pin Input Capacitance (E, G, W) Cin 8 pF I/O Capacitance CI/O 8 pF Characteristic MCM6206BB 2 MOTOROLA FAST SRAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted READ CYCLE (See Note 1) – 12 Parameter – 15 – 20 – 25 Symbol Min Max Min Max Min Max Min Max Unit Notes Read Cycle Time tAVAV 12 — 15 — 20 — 25 — ns 2 Address Access Time tAVQV — 12 — 15 — 20 — 25 ns Enable Access Time tELQV — 12 — 15 — 20 — 25 ns Output Enable Access Time tGLQV — 6 — 8 — 10 — 12 ns Output Hold from Address Change tAXQX 3 — 3 — 3 — 3 — ns 4,5,6 Enable Low to Output Active tELQX 4 — 4 — 4 — 4 — ns 4,5,6 Enable High to Output High–Z tEHQZ — 7 — 8 — 9 — 10 ns 4,5,6 Output Enable Low to Output Active tGLQX 0 — 0 — 0 — 0 — ns 4,5,6 Output Enable High to Output High–Z tGHQZ — 6 — 7 — 8 — 10 ns 4,5,6 Power Up Time tELICCH 0 — 0 — 0 — 0 — ns Power Down Time tEHICCL — 12 — 15 — 20 — 25 ns 3 NOTES: 1. W is high for read cycle. 2. All timings are referenced from the last valid address to the first transitioning address. 3. Addresses valid prior to or coincident with E going low. 4. At any given voltage and temperature, tEHQZ (max) is less than tELQX (min), and tGHQZ (max) is less than tGLQX (min), both for a given device and from device to device. 5. Transition is measured ±500 mV from steady–state voltage. 6. This parameter is sampled and not 100% tested. 7. Device is continuously selected (E = VIL, G = VIL). TIMING LIMITS Z0 = 50 Ω OUTPUT 50 Ω VL = 1.5 V The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. Figure 1. AC Test Loads MOTOROLA FAST SRAM MCM6206BB 3 READ CYCLE 1 (See Note 7) tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID DATA VALID tAVQV READ CYCLE 2 (See Note 3) tAVAV A (ADDRESS) tAVQV tELQV E (CHIP ENABLE) tEHQZ tELQX G (OUTPUT ENABLE) tGHQZ tGLQV tGLQX Q (DATA OUT) ICC HIGH Z tELICCH HIGH Z DATA VALID tEHICCL VCC SUPPLY CURRENT ISB MCM6206BB 4 MOTOROLA FAST SRAM WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) – 12 Parameter Write Cycle Time – 15 – 20 – 25 Symbol Min Max Min Max Min Max Min Max Unit Notes tAVAV 12 — 15 — 20 — 25 — ns 3 Address Setup Time tAVWL 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 10 — 12 — 15 — 20 — ns Write Pulse Width tWLWH, tWLEH 10 — 12 — 15 — 20 — ns Write Pulse Width, G High tWLWH, tWLEH 10 — 10 — 12 — 15 — ns Data Valid to End of Write tDVWH 6 — 7 — 8 — 10 — ns Data Hold Time tWHDX 0 — 0 — 0 — 0 — ns Write Low to Output High–Z tWLQZ — 6 — 7 — 8 — 10 ns 5,6,7 Write High to Output Active tWHQX 2 — 2 — 2 — 2 — ns 5,6,7 Write Recovery Time tWHAX 0 — 0 — 0 — 0 — ns 4 NOTES: 1. A write occurs during the overlap of E low and W low. 2. If G goes low coincident with or after W goes low, the output will remain in a high impedance state. 3. All timings are referenced from the last valid address to the first transitioning address. 4. If G ≥ VIH, the output will remain in a high impedance state. 5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device. 6. Transition is measured ±500 mV from steady–state voltage. 7. This parameter is sampled and not 100% tested. WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) tAVAV A (ADDRESS) tWHAX tAVWH E (CHIP ENABLE) tWLWH tWLEH W (WRITE ENABLE) tAVWL tDVWH D (DATA IN) DATA VALID tWLQZ Q (DATA OUT) MOTOROLA FAST SRAM tWHDX HIGH Z tWHQX HIGH Z MCM6206BB 5 WRITE CYCLE 2 (E Controlled, See Note 1) – 12 Parameter Write Cycle Time – 15 – 20 – 25 Symbol Min Max Min Max Min Max Min Max Unit tAVAV 12 — 15 — 20 — 25 — ns Address Setup Time tAVEL 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVEH 10 — 12 — 15 — 20 — ns Enable to End of Write tELEH, tELWH 9 — 10 — 12 — 15 — ns Data Valid to End of Write tDVEH 6 — 7 — 8 — 10 — ns Data Hold Time tEHDX 0 — 0 — 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — 0 — 0 — ns Notes 3,4 NOTES: 1. A write occurs during the overlap of E low and W low. 2. All timings are referenced from the last valid address to the first transitioning address. 3. If E goes low coincident with or after W goes low, the output will remain in a high impedance state. 4. If E goes high coincident with or before W goes high, the output will remain in a high impedance state. WRITE CYCLE 2 (E Controlled, See Note 1) tAVAV A (ADDRESS) tAVEH E (CHIP ENABLE) tELEH tELWH tAVEL tEHAX tWLEH W (WRITE ENABLE) tDVEH D (DATA IN) Q (DATA OUT) MCM6206BB 6 tEHDX DATA VALID HIGH Z MOTOROLA FAST SRAM ORDERING INFORMATION (Order by Full Part Number) MCM 6206BB EJ XX X Motorola Memory Prefix Shipping Method (R = Tape and Reel, Blank = Rails) Part Number Speed (12 = 12 ns, 15 = 15 ns, 20 = 20 ns, 25 = 25 ns) Package (J = 300 mil SOJ, E = Evolutionary Pinout) Full Part Numbers — MCM6206BBEJ12 MCM6206BBEJ15 MCM6206BBEJ20 MCM6206BBEJ25 MOTOROLA FAST SRAM MCM6206BBEJ12R MCM6206BBEJ15R MCM6206BBEJ20R MCM6206BBEJ25R MCM6206BB 7 PACKAGE DIMENSIONS CASE 810B–03 300 MIL SOJ 28 LEAD NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 3. CONTROLLING DIMENSION: INCH. 4. DIM R TO BE DETERMINED AT DATUM -T-. F DETAIL Z 28 15 N 1 D 24 PL 14 0.18 (0.007) -A- M T A 0.18 (0.007) H BRK S S T B S P -B- L G M M E C 0.10 (0.004) K DETAIL Z -T- SEATING PLANE S RAD R 0.25 (0.010) S T B S DIM A B C D E F G H K L M N P R S INCHES MIN MAX 0.720 0.730 0.295 0.305 0.128 0.148 0.015 0.020 0.088 0.098 0.026 0.032 0.050 BSC 0.020 — 0.035 0.045 0.025 BSC 0° 10° 0.030 0.045 0.330 0.340 0.260 0.270 0.030 0.040 MILLIMETERS MIN MAX 18.29 18.54 7.74 7.50 3.75 3.26 0.50 0.39 2.48 2.24 0.81 0.67 1.27 BSC 0.50 — 1.14 0.89 0.64 BSC 0° 10° 1.14 0.76 8.64 8.38 6.86 6.60 1.01 0.77 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488 Mfax: [email protected] – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, – US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 INTERNET: http://motorola.com/sps MCM6206BB 8 ◊ MOTOROLA MCM6206BB/D FAST SRAM