MOTOROLA Order this document by MCM6343/D SEMICONDUCTOR TECHNICAL DATA MCM6343 Product Preview 256K x 16 Bit 3.3 V Asynchronous Fast Static RAM The MCM6343 is a 4,194,304–bit static random access memory organized as 262,144 words of 16 bits. Static design eliminates the need for external clocks or timing strobes. The MCM6343 is equipped with chip enable (E), write enable (W), and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems. Separate byte enable controls (LB and UB) allow individual bytes to be written and read. LB controls the lower bits DQ0 to DQ7, while UB controls the upper bits DQ8 to DQ15. The MCM6343 is available in a 400 mil, 44–lead small–outline SOJ package and a 44–lead TSOP Type II package. • • • • • • • • Single 3.3 V ± 0.3 V Power Supply Fast Access Time: 12/15 ns Equal Address and Chip Enable Access Time All Inputs and Outputs are TTL Compatible Data Byte Control Fully Static Operation Power Operation: 250/240/230 mA Maximum, Active AC Commercial and Standard Industrial Temperature Option: – 40 to + 85°C BLOCK DIAGRAM OUTPUT ENABLE BUFFER G 18 E W ADDRESS BUFFERS 9 1 44 A 2 43 A A 3 42 A A 4 41 G A 5 40 UB E DQ0 6 7 39 38 LB DQ15 DQ1 8 37 DQ14 DQ2 9 36 DQ13 HIGH BYTE OUTPUT ENABLE DQ3 10 35 DQ12 LOW BYTE OUTPUT ENABLE VDD VSS 11 34 12 33 VSS VDD DQ4 13 32 DQ11 DQ5 14 31 DQ10 DQ6 15 30 DQ9 DQ7 W 16 17 29 28 DQ8 NC A 18 27 A A 19 26 A A 20 25 A A 21 24 A A 22 23 A HIGH BYTE OUTPUT BUFFER ROW COLUMN DECODER DECODER 8 CHIP ENABLE BUFFER 256K x 16 BIT MEMORY ARRAY 16 UB BYTE ENABLE BUFFER 8 HIGH BYTE WRITE DRIVER 8 SENSE AMPS LOW BYTE OUTPUT BUFFER 8 8 LB PIN ASSIGNMENT A 8 WRITE ENABLE BUFFER TS PACKAGE TSOP TYPE II CASE 924A–02 A 9 A YJ PACKAGE 400 MIL SOJ CASE 919–01 HIGH BYTE WRITE ENABLE LOW BYTE WRITE ENABLE LOW BYTE WRITE DRIVER 8 PIN NAMES 8 A0 – A17 . . . . . . . . . . . . . . . . . Address Input E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable W . . . . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . . . . Output Enable UB . . . . . . . . . . . . . . . . . . . . . . . . Upper Byte LB . . . . . . . . . . . . . . . . . . . . . . . . . Lower Byte DQ0 – DQ15 . . . . . . . . . . Data Input/Output VDD . . . . . . . . . . . . . . + 3.3 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . . . . . No Connection This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. REV 2 2/10/98 Motorola, Inc. 1998 MOTOROLA FAST SRAM MCM6343 1 TRUTH TABLE (X = Don’t Care) E G W LB UB Mode VDD Current DQ0 – DQ7 DQ8 – DQ15 H X X X X Not Selected ISB1, ISB2 High–Z High–Z L H H X X Output Disabled IDDA High–Z High–Z L X X H H Output Disabled IDDA High–Z High–Z L L H L H Low Byte Read IDDA Dout High–Z L L H H L High Byte Read IDDA High–Z Dout L L H L L Word Read IDDA Dout Dout L X L L H Low Byte Write IDDA Din High–Z L X L H L High Byte Write IDDA High–Z Din L X L L L Word Write IDDA Din Din ABSOLUTE MAXIMUM RATINGS (See Notes) Rating Symbol Value Unit VDD – 0.5 to + 4.6 V Voltage on Any Pin Vin – 0.5 to VDD + 0.5 V Output Current per Pin Iout ± 20 mA Package Power Dissipation PD TBD W Supply Voltage Temperature Under Bias Commercial Industrial Tbias – 10 to + 85 – 45 to + 90 °C Operating Temperature Commercial Industrial TA 0 to + 70 – 45 to + 85 °C Tstg – 55 to + 150 °C Storage Temperature This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high–impedance circuits. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained. NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. All voltages are referenced to VSS. 3. Power dissipation capability will be dependent upon package characteristics and use environment. MCM6343 2 MOTOROLA FAST SRAM DC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V ± 0.3 V, TA = 0 to 70°C, Unless Otherwise Noted) (TA = – 40 to + 85°C for Industrial Temperature Offering) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Power Supply Voltage VDD 3.0 3.3 3.6 V Input High Voltage VIH 2.2 — VDD + 0.3** V Input Low Voltage VIL – 0.5* — 0.8 V Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VDD) Ilkg(I) — ± 1.0 µA Output Leakage Current (E = VIH, Vout = 0 to VDD) Ilkg(O) — ± 1.0 µA * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA. ** VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA. DC CHARACTERISTICS Parameter Output Low Voltage (IOL = + 4.0 mA) (IOL = + 100 µA) VOL — 0.4 VSS + 0.2 V Output High Voltage (IOH = – 4.0 mA) (IOH = – 100 µA) VOH 2.4 VDD – 0.2 — V Symbol 0 to 70°C – 40 to + 85°C Unit POWER SUPPLY CURRENTS Parameter AC Active Supply Current (Iout = 0 mA, VCC = max) MCM6343–12: tAVAV = 12 ns MCM6343–15: tAVAV = 15 ns ICC 240 230 240 mA AC Standby Current (VCC = max, E = VIH, No other restrictions on other inputs) MCM6343–12: tAVAV = 12 ns MCM6343–15: tAVAV = 15 ns ISB1 50 45 55 50 mA ISB2 5 5 mA Symbol Typ Max Unit Cin — 6 pF Control Input Capacitance Cin — 6 pF Input/Output Capacitance CI/O — 8 pF CMOS Standby Current (E ≥ VCC – 0.2 V, Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V) (VCC = max, f = 0 MHz) CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Parameter Address Input Capacitance MOTOROLA FAST SRAM MCM6343 3 AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 3.3 V ± 0.3 V, TA = 0 to + 70°C, Unless Otherwise Noted) (TA = – 40 to + 85°C for Industrial Temperature Offering) Logic Input Timing Measurement Reference Level . . . . . . . . 1.50 V Logic Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.50 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 READ CYCLE TIMING (See Notes 1, 2, and 3) MCM6343–12 P Parameter MCM6343–15 S b l Symbol Min Max Min Max U i Unit N Notes Read Cycle Time tAVAV 12 — 15 — ns 4 Address Access Time tAVQV — 12 — 15 ns Enable Access Time tELQV — 12 — 15 ns Output Enable Access Time tGLQV — 6 — 7 ns Output Hold from Address Change tAXQX 3 — 3 — ns Enable Low to Output Active tELQX 3 — 3 — ns 6, 7, 8 Output Enable Low to Output Active tGLQX 0 — 0 — ns 6, 7, 8 Enable High to Output High–Z tEHQZ 0 6 0 7 ns 6, 7, 8 Output Enable High to Output High–Z tGHQZ 0 6 0 7 ns 6, 7, 8 Byte Enable Access Time tBLQV — 6 — 7 ns Byte Enable Low to Output Active tBLQX 0 — 0 — ns 6, 7, 8 Byte High to Output High–Z tBHQZ 0 6 0 7 ns 6, 7, 8 5 NOTES: 1. W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. Device is continuously selected (E ≤ VIL, G ≤ VIL). 4. All read cycle timings are referenced from the last valid address to the first transitioning address. 5. Addresses valid prior to or coincident with E going low. 6. At any given voltage and temperature, tEHQZ max tELQX min, and tGHQZ max tGLQX min, both for a given device and from device to device. 7. This parameter is sampled and not 100% tested. 8. Transition is measured ± 200 mV from steady–state voltage. t t TIMING LIMITS RL = 50 Ω OUTPUT Z0 = 50 Ω VL = 1.5 V The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. Figure 1. AC Test Load MCM6343 4 MOTOROLA FAST SRAM READ CYCLE 1 (See Note 8) tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID DATA VALID tAVQV READ CYCLE 2 (See Note 4) tAVAV A (ADDRESS) tAVQV tELQV E (CHIP ENABLE) tEHQZ tELQX G (OUTPUT ENABLE) tGHQZ tGLQV tGLQX LB, UB (BYTE ENABLE) tBLQV tBHQZ tBLQX Q (DATA OUT) MOTOROLA FAST SRAM DATA VALID MCM6343 5 WRITE CYCLE 1 (W Controlled; See Notes 1, 2, and 3) MCM6343–12 P Parameter MCM6343–15 S b l Symbol Min Max Min Max U i Unit N Notes Write Cycle Time tAVAV 12 — 15 — ns 4 Address Setup Time tAVWL 0 — 0 — ns Address Valid to End of Write tAVWH 10 — 12 — ns Address Valid to End of Write (G High) tAVWH 9 — 10 — ns Write Pulse Width tWLWH tWLEH 10 — 12 — ns Write Pulse Width (G High) tWLWH tWLEH 9 — 10 — ns Data Valid to End of Write tDVWH 6 — 7 — ns Data Hold Time tWHDX 0 — 0 — ns Write Low to Data High–Z tWLQZ 0 6 0 7 ns 5, 6, 7 Write High to Output Active tWHQX 3 — 3 — ns 5, 6, 7 Write Recovery Time tWHAX 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state. 4. All write cycle timings are referenced from the last valid address to the first transitioning address. 5. This parameter is sampled and not 100% tested. 6. Transition is measured ± 200 mV from steady–state voltage. 7. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device. WRITE CYCLE 1 (W Controlled; See Notes 1, 2, and 3) tAVAV A (ADDRESS) tWHAX tAVWH E (CHIP ENABLE) tWLEH tWLWH W (WRITE ENABLE) tWHDX tAVWL LB, UB (BYTE ENABLE) tDVWH D (DATA IN) DATA VALID tWLQZ Q (DATA OUT) HIGH–Z HIGH–Z tWHQX MCM6343 6 MOTOROLA FAST SRAM WRITE CYCLE 2 (E Controlled; See Notes 1, 2, and 3) MCM6343–12 P Parameter MCM6343–15 S b l Symbol Min Max Min Max U i Unit N Notes Write Cycle Time tAVAV 12 — 15 — ns 4 Address Setup Time tAVEL 0 — 0 — ns Address Valid to End of Write tAVEH 10 — 12 — ns Address Valid to End of Write (G High) tAVEH 9 — 10 — ns Enable to End of Write tELEH, tELWH 10 — 12 — ns 5, 6 Enable to End of Write (G High) tELEH, tELWH 9 — 10 — ns 5, 6 Data Valid to End of Write tDVEH 6 — 7 — ns Data Hold Time tEHDX 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state. 4. All write cycle timing is referenced from the last valid address to the first transitioning address. 5. If E goes low coincident with or after W goes low, the output will remain in a high–impedance condition. 6. If E goes high coincident with or before W goes high, the output will remain in a high–impedance condition. WRITE CYCLE 2 (E Controlled; See Notes 1, 2, and 3) tAVAV A (ADDRESS) tAVEH tEHAX tELEH E (CHIP ENABLE) tAVEL tELWH W (WRITE ENABLE) LB, UB (BYTE ENABLE) tDVEH D (DATA IN) Q (DATA OUT) MOTOROLA FAST SRAM tEHDX DATA VALID HIGH–Z MCM6343 7 WRITE CYCLE 3 (E Controlled; See Notes 1, 2, and 3) MCM6343–12 P Parameter MCM6343–15 S b l Symbol Min Max Min Max U i Unit N Notes Write Cycle Time tAVAV 12 — 15 — ns 4 Address Setup Time tAVBL 0 — 0 — ns Address Valid to End of Write tAVBH 10 — 12 — ns Address Valid to End of Write (G High) tAVBH 9 — 10 — ns Byte Pulse Width tBLWH tBLEH 10 — 12 — ns Byte Pulse Width (G High) tBLWH tBLEH 9 — 10 — ns Data Valid to End of Write tDVBH 6 — 7 — ns Data Hold Time tBHDX 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state. 4. All write cycle timings are referenced from the last valid address to the first transitioning address. WRITE CYCLE 3 (E Controlled; See Notes 1, 2, and 3) tAVAV A (ADDRESS) tAVBH E (CHIP ENABLE) tAVBL tBLEH tBLWH LB, UB (BYTE ENABLE) tBHDX W (WRITE ENABLE) tDVBH D (DATA IN) Q (DATA OUT) MCM6343 8 DATA VALID HIGH–Z HIGH–Z MOTOROLA FAST SRAM ORDERING INFORMATION (Order by Full Part Number) XCM 6943 XX XX X Motorola Memory Prefix Shipping Method (R = Tape and Reel, Blank = Rails) Part Number Speed (12 = 12 ns, 15 = 15 ns) Package (YJ = 400 mil SOJ, TS = TSOP Type II) Full Commercial Part Numbers — MCM6343YJ12 MCM6343YJ15 Full Industrial Part Numbers — SCM6343YJ12A SCM6343YJ15A MCM6343YJ12R MCM6343YJ15R MCM6343TS12 MCM6343TS15 SCM6343YJ12AR SCM6343YJ15AR SCM6343TS12A* SCM6343TS15A* * Not available in Tape and Reel. PACKAGE DIMENSIONS YJ PACKAGE 44–LEAD 400 MIL SOJ CASE 919–01 44 23 E1 1 22 B A D 44X b1 42X 0.007 e L C A B A A3 SEATING PLANE A e /2 C 44X 0.004 C b 0.007 M C A B E 0.007 A M C A B A2 44X R E2 /2 A1 0.015 B 22 ZONES 2X MOTOROLA FAST SRAM NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, TIE BAR BURRS AND GATE BURRS. MOLD FLASH, TIE BAR BURRS AND GATE BURRS SHALL NOT EXCEED 0.006 PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010 PER SIDE. 4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS D AND E1 AND, HENCE, DATUMS A AND B, ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 5. DIMENSION b1 DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE SHOULDER WIDTH TO EXCEED b1 MAX BY MORE THAN 0.005. THE DAMBAR INTRUSION(S) SHALL NOT REDUCE THE SHOULDER WIDTH TO LESS THAN 0.001 BELOW b1 MIN. R1 DIM A A1 A2 A3 b b1 D E E1 E2 e R1 INCHES MIN MAX 0.128 0.148 0.025 ––– 0.082 ––– 0.035 0.045 0.015 0.020 0.026 0.032 1.120 1.130 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC 0.030 0.040 E2 VIEW A–A MCM6343 9 TS PACKAGE 44–LEAD TSOP TYPE II CASE 924A–02 VIEW A B 44 23 E1 A A 1 22 A2 A D A 22X 0.2 44X 0.004 (0.1) C SEATING PLANE 4X e /2 42X ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ c A1 b 0.2 M C e C B L SECTION A–A q VIEW A ROTATED 90 _ CLOCKWISE 40 PLACES M E C B NOTES: 1. DIMENSIONINS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETER. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.15 PER SIDE. 4. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.58. DIM A A1 A2 b c D e E E1 L q MILLIMETERS MIN MAX ––– 1.20 0.05 0.15 0.95 1.05 0.30 0.45 0.12 0.21 18.28 18.54 0.80 BSC 11.56 11.96 10.03 10.29 0.40 0.60 0_ 5_ Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. 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Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488 Mfax : [email protected] – TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, Motorola Fax Back System – US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 – http://sps.motorola.com /mfax / HOME PAGE : http://motorola.com/sps / CUSTOMER FOCUS CENTER: 1-800-521-6274 MCM6343 10 ◊ MCM6343/D MOTOROLA FAST SRAM