MOTOROLA Order this document by MCM6229BB/D SEMICONDUCTOR TECHNICAL DATA MCM6229BB Product Preview 256K x 4 Bit Static Random Access Memory XJ PACKAGE 400 MIL SOJ CASE 810–03 The MCM6229BB is a 1,048,576 bit static random access memory organized as 262,144 words of 4 bits. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6229BB is equipped with both chip enable (E) and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems. The MCM6229BB is available in 300 mil and 400 mil, 28 lead surface–mount SOJ packages. • • • • • • Single 5 V ± 10% Power Supply Fast Access Times: 15/17/20/25/35 ns Equal Address and Chip Enable Access Times All Inputs and Outputs are TTL Compatible and LVTTL Compatible Three State Outputs Low Power Operation: 155/150/135/130/110 mA Maximum, Active AC BLOCK DIAGRAM A EJ PACKAGE 300 MIL SOJ CASE 810B–03 PIN ASSIGNMENTS A 1 28 VCC A 2 27 A A 3 26 A A 4 25 A A 5 24 A A 6 23 A 22 A 21 A A 7 A A A A 9 20 NC* A A MEMORY MATRIX 512 ROWS x 2048 COLUMNS ROW DECODER A A 8 A 10 19 DQ A 11 18 DQ E 12 17 DQ G 13 16 DQ VSS 14 15 W A A DQ PIN NAMES COLUMN I/O INPUT DATA CONTROL COLUMN DECODER DQ A E W G A A A A A A A A A . . . . . . . . . . . . . . . . . . . . Address Inputs W . . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . Output Enable E . . . . . . . . . . . . . . . . . . . . . . Chip Enable DQ . . . . . . . . . . . . . Data Inputs/Outputs VCC . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . Ground NC* . . . . . . . . . . . . . . . . . No Connection *If not used for no connect, then do not exceed voltages of – 0.5 to VCC + 0.5 V. This pin is used for manufacturing diagnostics. This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. 11/7/96 Motorola, Inc. 1995 MOTOROLA FAST SRAM MCM6229BB 1 TRUTH TABLE E G W Mode I/O Pin Cycle Current H X X Not Selected High–Z — ISB1, ISB2 L H H Output Disabled High–Z — ICCA L L H Read Dout Read ICCA L X L Write Din Write ICCA H = High, L = Low, X = Don’t Care ABSOLUTE MAXIMUM RATINGS (See Note) Symbol Value Unit VCC – 0.5 to 7.0 V Vin, Vout – 0.5 to VCC + 0.5 V Output Current (per I/O) Iout ± 20 mA Power Dissipation PD 1.0 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C Rating Power Supply Voltage Relative to VSS Voltage Relative to VSS for Any Pin Except VCC Storage Temperature Tstg – 55 to + 150 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high–impedance circuits. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Unit Supply Voltage (Operating Voltage Range) VCC 4.5 5.5 V Input High Voltage VIH 2.2 VCC + 0.3** V Input Low Voltage VIL – 0.5* 0.8 V Symbol Min Max Unit Ilkg(I) — ±1 µA * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns). ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns). DC CHARACTERISTICS AND SUPPLY CURRENTS Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Ilkg(O) — ±1 µA AC Active Supply Current (Iout = 0 mA, all inputs = VIL or VIH, VIL = 0, VIH ≥ 3 V, cycle time ≥ tAVAV min, VCC = max) MCM6229BB–15: tAVAV = 15 ns MCM6229BB–17: tAVAV = 17 ns MCM6229BB–20: tAVAV = 20 ns MCM6229BB–25: tAVAV = 25 ns MCM6229BB–35: tAVAV = 35 ns ICCA — — — — — 155 150 135 130 110 mA AC Standby Current (VCC = max, E = VIH, f = fmax) MCM6229BB–15: tAVAV = 15 ns MCM6229BB–17: tAVAV = 17 ns MCM6229BB–20: tAVAV = 20 ns MCM6229BB–25: tAVAV = 25 ns MCM6229BB–35: tAVAV = 35 ns ISB1 — — — — — 45 40 35 30 25 mA CMOS Standby Current (E ≥ VCC – 0.2 V, Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V, VCC = max, f = 0 MHz) ISB2 — 5 mA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V Output Leakage Current (E = VIH, Vout = 0 to VCC) MCM6229BB 2 MOTOROLA FAST SRAM CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Symbol Typ Max Unit All Inputs Except Clocks and DQs E, G, and W Cin Cck 4 5 6 8 pF DQ CI/O 5 8 pF Characteristic Input Capacitance I/O Capacitance AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1a READ CYCLE TIMING (See Notes 1, 2, and 3) Parameter 6229BB–15 6229BB–17 6229BB–20 6229BB–25 6229BB–35 Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes Read Cycle Time tAVAV 15 — 17 — 20 — 25 — 35 — ns 3 Address Access Time tAVQV — 15 — 17 — 20 — 25 — 35 ns Enable Access Time tELQV — 15 — 17 — 20 — 25 — 35 ns Output Enable Access Time tGLQV — 6 — 7 — 7 — 8 — 8 ns Output Hold from Address Change tAXQX 3 — 3 — 3 — 3 — 3 — ns Enable Low to Output Active tELQX 5 — 5 — 5 — 5 — 5 — ns 5, 6, 7 Output Enable Low to Output Active tGLQX 0 — 0 — 0 — 0 — 0 — ns 5, 6, 7 Enable High to Output High–Z tEHQZ 0 6 0 7 0 7 0 8 0 8 ns 5, 6, 7 Output Enable High to Output High–Z tGHQZ 0 6 0 7 0 7 0 8 0 8 ns 5, 6, 7 4 NOTES: 1. W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. Addresses valid prior to or coincident with E going low. 5. At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given device and from device to device. 6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b. 7. This parameter is sampled and not 100% tested. 8. Device is continuously selected (E ≤ VIL, G ≤ VIL). TIMING LIMITS +5 V 480 Ω OUTPUT Z0 = 50 Ω RL = 50 Ω OUTPUT 255 Ω 5 pF VL = 1.5 V (a) (b) The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. Figure 1. AC Test Loads MOTOROLA FAST SRAM MCM6229BB 3 READ CYCLE 1 (See Notes 1, 2, 3, and 9) tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID DATA VALID tAVQV READ CYCLE 2 (See Notes 3 and 5) tAVAV A (ADDRESS) tELQV E (CHIP ENABLE) tELQX tEHQZ G (OUTPUT ENABLE) tGHQZ tGLQV tGLQX Q (DATA OUT) HIGH–Z DATA VALID tAVQV tELICCH tEHICCL ICC SUPPLY CURRENT ISB MCM6229BB 4 MOTOROLA FAST SRAM WRITE CYCLE 1 (W Controlled, See Notes 1, 2, 3, and 4) Parameter Write Cycle Time 6229BB–15 6229BB–17 6229BB–20 6229BB–25 6229BB–35 Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes tAVAV 15 — 17 — 20 — 25 — 35 — ns 4 Address Setup Time tAVWL 0 — 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 12 — 14 — 15 — 17 — 20 — ns Write Pulse Width tWLWH, tWLEH 12 — 14 — 15 — 17 — 20 — ns Data Valid to End of Write tDVWH 7 — 8 — 9 — 10 — 11 — ns Data Hold TIme tWHDX 0 — 0 — 0 — 0 — 0 — ns Write Low to Data High–Z tWLQZ — 6 — 7 — 7 — 8 — 8 ns 5, 6, 7 Write High to Output Active tWHQX 5 — 5 — 5 — 5 — 5 — ns 5, 6, 7 Write Recovery Time tWHAX 0 — 0 — 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state. 4. All timings are referenced from the last valid address to the first transitioning address. 5. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b. 6. This parameter is sampled and not 100% tested. 7. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device. WRITE CYCLE 1 (W Controlled See Notes 1, 2, 3, and 4) tAVAV A (ADDRESS) tWHAX tAVWH E (CHIP ENABLE) tWLWH tWLEH W (WRITE ENABLE) tAVWL tDVWH D (DATA IN) DATA VALID tWLQZ Q (DATA OUT) tWHDX HIGH–Z MOTOROLA FAST SRAM tWHQX HIGH–Z MCM6229BB 5 WRITE CYCLE 2 (E Controlled, See Notes 1, 2, and 3) Parameter Write Cycle Time 6229BB–15 6229BB–17 6229BB–20 6229BB–25 6229BB–35 Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes tAVAV 15 — 17 — 20 — 25 — 35 — ns 4 Address Setup Time tAVEL 0 — 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVEH 12 — 14 — 15 — 17 — 20 — ns Enable to End of Write tELEH, tELWH 12 — 14 — 15 — 17 — 20 — ns Write Pulse Width tWLEH 12 — 14 — 15 — 17 — 20 — ns Data Valid to End of Write tDVEH 7 — 8 — 9 — 10 — 11 — ns Data Hold Time tEHDX 0 — 0 — 0 — 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — 0 — 0 — 0 — ns 5, 6 NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state. 4. All timings are referenced from the last valid address to the first transitioning address. 5. If E goes low coincident with or after W goes low, the output will remain in a high–impedance state. 6. If E goes high coincident with or before W goes high, the output will remain in a high–impedance state. WRITE CYCLE 2 (E Controlled See Notes 1, 2, 3, and 4) tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL tELWH tEHAX tWLEH W (WRITE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX HIGH–Z Q (DATA OUT) ORDERING INFORMATION (Order by Full Part Number) MCM 6229BB XX XX XX Motorola Memory Prefix Shipping Method (R2 = Tape and Reel, Blank = Rails) Part Number Speed (15 = 15 ns, 17 = 17 ns, 20 = 20 ns, 25 = 25 ns, 35 = 35 ns) Package (XJ = 400 mil SOJ, EJ = 300 mil SOJ) Full Part Numbers — MCM6229BBXJ15 MCM6229BBXJ17 MCM6229BBXJ20 MCM6229BBXJ25 MCM6229BBXJ35 MCM6229BB 6 MCM6229BBXJ15R2 MCM6229BBXJ17R2 MCM6229BBXJ20R2 MCM6229BBXJ25R2 MCM6229BBXJ35R2 MCM6229BBEJ15 MCM6229BBEJ17 MCM6229BBEJ20 MCM6229BBEJ25 MCM6229BBEJ35 MCM6229BBEJ15R2 MCM6229BBEJ17R2 MCM6229BBEJ20R2 MCM6229BBEJ25R2 MCM6229BBEJ35R2 MOTOROLA FAST SRAM PACKAGE DIMENSIONS 28 LEAD 400 MIL SOJ CASE 810–03 F 28 DETAIL Z N 15 D 28 PL 0.18 (0.007) 1 M T A S 14 H BRK 0.18 (0.007) –A– S T B S P L G –B– M M C E 0.10 (0.004) K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION R TO BE DETERMINED AT DATUM –T–. DETAIL Z –T– SEATING PLANE R 0.25 (0.010) MOTOROLA FAST SRAM S S T B S RADIUS DIM A B C D E F G H K L M N P R S INCHES MIN MAX 0.720 0.730 0.395 0.405 0.128 0.148 0.015 0.020 0.088 0.098 0.026 0.032 0.050 BSC ––– 0.020 0.035 0.045 0.025 BSC 0_ 5_ 0.030 0.045 0.435 0.445 0.360 0.380 0.030 0.040 MILLIMETERS MIN MAX 18.29 18.54 10.04 10.28 3.26 3.75 0.39 0.50 2.24 2.48 0.67 0.81 1.27 BSC ––– 0.50 0.89 1.14 0.64 BSC 0_ 5_ 0.76 1.14 11.05 11.30 9.15 9.65 0.77 1.01 MCM6229BB 7 28 LEAD 300 MIL SOJ CASE 810B–03 F 28 15 1 D 24 PL 0.18 (0.007) 14 0.18 (0.007) P –B– H BRK –A– L G M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION R TO BE DETERMINED AT DATUM –T–. DETAIL Z N S M T A T B S S M E C 0.10 (0.004) K DETAIL Z –T– SEATING PLANE S RADIUS R 0.25 (0.010) S T B S DIM A B C D E F G H K L M N P R S INCHES MIN MAX 0.720 0.730 0.295 0.305 0.128 0.148 0.015 0.020 0.088 0.098 0.026 0.032 0.050 BSC ––– 0.020 0.035 0.045 0.025 BSC 0_ 10 _ 0.030 0.045 0.330 0.340 0.260 0.270 0.030 0.040 MILLIMETERS MIN MAX 18.29 18.54 7.50 7.74 3.26 3.75 0.39 0.50 2.24 2.48 0.67 0.81 1.27 BSC ––– 0.50 0.89 1.14 0.64 BSC 0_ 10 _ 0.76 1.14 8.38 8.64 6.60 6.86 0.77 1.01 Motorola reserves the right to make changes without further notice to any products herein. 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