SN54/74LS122 SN54/74LS123 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS122 has an internal timing resistor that allows the circuits to be used with only an external capacitor. Once triggered, the basic pulse width may be extended by retriggering the gated low-level-active (A) or high-level-active (B) inputs, or be reduced by use of the overriding clear. • • • • • RETRIGGERABLE MONOSTABLE MULTIVIBRATORS LOW POWER SCHOTTKY Overriding Clear Terminates Output Pulse Compensated for VCC and Temperature Variations DC Triggered from Active-High or Active-Low Gated Logic Inputs Retriggerable for Very Long Output Pulses, up to 100% Duty Cycle Internal Timing Resistors on LS122 J SUFFIX CERAMIC CASE 620-09 16 1 SN54 / 74LS123 (TOP VIEW) (SEE NOTES 1 THRU 4) ! N SUFFIX PLASTIC CASE 648-08 16 1 16 1 D SUFFIX SOIC CASE 751B-03 J SUFFIX CERAMIC CASE 632-08 14 SN54 / 74LS122 (TOP VIEW) (SEE NOTES 1 THRU 4) 1 14 N SUFFIX PLASTIC CASE 646-06 1 14 1 D SUFFIX SOIC CASE 751A-02 " NOTES: 1. An external timing capacitor may be connected between Cext and Rext/Cext (positive). 2. To use the internal timing resistor of the LS122, connect Rint to VCC. 3. For improved pulse width accuracy connect an external resistor between Rext/Cext and VCC with Rint open-circuited. 4. To obtain variable pulse widths, connect an external variable resistance between Rint/Cext and VCC. FAST AND LS TTL DATA 5-197 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC SN54/74LS122 • SN54/74LS123 LS122 FUNCTIONAL TABLE INPUTS LS123 FUNCTIONAL TABLE OUTPUTS INPUTS OUTPUTS CLEAR A1 A2 B1 B2 Q Q CLEAR A B Q Q L X X X H H H H H H H ↑ ↑ X H X X L L X X H ↓ ↓ L X X H X X X X L L ↓ ↓ H X L X X L X ↑ H ↑ H H H H H H X X X L H ↑ H ↑ H H H H H L L L L H H H H L X X H H ↑ X H X L ↓ L X X L ↑ H H L L L H H H TYPICAL APPLICATION DATA The output pulse tW is a function of the external components, Cext and Rext or Cext and Rint on the LS122. For values of Cext ≥ 1000 pF, the output pulse at VCC = 5.0 V and VRC = 5.0 V (see Figures 1, 2, and 3) is given by tW = K Rext Cext where K is nominally 0.45 If Cext is on pF and Rext is in kΩ then tW is in nanoseconds. The Cext terminal of the LS122 and LS123 is an internal connection to ground, however for the best system performance Cext should be hard-wired to ground. Care should be taken to keep Rext and Cext as close to the monostable as possible with a minimum amount of inductance between the Rext/Cext junction and the Rext/Cext pin. Good groundplane and adequate bypassing should be designed into the system for optimum performance to insure that no false triggering occurs. It should be noted that the Cext pin is internally connected to ground on the LS122 and LS123, but not on the LS221. Therefore, if Cext is hard-wired externally to ground, substitution of a LS221 onto a LS123 socket will cause the LS221 to become non-functional. The switching diode is not needed for electrolytic capacitance application and should not be used on the LS122 and LS123. To find the value of K for Cext ≥ 1000 pF, refer to Figure 4. Variations on VCC or VRC can cause the value of K to change, as can the temperature of the LS123, LS122. Figures 5 and 6 show the behavior of the circuit shown in Figures 1 and 2 if separate power supplies are used for VCC and VRC. If VCC is tied to VRC, Figure 7 shows how K will vary with VCC and temperature. Remember, the changes in Rext and Cext with temperature are not calculated and included in the graph. As long as Cext ≥ 1000 pF and 5K ≤ Rext ≤ 260K (SN74LS122 / 123) or 5K ≤ Rext ≤ 160 K (SN54LS122 / 123), the change in K with respect to Rext is negligible. If Cext ≤ 1000 pF the graph shown on Figure 8 can be used to determine the output pulse width. Figure 9 shows how K will change for Cext ≤ 1000 pF if VCC and VRC are connected to the same power supply. The pulse width tW in nanoseconds is approximated by tW = 6 + 0.05 Cext (pF) + 0.45 Rext (kΩ) Cext + 11.6 Rext In order to trim the output pulse width, it is necessary to include a variable resistor between VCC and the Rext/Cext pin or between VCC and the Rext pin of the LS122. Figure 10, 11, and 12 show how this can be done. Rext remote should be kept as close to the monostable as possible. Retriggering of the part, as shown in Figure 3, must not occur before Cext is discharged or the retrigger pulse will not have any effect. The discharge time of Cext in nanoseconds is guaranteed to be less than 0.22 Cext (pF) and is typically 0.05 Cext (pF). For the smallest possible deviation in output pulse widths from various devices, it is suggested that Cext be kept ≥ 1000 pF. FAST AND LS TTL DATA 5-198 SN54/74LS122 • SN54/74LS123 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 74 4.0 8.0 mA Rext External Timing Resistance 54 74 180 260 kΩ Cext External Capacitance 54, 74 Rext / Cext Wiring Capacitance at Rext / Cext Terminal 54, 74 5.0 5.0 No Restriction WAVEFORMS EXTENDING PULSE WIDTH OVERRIDING THE OUTPUT PULSE FAST AND LS TTL DATA 5-199 50 pF SN54/74LS122 • SN54/74LS123 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current Typ Max 2.0 54 0.7 74 0.8 – 0.65 – 1.5 Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA 54 2.5 3.5 V 74 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA 20 µA VCC = MAX, VIN = 2.7 V – 20 0.1 mA VCC = MAX, VIN = 7.0 V – 0.4 mA VCC = MAX, VIN = 0.4 V –100 mA VCC = MAX mA VCC = MAX LS122 11 LS123 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ Max Unit tPLH tPHL Propagation Delay, A to Q Propagation Delay, A to Q 23 33 32 45 tPLH tPHL Propagation Delay, B to Q Propagation Delay, B to Q 23 44 34 56 tPLH tPHL Propagation Delay, Clear to Q Propagation Delay, Clear to Q 28 45 20 27 tW min A or B to Q 116 200 ns tWQ A to B to Q 4.5 5.0 µs Max Unit Test Conditions ns Cext = 0 CL = 15 pF ns Rext = 5.0 kΩ RL = 2.0 kΩ ns 4.0 Cext = 1000 pF, Rext = 10 kΩ, CL = 15 pF, RL = 2.0 kΩ AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol tW Parameter Pulse Width Min Typ 40 ns FAST AND LS TTL DATA 5-200 Test Conditions SN54/74LS122 • SN54/74LS123 &$ &$ &$ &$ µ &$ &$ &$ #%$ &$ &$ 1/2 LS123 LS122 !" Ω Figure 1 #%$ $ Figure 3 µ Ω Figure 2 !" &$ !" ≤ &$ ≤ Figure 4 FAST AND LS TTL DATA 5-201 µ &$ #%$ SN54/74LS122 • SN54/74LS123 " " " " ° K K ° ° ° ° ° ° K ( %+* ( %+* ( %+* ° ° ° ° ° ° ° ° VCC VRC VCC = VRC Figure 5. K versus VCC Figure 6. K versus VRC Figure 7. K versus VCC and VRC & %+* & %+* Ω Ω * # ! ! !# ') Ω Ω &Ω %+* &Ω %+* &Ω %+* & %+* & %+* $ %+* ( Figure 8 FAST AND LS TTL DATA 5-202 SN54/74LS122 • SN54/74LS123 ° ° ° ° K ° Figure 9 Figure 10. LS123 Remote Trimming Circuit FAST AND LS TTL DATA 5-203 SN54/74LS122 • SN54/74LS123 Figure 11. LS122 Remote Trimming Circuit Without Rext Figure 12. LS122 Remote Trimming Circuit with Rint FAST AND LS TTL DATA 5-204 Case 751B-03 D Suffix 16-Pin Plastic SO-16 -A- "! ! " " ! " # 1 %# ) ! !" $ !" 8 C -T- D M K " ! #! J F ! Case 648-08 N Suffix 16-Pin Plastic R X 45° G " ! ) #! P ! " " 9 -B- ! 16 & ! ! ° ° ° ° ( ( ( ( "! ! " " ! ! ' " " ! ' ! " # & -A- 16 9 1 8 ! ! $ ! B # ) " ! " # ) !" $ !" ) F L C S -T- K H G M J D " Case 620-09 J Suffix 16-Pin Ceramic Dual In-Line -A- ! ! ! ! ° ° ° ° "! ! " 16 " ) " L K M N J G D " $ " $ ! " " ! ! FAST AND LS TTL DATA 5-205 & # ) !" $ !" ) -T $ " " C F & 8 E ! ! ! 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Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. ◊ FAST AND LS TTL DATA 5-206