DM74LS221 Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs Y General Description Y The DM74LS221 is a dual monostable multivibrator with Schmitt-trigger input. Each device has three inputs permitting the choice of either leading-edge or trailing-edge triggering. Pin (A) is an active-low trigger transition input and pin (B) is an active-high transition Schmitt-trigger input that allows jitter free triggering for inputs with transition rates as slow as 1 volt/second. This provides the input with excellent noise immunity. Additionally an internal latching circuit at the input stage also provides a high immunity to VCC noise. The clear (CLR) input can terminate the output pulse at a predetermined time independent of the timing components. This (CLR) input also serves as a trigger input when it is pulsed with a low level pulse transition (ß). To obtain the best and trouble free operation from this device please read operating rules as well as the NSC one-shot application notes carefully and observe recommendations. Features Y Y Y Y Y Y Y Pin-out identical to ’LS123 (Note 1) Output pulse width range from 30 ns to 70 seconds Hysteresis provided at (B) input for added noise immunity Direct reset terminates output pulse Triggerable from CLEAR input DTL, TTL compatible Input clamp diodes Note 1: The pin-out is identical to ’LS123 but, functionally it is not; refer to Operating Rules Ý10 in this datasheet. Functional Description The basic output pulse width is determined by selection of an external resistor (RX) and capacitor (CX). Once triggered, the basic pulse width is independent of further input transitions and is a function of the timing components, or it may be reduced or terminated by use of the active low CLEAR input. Stable output pulse width ranging from 30 ns to 70 seconds is readily obtainable. A dual, highly stable one-shot Compensated for VCC and temperature variations Connection Diagram Function Table Dual-In-Line Package Inputs Outputs CLEAR A B Q Q L X X H H X H X L X X L v u L L L L É É É H H H ß ß ß * u H H H e High Logic Level L e Low Logic Level X e Can Be Either Low or High u e Positive Going Transition v e Negative Going Transition É e A Positive Pulse ß e A Negative Pulse TL/F/6409 – 1 *This mode of triggering requires first the B input be set from a low to high level while the CLEAR input is maintained at logic low level. Then with the B input at logic high level, the CLEAR input whose positive transition from low to high will trigger an output pulse. Order Number DM74LS221M or DM74LS221N See NS Package Number M16A or N16A TL/F/6409 – 2 C1995 National Semiconductor Corporation TL/F/6409 RRD-B30M105/Printed in U. S. A. DM74LS221 Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs February 1992 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage Input Voltage Operating Free Air Temperature Range DM74LS Storage Temperature Range 7V 7V 0§ C to a 70§ C b 65§ C to a 150§ C Recommended Operating Conditions Symbol DM74LS221 Parameter Units Min Nom Max 4.75 5 5.25 V 1 2 V VCC Supply Voltage VT a Positive-Going Input Threshold Voltage at the A Input (VCC e Min) VTb Negative-Going Input Threshold Voltage at the A Input (VCC e Min) VT a Positive-Going Input Threshold Voltage at the B Input (VCC e Min) VTb Negative-Going Input Threshold Voltage at the B Input (VCC e Min) IOH High Level Output Current b 0.4 mA IOL Low Level Output Current 8 mA tW Pulse Width (Note 1) 0.8 1 1 0.8 Data 40 Clear 40 V 2 0.9 V V ns tREL Clear Release Time (Note 1) dV dt Rate of Rise or Fall of Schmitt Input (B) (Note 1) 15 1 V s dV dt Rate of Rise or Fall of Logic Input (A) (Note 1) 1 V ms REXT External Timing Resistor (Note 1) 1.4 100 kX 0 1000 mF CEXT External Timing Capacitance (Note 1) DC Duty Cycle (Note 1) TA ns RT e 2 kX 50 RT e REXT (Max) 60 Free Air Operating Temperature 0 70 % §C Note 1: TA e 25§ C and VCC e 5V. Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC e Min, II e b18 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max VIL e Max, VIH e Min II Input Current @ Max Input Voltage Min 2.7 Typ (Note 1) Max Units b 1.5 V 3.4 0.35 V 0.5 VCC e Min, IOL e 4 mA 0.4 VCC e Max, VI e 7V 0.1 2 V mA Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) (Continued) Symbol Parameter Conditions IIH High Level Input Current VCC e Max, VI e 2.7V IIL Low Level Input Current VCC e Max VI e 0.4V IOS Short Circuit Output Current VCC e Max (Note 2) ICC Supply Current VCC e Max Min Typ (Note 1) Max Units 20 mA A1, A2 b 0.4 B b 0.8 Clear b 0.8 b 20 b 100 Quiescent 4.7 11 Triggered 19 27 mA mA mA Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Switching Characteristics at VCC e 5V and TA e 25§ C Parameter From (Input) To (Output) tPLH Propagation Delay Time Low to High Level Output A1, A2 to Q tPLH Propagation Delay Time Low to High Level Output B to Q tPHL Propagation Delay Time High to Low Level Output tPHL Symbol Max Units 70 ns 55 ns A1, A2 to Q 80 ns Propagation Delay Time High to Low Level Output B to Q 65 ns tPLH Propagation Delay Time Low to High Level Output Clear to Q 65 ns tPHL Propagation Delay Time High to Low Level Output Clear to Q 55 ns tW(out) Output Pulse Width Using Zero Timing Capacitance A1, A2 to Q, Q CEXT e 0 REXT e 2 kX RL e 2 kX CL e 15 pF 20 70 ns Output Pulse Width Using External Timing Resistor A1, A2 to Q, Q CEXT e 100 pF REXT e 10 kX RL e 2 kX CL e 15 pF 600 750 ns CEXT e 1 mF REXT e 10 kX RL e 2 kX CL e 15 pF 6 7.5 ms CEXT e 80 pF REXT e 2 kX RL e 2 kX CL e 15 pF 70 150 ns tW(out) Conditions Min CEXT e 80 pF REXT e 2 kX CL e 15 pF RL e 2 kX 3 Operating Rules 5. For CX k 1000 pF see Figure 3 for TW vs CX family curves with RX as a parameter: 1. An external resistor (RX) and an external capacitor (CX) are required for proper operation. The value of CX may vary from 0 to approximately 1000 mF. For small time constants high-grade mica, glass, polypropylene, polycarbonate, or polystyrene material capacitor may be used. For large time constants use tantalum or special aluminum capacitors. If timing capacitor has leakages approaching 100 nA or if stray capacitance from either terminal to ground is greater than 50 pF the timing equations may not represent the pulse width the device generates. 2. When an electrolytic capacitor is used for CX a switching diode is often required for standard TTL one-shots to prevent high inverse leakage current. This switching diode is not needed for the ’LS221 one-shot and should not be used. Furthermore, if a polarized timing capacitor is used on the ’LS221, the positive side of the capacitor should be connected to the ‘‘CEXT’’ pin (Figure 1 ) . TL/F/6409 – 4 FIGURE 3 6. To obtain variable pulse widths by remote trimming, the following circuit is recommended: TL/F/6409 – 5 Note: ‘‘Rremote’’ should be as close to the one-shot as possible. FIGURE 4 TL/F/6409 – 8 7. Output pulse width versus VCC and temperatures: Figure 5 depicts the relationship between pulse width variation versus VCC. Figure 6 depicts pulse width variation versus temperatures. FIGURE 1 3. For CX ll 1000 pF, the output pulse width (TW) is defined as follows: TW e KRX CX where [RX is in kX] [CX is in pF] [TW is in ns] K & Ln2 e 0.70 4. The multiplicative factor K is plotted as a function of CX below for design considerations: TL/F/6409 – 6 FIGURE 5 TL/F/6409 – 3 FIGURE 2 TL/F/6409 – 7 FIGURE 6 4 Operating Rules (Continued) 8. Duty cycle is defined as TW/T c 100 in percentage, if it goes above 50% the output pulse width will become shorter. If the duty cycle varies between low and high values, this causes output pulse width to vary, or jitter (a function of the REXT only). To reduce jitter , REXT should be as large as possible, for example, with REXT e 100k jitter is not appreciable until the duty cycle approaches 90%. 9. Under any operating condition CX and RX must be kept as close to the one-shot device pins as possible to minimize stray capacitance, to reduce noise pick-up, and to reduce I-R and Ldi/dt voltage developed along their connecting paths. If the lead length from CX to pins (6) and (7) or pins (14) and (15) is greater than 3 cm, for example, the output pulse width might be quite different from values predicted from the appropriate equations. A noninductive and low capacitive path is necessary to ensure complete discharge of CX in each cycle of its operation so that the output pulse width will be accurate. 10. Although the ’LS221’s pin-out is identical to the ’LS123 it should be remembered that they are not functionally identical. The ’LS123 is a retriggerable device such that the output is dependent upon the input transitions when its output ‘‘Q’’ is at the ‘‘High’’ state. Furthermore, it is recommended for the ’LS123 to externally ground the CEXT pin for improved system performance. However, this pin on the ’LS221 is not an internal connection to the device ground. Hence, if substitution of an ’LS221 onto an ’LS123 design layout where the CEXT pin is wired to the ground, the device will not function. 11. VCC and ground wiring should conform to good highfrequency standards and practices so that switching transients on the VCC and ground return leads do not cause interaction between one-shots. A 0.01 mF to 0.10 mF bypass capacitor (disk ceramic or monolithic type) from VCC to ground is necessary on each device. Furthermore, the bypass capacitor should be located as close to the VCC-pin as space permits. For further detailed device characteristics and output performance, please refer to the NSC one-shot application note AN-372. Physical Dimensions inches (millimeters) 16-Lead Small Outline Molded Package (M) Order Number DM74LS221M NS Package Number M16A 5 DM74LS221 Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs Physical Dimensions inches (millimeters) (Continued) 16-Lead Molded Dual-In-Line Package (N) Order Number DM74LS221N NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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