SN74LS122 SN74LS123 Retriggerable Monostable Multivibrators These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS122 has an internal timing resistor that allows the circuits to be used with only an external capacitor. Once triggered, the basic pulse width may be extended by retriggering the gated low-level-active (A) or high-level-active (B) inputs, or be reduced by use of the overriding clear. • Overriding Clear Terminates Output Pulse • Compensated for VCC and Temperature Variations • DC Triggered from Active-High or Active-Low Gated Logic Inputs • Retriggerable for Very Long Output Pulses, up to 100% Duty Cycle • Internal Timing Resistors on LS122 http://onsemi.com LOW POWER SCHOTTKY 14 1 PLASTIC N SUFFIX CASE 646 GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage Min Typ Max Unit 4.75 5.0 5.25 V 0 25 70 °C TA Operating Ambient Temperature Range IOH Output Current – High – 0.4 mA IOL Output Current – Low 8.0 mA Rext External Timing Resistance 260 kW Cext External Capacitance Rext/Cext Wiring Capacitance at Rext/Cext Terminal 5.0 14 1 SOIC D SUFFIX CASE 751A No Restriction 16 50 pF 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 6 1 Device Package Shipping SN74LS122N 14 Pin DIP 2000 Units/Box SN74LS122D 14 Pin 2500/Tape & Reel SN74LS123N 16 Pin DIP 2000 Units/Box SN74LS123D 16 Pin 2500/Tape & Reel Publication Order Number: SN74LS122/D SN74LS122 SN74LS123 SN74LS123 (TOP VIEW) (SEE NOTES 1 THRU 4) 1 Rext/ 1 Cext Cext VCC 16 15 14 1Q 2Q 2 CLR 2B 2A 13 12 11 10 9 Q Q CLR Q 1 1A 2 1B 3 1 CLR CLR Q 4 1Q 5 2Q 8 7 2 GND Rext/ Cext 6 2 Cext SN74LS122 (TOP VIEW) (SEE NOTES 1 THRU 4) VCC Rext/ Cext NC Cext NC Rint Q 14 13 12 11 10 9 8 6 Q 7 GND Rint Q CLR Q 1 A1 2 A2 3 B1 4 B2 5 CLR NC — NO INTERNAL CONNECTION. NOTES: 1. An external timing capacitor may be connected between Cext and Rext/Cext (positive). 2. To use the internal timing resistor of the LS122, connect Rint to VCC. 3. For improved pulse width accuracy connect an external resistor between Rext/Cext and VCC with Rint open-circuited. 4. To obtain variable pulse widths, connect an external variable resistance between Rint/Cext and VCC. http://onsemi.com 2 SN74LS122 SN74LS123 LS122 FUNCTIONAL TABLE LS123 FUNCTIONAL TABLE INPUTS OUTPUTS INPUTS OUTPUTS CLEAR A1 A2 B1 B2 Q Q CLEAR A B Q Q L X X X H H H H H H H ↑ ↑ X H X X L L X X H ↓ ↓ L X X H X X X X L L ↓ ↓ H X L X X L X ↑ H ↑ H H H H H H X X X L H ↑ H ↑ H H H H H L L L L H H H H L X X H H ↑ X H X L ↓ L X X L ↑ H H L L L H H H TYPICAL APPLICATION DATA The output pulse tW is a function of the external components, Cext and Rext or Cext and Rint on the LS122. For values of Cext ≥ 1000 pF, the output pulse at VCC = 5.0 V and VRC = 5.0 V (see Figures 1, 2, and 3) is given by tW = K Rext Cext where K is nominally 0.45 Figures 5 and 6 show the behavior of the circuit shown in Figures 1 and 2 if separate power supplies are used for VCC and VRC. If VCC is tied to VRC, Figure 7 shows how K will vary with VCC and temperature. Remember, the changes in Rext and Cext with temperature are not calculated and included in the graph. As long as Cext ≥ 1000 pF and 5K ≤ Rext ≤ 260K, the change in K with respect to Rext is negligible. If Cext ≤ 1000 pF the graph shown on Figure 8 can be used to determine the output pulse width. Figure 9 shows how K will change for Cext ≤ 1000 pF if VCC and VRC are connected to the same power supply. The pulse width tW in nanoseconds is approximated by tW = 6 + 0.05 Cext (pF) + 0.45 Rext (kΩ) Cext + 11.6 Rext If Cext is on pF and Rext is in kΩ then tW is in nanoseconds. The Cext terminal of the LS122 and LS123 is an internal connection to ground, however for the best system performance Cext should be hard-wired to ground. Care should be taken to keep Rext and Cext as close to the monostable as possible with a minimum amount of inductance between the Rext/Cext junction and the Rext/Cext pin. Good groundplane and adequate bypassing should be designed into the system for optimum performance to ensure that no false triggering occurs. It should be noted that the Cext pin is internally connected to ground on the LS122 and LS123, but not on the LS221. Therefore, if Cext is hard-wired externally to ground, substitution of a LS221 onto a LS123 socket will cause the LS221 to become non-functional. The switching diode is not needed for electrolytic capacitance application and should not be used on the LS122 and LS123. To find the value of K for Cext ≥ 1000 pF, refer to Figure 4. Variations on VCC or VRC can cause the value of K to change, as can the temperature of the LS123, LS122. In order to trim the output pulse width, it is necessary to include a variable resistor between VCC and the Rext/Cext pin or between VCC and the Rext pin of the LS122. Figure 10, 11, and 12 show how this can be done. Rext remote should be kept as close to the monostable as possible. Retriggering of the part, as shown in Figure 3, must not occur before Cext is discharged or the retrigger pulse will not have any effect. The discharge time of Cext in nanoseconds is guaranteed to be less than 0.22 Cext (pF) and is typically 0.05 Cext (pF). For the smallest possible deviation in output pulse widths from various devices, it is suggested that Cext be kept ≥ 1000 pF. http://onsemi.com 3 SN74LS122 SN74LS123 WAVEFORMS RETRIGGER PULSE (See Application Data) B INPUT Q OUTPUT tW OUTPUT WITHOUT RETRIGGER EXTENDING PULSE WIDTH B INPUT CLEAR PULSE CLEAR INPUT OUTPUT WITHOUT CLEAR PULSE Q OUTPUT OVERRIDING THE OUTPUT PULSE http://onsemi.com 4 SN74LS122 SN74LS123 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL O Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Min Parameter Typ Max 2.0 0.8 – 0.65 2.7 – 1.5 3.5 Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 0.25 0.4 V IOL = 4.0 mA 0.35 0.5 V IOL = 8.0 mA 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V – 0.4 mA VCC = MAX, VIN = 0.4 V –100 mA VCC = MAX mA VCC = MAX – 20 LS122 11 LS123 20 Power Supply Current Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Typ Max Propagation g Delay, y A to Q Propagation Delay, A to Q 23 33 32 45 Propagation g Delay, y B to Q Propagation Delay, B to Q 23 44 34 56 tPLH tPHL Propagation g Delay, y Clear to Q Propagation Delay, Clear to Q 28 45 20 27 tW min A or B to Q 116 200 ns tWQ A to B to Q 4.5 5.0 µs Max Unit Symbol tPLH tPHL tPLH tPHL Parameter Min Unit Test Conditions ns Cext = 0 CL = 15 pF ns Rext = 5.0 kΩ RL = 2.0 kΩ ns 4.0 Cext = 1000 pF, Rext = 10 kΩ, CL = 15 pF, RL = 2.0 kΩ AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol tW Parameter Pulse Width Min Typ 40 ns http://onsemi.com 5 Test Conditions SN74LS122 SN74LS123 VRC VCC VCC VCC Pin A 51 Ω 0.1 µF Pout Q Pin GND 51 Ω Figure 1. Pin tW RETRIGGER Figure 3. 10 5K ≤ Rext ≤ 260K EXTERNAL CAPACITANCE, Cext ( µF) Cext Cext Rext/ VCC CLR Cext Q B2 LS122 B1 A2 Q A1 GND Figure 2. Pout 1 0.1 0.01 0.001 VCC Rext Rext Cext Cext Rext/ VCC Cext Q CLR 1/2 LS123 B VRC 0.3 0.35 0.4 K 0.45 0.5 Figure 4. http://onsemi.com 6 0.55 0.1 µF Pout SN74LS122 SN74LS123 0.55 0.55 0.55 VCC = 5 V Cext = 1000 pF VRC = 5 V Cext = 1000 pF 0.5 0.5 – 55°C K K 0°C 25°C 0°C 0.45 0.5 – 55°C 0°C – 55°C K Cext = 1000 pF 0.45 0.45 70°C 25°C 25°C 70°C 70°C 125°C 0.4 125°C 0.4 0.4 125°C 0.35 0.35 4.5 5 VCC 5.5 0.35 4.5 Figure 5. K versus VCC 5 VRC 5.5 Figure 6. K versus VRC 4.5 5 VCC = VRC Figure 7. K versus VCC and VRC 100000 Rext = 260 kΩ Rext = 160 kΩ t W, OUTPUT PULSE WIDTH (ns) 10000 1000 100 10 Rext = 80 kΩ Rext = 40 kΩ Rext = 20 kΩ Rext = 10 kΩ Rext = 5 kΩ 1 10 100 Cext, EXTERNAL TIMING CAPACITANCE (pF) Figure 8. http://onsemi.com 7 5.5 1000 SN74LS122 SN74LS123 0.65 Cext = 200 pF – 55°C 0.6 0°C 25°C 70°C K 0.55 125°C 0.5 4.5 4.75 5 VCC VOLTS 5.25 5.5 Figure 9. VCC Rext PIN 7 OR 15 Cext PIN 6 OR 14 Figure 10. LS123 Remote Trimming Circuit http://onsemi.com 8 Rext REMOTE SN74LS122 SN74LS123 VCC PIN 9 OPEN Rext Rext REMOTE PIN 13 Cext PIN 11 Figure 11. LS122 Remote Trimming Circuit Without Rext VCC Rext REMOTE PIN 9 PIN 13 PIN 11 Figure 12. LS122 Remote Trimming Circuit with Rint http://onsemi.com 9 SN74LS122 SN74LS123 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 646–06 ISSUE M 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. 8 B 1 7 A F DIM A B C D F G H J K L M N L N C –T– SEATING PLANE J K H D 14 PL G M 0.13 (0.005) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– 8 –B– 1 P 7 PL 0.25 (0.010) 7 G M B M R X 45 _ C F –T– SEATING PLANE D 14 PL 0.25 (0.010) M T B J M K S A MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 ––– 10_ 0.38 1.01 M D SUFFIX PLASTIC SOIC PACKAGE CASE 751A–03 ISSUE F 14 INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 ––– 10_ 0.015 0.039 S http://onsemi.com 10 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 SN74LS122 SN74LS123 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C DIM A B C D F G H J K L M S L S SEATING PLANE –T– K H G D M J 16 PL 0.25 (0.010) T A M M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 11 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 SN74LS122 SN74LS123 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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