SN54/74LS290
SN54/74LS293
DECADE COUNTER;
4-BIT BINARY COUNTER
The SN54 / 74LS290 and SN54/ 74LS293 are high-speed 4-bit ripple type
counters partitioned into two sections. Each counter has a divide-by-two section and either a divide-by-five (LS290) or divide-by-eight (LS293) section
which are triggered by a HIGH-to-LOW transition on the clock inputs. Each
section can be used separately or tied together (Q to CP)to form BCD,
Bi-quinary, or Modulo-16 counters. Both of the counters have a 2-input gated
Master Reset (Clear), and the LS290 also has a 2-input gated Master Set
(Preset 9).
•
•
•
•
•
Corner Power Pin Versions of the LS90 and LS93
Low Power Consumption . . . Typically 45 mW
High Count Rates . . . Typically 42 MHz
Choice of Counting Modes . . . BCD, Bi-Quinary, Binary
Input Clamp Diodes Limit High Speed Termination Effects
DECADE COUNTER;
4-BIT BINARY COUNTER
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 632-08
14
1
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC
MR
MR
CP1
CP0
Q0
Q3
14
13
12
11
10
9
8
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
LS290
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
14
1
MS
2
NC
3
MS
4
Q2
5
Q1
6
NC
7
GND
VCC
MR
MR
CP1
CP0
Q0
Q3
14
13
12
11
10
9
8
1
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LS293
1
NC
2
NC
3
NC
4
Q2
5
Q1
6
NC
7
GND
PIN NAMES
LOADING (Note a)
HIGH
CP0
CP1
CP1
MR1, MR2
MS1, MS2
Q0
Q1, Q2, Q3
Clock (Active LOW going edge) Input to ÷ 2 Section.
Clock (Active LOW going edge) Input to ÷ 5 Section (LS290).
Clock (Active LOW going edge) Input to ÷ 8 Section (LS293).
Master Reset (Clear) Inputs
Master Set (Preset-9, LS290) Inputs
Output from ÷ 2 Section (Notes b & c)
Outputs from ÷ 5 & ÷ 8 Sections (Note b)
0.05 U.L.
0.05 U.L.
0.05 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.
c) The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 Input of the device.
FAST AND LS TTL DATA
5-466
LOW
1.5 U.L.
2.0 U.L.
1.0 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
SN54/74LS290 D SN54/74LS293
LOGIC SYMBOL
LS290
LS293
LOGIC DIAGRAMS
LS290
LS293
FAST AND LS TTL DATA
5-467
SN54/74LS290 D SN54/74LS293
FUNCTIONAL DESCRIPTION
The LS290 and LS293 are 4-bit ripple type Decade, and
4-Bit Binary counters respectively. Each device consists of
four master/ slave flip-flops which are internally connected to
provide a divide-by-two section and a divide-by-five (LS290)
or divide-by-eight (LS293) section. Each section has a
separate clock input which initiates state changes of the
counter on the HIGH-to-LOW clock transition. State changes
of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are
subject to decoding spikes and should not be used for clocks
or strobes. The Q0 output of each device is designed and
specified to drive the rated fan-out plus the CP1 input of the
device.
A gated AND asynchronous Master Reset (MR 1 ⋅ MR2) is
provided on both counters which overrides the clocks and
resets (clears) all the flip-flops. A gated AND asynchronous
Master Set (MS1 ⋅ MS2) is provided on the LS290 which
overrides the clocks and the MR inputs and sets the outputs to
nine (HLLH).
Since the output from the divide-by-two section is not
internally connected to the succeeding stages, the devices
may be operated in various counting modes:
LS290
A. BCD Decade (8421) Counter — the CP1 input must be
externally connected to the Q0 output. The CP0 input
receives the incoming count and a BCD count sequence is
produced.
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3
output must be externally connected to the CP0 input. The
input count is then applied to the CP1 input and a
divide-by-ten square wave is obtained at output Q0.
C. Divide-By-Two and Divide-By-Five Counter — No external
interconnections are required. The first flip-flop is used as a
binary element for the divide-by-two function (CP 0 as the
input and Q0 as the output). The CP1 input is used to obtain
binary divide-by-five operation at the Q3 output.
LS293
A. 4-Bit Ripple Counter — The output Q0 must be externally
connected to input CP1. The input count pulses are applied
to input CP0. Simultaneous division of 2, 4, 8, and 16 are
performed at the Q0, Q1, Q2, and Q3 outputs as shown in
the truth table.
B. 3-Bit Ripple Counter — The input count pulses are applied
to input CP1. Simultaneous frequency divisions of 2, 4, and
8 are available at the Q1, Q2, and Q3 outputs. Independent
use of the first flip-flop is available if the reset function
coincides with reset of the 3-bit ripple-through counter.
LS290 MODE SELECTION
RESET/SET INPUTS
LS293 MODE SELECTION
OUTPUTS
MR1
MR2
MS1
MS2
Q0
Q1
H
H
X
L
X
L
X
H
H
X
X
L
X
L
L
X
H
L
X
X
L
X
L
H
X
L
L
X
L
L
H
L
L
L
Q2
L
L
L
Count
Count
Count
Count
RESET INPUTS
Q3
MR1
MR2
Q0
Q1
L
L
H
H
L
H
L
H
H
L
L
L
L
0
1
2
3
4
5
6
7
8
9
Q2
Q3
L
Count
Count
Count
L
TRUTH TABLE
OUTPUT
LS290
BCD COUNT SEQUENCE
COUNT
OUTPUTS
COUNT
OUTPUT
Q0
Q1
Q2
Q3
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NOTE: Output Q0 is connected to Input CP1
for BCD count.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Q0
Q1
Q2
Q3
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Note: Output Q0 connected to input CP1.
FAST AND LS TTL DATA
5-468
SN54/74LS290 • SN54/74LS293
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
– 55
0
25
25
125
70
°C
IOH
Output Current — High
54, 74
– 0.4
mA
IOL
Output Current — Low
54
74
4.0
8.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Min
Parameter
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIK
Input Clamp Diode Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIH
Input HIGH Current
IIL
Input LOW Current
MS, MR
CP0
CP1 (LS290)
CP1 (LS293)
IOS
Short Circuit Current (Note 1)
ICC
Power Supply Current
Typ
Max
Unit
2.0
54
0.7
74
0.8
– 0.65
– 1.5
Test Conditions
V
Guaranteed Input HIGH Voltage for
All Inputs
V
Guaranteed Input LOW Voltage for
All Inputs
V
VCC = MIN, IIN = – 18 mA
54
2.5
3.5
V
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
54, 74
0.25
0.4
V
IOL = 4.0 mA
74
0.35
0.5
V
IOL = 8.0 mA
20
µA
VCC = MAX, VIN = 2.7 V
0.1
mA
VCC = MAX, VIN = 7.0 V
mA
VCC = MAX, VIN = 0.4 V
– 100
mA
VCC = MAX
15
mA
VCC = MAX
–0.4
–2.4
–3.2
–1.6
–20
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
5-469
SN54/74LS290 D SN54/74LS293
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, CL = 15 pF)
Limits
LS290
Symbol
Parameter
Min
Typ
LS293
Max
Min
Typ
Unit
Max
fMAX
CP0 Input Clock Frequency
32
32
MHz
fMAX
CP1 Input Clock Frequency
16
tPLH
tPHL
Propagation Delay,
CP0 Input to Q0 Output
10
12
16
18
10
12
16
18
ns
tPLH
tPHL
CP0 Input to Q3 Output
32
34
48
50
46
46
70
70
ns
tPLH
tPHL
CP1 Input to Q1 Output
10
14
16
21
10
14
16
21
ns
tPLH
tPHL
CP1 Input to Q2 Output
21
23
32
35
21
23
32
35
ns
tPLH
tPHL
CP1 Input to Q3 Output
21
23
32
35
34
34
51
51
ns
tPHL
MS Input to Q0 and Q3 Outputs
20
30
ns
tPHL
MS Input to Q1 and Q2 Outputs
26
40
ns
tPHL
MR Input to Any Output
26
40
16
MHz
26
40
ns
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits
LS290
Symbol
Parameter
Min
LS293
Max
Min
Unit
Max
tW
CP0 Pulse Width
15
15
ns
tW
CP1 Pulse Width
30
30
ns
tW
MS Pulse Width
15
tW
MR Pulse Width
15
15
ns
trec
Recovery Time MR to CP
25
25
ns
ns
RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition form HIGH-to-LOW in order to
recognize and transfer HIGH data to the Q outputs.
AC WAVEFORMS
Figure 1
*The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the appropriate Truth Tables.
⋅ Figure 2
Figure 3
FAST AND LS TTL DATA
5-470
Case 751A-02 D Suffix
14-Pin Plastic
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FAST AND LS TTL DATA
5-471
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◊
FAST AND LS TTL DATA
5-472