SN54/74LS196 SN54/74LS197 4-STAGE PRESETTABLE RIPPLE COUNTERS The SN54/74LS196 decade counter is partitioned into divide-by-two and divide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1) sequence or in a bi-quinary mode producing a 50% duty cycle output. The SN54/74LS197 contains divide-by-two and divide-by-eight sections which can be combined to form a modulo-16 binary counter. Low Power Schottky technology is used to achieve typical count rates of 70 MHz and power dissipation of only 80 mW. Both circuit types have a Master Reset (MR) input which overrides all other inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL) overrides clocked operations and asynchronously loads the data on the Parallel Data inputs (Pn) into the flip-flops. This preset feature makes the circuits usable as programmable counters. The circuits can also be used as 4-bit latches, loading data from the Parallel Data inputs when PL is LOW and storing the data when PL is HIGH. • • • • • • • 4-STAGE PRESETTABLE RIPPLE COUNTERS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 632-08 14 1 Low Power Consumption — Typically 80 mW High Counting Rates — Typically 70 MHz Choice of Counting Modes — BCD, Bi-Quinary, Binary Asynchronous Presettable Asynchronous Master Reset Easy Multistage Cascading Input Clamp Diodes Limit High Speed Termination Effects N SUFFIX PLASTIC CASE 646-06 14 1 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 14 MR Q3 13 12 P3 11 P1 10 Q1 CP0 9 8 D SUFFIX SOIC CASE 751A-02 14 1 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 PL 2 Q2 3 P2 4 P0 5 Q0 6 CP1 LOADING (Note a) CP1 (LS197) MR PL P0–P3 Q0–Q3 Clock (Active LOW Going Edge) Input to Divide-by-Two Section Clock (Active LOW Going Edge) Input to Divide-by-Five Section Clock (Active LOW Going Edge) Input to Divide-by-Eight Section Master Reset (Active LOW) Input Parallel Load (Active LOW) Input Data Inputs Outputs (Notes b, c) 1.0 U.L. 1.5 U.L. 2.0 U.L. 1.75 U.L. 1.0 U.L. 0.8 U.L. 1.0 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 0.5 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. NOTES: a. 1 TTL Unit Load (U.L.) = 40µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. c. In addition to loading shown, Q0 can also drive CP1. FAST AND LS TTL DATA 5-1 Ceramic Plastic SOIC LOGIC SYMBOL LOW HIGH CP1 (LS196) SN54LSXXXJ SN74LSXXXN SN74LSXXXD 7 GND PIN NAMES CP0 ORDERING INFORMATION 1 4 10 3 11 8 CP0 PL P0 P1 P2 P3 6 CP1 MR Q0 Q1 Q2 Q3 13 5 9 2 12 VCC = PIN 14 GND = PIN 7 SN54/74LS196 • SN54/74LS197 LOGIC DIAGRAM P0 13 P1 4 P2 10 P3 3 11 MR PL 1 8 J SD Q J SD Q J SD Q J SD Q K CD Q K CD Q K CD Q K CD Q CP0 6 CP1 5 12 2 9 Q0 Q1 Q2 Q3 LS196 P0 13 P1 4 P2 10 P3 3 11 MR PL 1 8 J SD Q J SD Q J SD Q J SD Q K CD Q K CD Q K CD Q K CD Q CP0 6 CP1 5 9 Q0 Q1 LS197 VCC = PIN 14 GND = PIN 7 = PIN NUMBERS FAST AND LS TTL DATA 5-2 2 Q2 12 Q3 SN54/74LS196 • SN54/74LS197 FUNCTIONAL DESCRIPTION The LS196 and LS197 are asynchronously presettable decade and binary ripple counters. The LS196 Decade Counter is partitioned into divide-by-two and divide-by-five sections while the LS197 is partitioned into divide-by-two and divideby-eight sections, with all sections having a separate Clock input. In the counting modes, state changes are initiated by the HIGH to LOW transition of the clock signals. State changes of the Q outputs, however, do not occur simultaneously because of the internal ripple delays. When using external logic to decode the Q outputs, designers should bear in mind that the unequal delays can lead to decoding spikes and thus a decoded signal should not be used as a clock or strobe. The CP0 input serves the Q0 flip-flop in both circuit types while the CP1 input serves the divide-by-five or divide-by-eight section. The Q0 output is designed and specified to drive the rated fan-out plus the CP1 input. With the input frequency connected to CP0 and Q0 driving CP1, the LS197 forms a straightforward module-16 counter, with Q0 the least significant output and Q3 the most significant output. The LS196 Decade Counter can be connected up to operate in two different count sequences, as indicated in the tables of Figure 2. With the input frequency connected to CP0 and with Q0 driving CP1, the circuit counts in the BCD (8, 4, 2, 1) sequence. With the input frequency connected to CP1 and Q3 driving CP0, Q0 becomes the low frequency output and has a 50% duty cycle waveform. Note that the maximum counting rate is reduced in the latter (bi-quinary) configuration because of the interstage gating delay within the divide-by-five section. The LS196 and LS197 have an asynchronous active LOW Master Reset input (MR) which overrides all other inputs and forces all outputs LOW. The counters are also asynchronously presettable. A LOW on the Parallel Load input (PL) overrides the clock inputs and loads the data from Parallel Data (P0 – P3) inputs into the flip-flops. While PL is LOW, the counters act as transparent latches and any change in the Pn inputs will be reflected in the outputs. Figure 2. LS196 COUNT SEQUENCES DECADE (NOTE 1) BI-QUINARY (NOTE 2) COUNT Q3 Q2 Q1 Q0 COUNT Q0 Q3 Q2 Q1 0 1 2 3 4 5 6 7 8 9 L L L L L L L L H H L L L L H H H H L L L L H H L L H H L L L H L H L H L H L H 0 1 2 3 4 5 6 7 8 9 L L L L L H H H H H L L L L H L L L L H L L H H L L L H H L L H L H L L H L H L NOTES: 1. Signal applied to CP0, Q0 connected to CP1. 2. Signal applied to CP1, Q3 connected to CP0. MODE SELECT TABLE INPUTS RESPONSE MR PL CP L H H X L H X X Reset (Clear) Parallel Load Count H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care = HIGH to Low Clock Transition FAST AND LS TTL DATA 5-3 SN54/74LS196 • SN54/74LS197 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 74 4.0 8.0 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits S b l Symbol Min P Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage Typ Max 2.0 54 0.7 74 0.8 – 0.65 – 1.5 VCC = MIN, IIN = – 18 mA 74 2.7 3.5 V VCC = MIN,, IOH = MAX,, VIN = VIH or VIL per Truth Table IIH 20 40 40 80 Data, PL MR, CP0 (LS196) MR, CP0, CP1 (LS197) CP1 (LS196) 0.1 0.2 0.2 0.4 Power Supply Current Guaranteed Input p LOW Voltage g for All Inputs V Input HIGH Current Data, PL MR, CP0 (LS196) MR, CP0, CP1 (LS197) CP1 (LS196) Short Circuit Current (Note 1) V V Output LOW Voltage ICC Guaranteed Input HIGH Voltage for All Inputs 3.5 VOL IOS V 2.5 Output HIGH Voltage IIL T Test C Conditions di i 54 VOH Input LOW Current Data, PL MR CP0 CP1 (LS196) CP1 (LS197) U i Unit VCC = VCC MIN, VIN = VIL or VIH per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA µA VCC = MAX, VIN = 2.7 V mA VCC = MAX, VIN = 7.0 V mA VCC = MAX, VIN = 0.4 V – 100 mA VCC = MAX 27 mA VCC = MAX – 0.4 – 0.8 – 2.4 – 2.8 – 1.3 – 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-4 SN54/74LS196 • SN54/74LS197 AC CHARACTERISTICS (TA = 25°C) Limits LS196 Symbol S b l Parameter P Min Typ 30 40 LS197 Max Min Typ 30 40 Max Unit U i fMAX Maximum Clock Frequency tPLH tPHL CP0 Input to Q0 Output 8.0 13 15 20 8.0 14 15 21 ns tPLH tPHL CP1 Input to Q1 Output 16 22 24 33 12 23 19 35 ns tPLH tPHL CP1 Input to Q2 Output 38 41 57 62 34 42 51 63 ns tPLH tPHL CP1 Input to Q3 Output 12 30 18 45 55 63 78 95 ns tPLH tPHL Data to Output 20 29 30 44 18 29 27 44 ns tPLH tPHL PL Input to Any Output 27 30 41 45 26 30 39 45 ns tPHL MR Input to Any Output 34 51 34 51 ns Max U i Unit Test C Conditions di i T MHz VCC = 5.0 50V CL = 15 pF AC SETUP REQUIREMENTS (TA = 25°C) Limits LS196 S b l Symbol P Parameter Min Typ LS197 Max Min Typ tW CP0 Pulse Width 20 20 ns tW CP1 Pulse Width 30 30 ns tW PL Pulse Width 20 20 ns tW MR Pulse Width 15 15 ns ts Data Input Setup Time — HIGH 10 10 ns ts Data Input Setup Time — LOW 15 15 ns th Data Hold Time — HIGH 10 10 ns th Data Hold Time — LOW 10 10 ns trec Recovery Time 30 30 ns T Test C Conditions di i VCC = 5.0 50V DEFINITIONS OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from HIGH to LOW in order to be recognized and transferred to the outputs. nition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from HIGH to LOW and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from HIGH to LOW in order to recognize and transfer LOW Data to the Q outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from HIGH to LOW that the logic level must be maintained at the input in order to ensure continued recog- FAST AND LS TTL DATA 5-5 SN54/74LS196 • SN54/74LS197 AC WAVEFORMS CP Q 1.3 V tPHL 1.3 V 1.3 V tW(H) tPLH 1.3 V Figure 1 Pn 1.3 V 1.3 V tPHL Pn tPLH tW PL 1.3 V 1.3 V Qn tPLH 1.3 V Qn NOTE: PL = LOW Figure 2 Figure 3 Pn* PL OR MR 1.3 V 1.3 V th(H) 1.3 V ts(H) ts(L) 1.3 V PL trec tW tPHL th(L) 1.3 V 1.3 V CP tPHL Q Qn* 1.3 V Q=P Q=P * The shaded areas indicate when the input is permitted * to change for predictable output performance Figure 4 Figure 5 FAST AND LS TTL DATA 5-6