SN54/74LS75 SN54/74LS77 4-BIT D LATCH The TTL/MSI SN54 / 74LS75 and SN54 / 74LS77 are latches used as temporary storage for binary information between processing units and input /output or indicator units. Information present at a data (D) input is transferred to the Q output when the Enable is HIGH and the Q output will follow the data input as long as the Enable remains HIGH. When the Enable goes LOW, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the Enable is permitted to go HIGH. The SN54 / 74LS75 features complementary Q and Q output from a 4-bit latch and is available in the 16-pin packages. For higher component density applications the SN54 / 74LS77 4-bit latch is available in the 14-pin package with Q outputs omitted. 4-BIT D LATCH LOW POWER SCHOTTKY CONNECTION DIAGRAMS DIP (TOP VIEW) Q0 Q1 16 15 Q1 14 E0–1 GND 13 12 Q2 Q2 Q3 11 10 9 J SUFFIX CERAMIC CASE 620-09 16 1 SN54 / 74LS75 1 Q0 2 D0 Q0 14 3 D1 Q1 13 4 5 E2–3 VCC E0–1 GND 12 11 NC 10 6 D2 Q2 9 16 8 Q3 7 D3 N SUFFIX PLASTIC CASE 648-08 1 Q3 8 16 1 D SUFFIX SOIC CASE 751B-03 SN54 / 74LS77 1 D0 2 D1 3 E2–3 4 VCC 5 D2 6 D3 PIN NAMES D1–D4 E0–1 E2–3 Q1–Q4 Q1–Q4 J SUFFIX CERAMIC CASE 632-08 7 NC 14 1 LOADING (Note a) Data Inputs Enable Input Latches 0, 1 Enable Input Latches 2, 3 Latch Outputs (Note b) Complimentary Latch Outputs (Note b) HIGH LOW 0.5 U.L. 2.0 U.L. 2.0 U.L. 10 U.L. 10 U.L. 0.25 U.L. 1.0 U.L. 1.0 U.L. 5 (2.5) U.L. 5 (2.5) U.L. NOTES: a) 1 Unit Load (U.L.) = 40 µA HIGH. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 TRUTH TABLE (Each latch) ORDERING INFORMATION tn tn + 1 D H L Q H L NOTES: tn = bit time before enable negative-going transition tn+1 = bit time after enable negative-going transition SN54LSXXJ SN74LSXXN SN74LSXXD FAST AND LS TTL DATA 5-1 Ceramic Plastic SOIC SN54/74LS75 LOGIC SYMBOLS SN54/74LS75 2 5 6 D0 E0–1 E2–3 D1 D2 D3 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q0 Q1 Q2 Q3 16 1 15 14 10 11 9 14 13 9 8 2 13 4 SN54/74LS77 D0 E0–1 E2–3 3 6 7 D1 D2 D3 1 12 3 VCC = PIN 5 GND = PIN 12 8 VCC = PIN 4 GND = PIN 11 NC = PIN 7, 10 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits S b l Symbol Min P Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage Typ 2.0 54 Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current U i Unit T Test C Conditions di i V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input p LOW Voltage g for All Inputs 0.7 74 VOH Max 0.8 V VCC = MIN, IIN = – 18 mA 54 2.5 – 0.65 3.5 – 1.5 V 74 2.7 3.5 V VCC = MIN,, IOH = MAX,, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA D Input E Input 20 80 µA VCC = MAX, VIN = 2.7 V D Input E Input 0.1 0.4 mA VCC = MAX, VIN = 7.0 V D Input E Input – 0.4 –1.6 mA VCC = MAX, VIN = 0.4 V –100 mA VCC = MAX 12 mA VCC = MAX Typ Max U i Unit – 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits S b l Symbol P Parameter Min tPLH tPHL Propagation Delay, Data to Q 15 9.0 27 17 ns tPLH tPHL Propagation Delay, Data to Q 12 7.0 20 15 ns tPLH tPHL Propagation Delay, Enable to Q 15 14 27 25 ns tPLH tPHL Propagation Delay, Enable to Q 16 7.0 30 15 ns FAST AND LS TTL DATA 5-2 T Test C Conditions di i 50V VCC = 5.0 CL = 15 pF SN54/74LS77 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits S b l Symbol Min P Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage Typ Max 2.0 54 0.7 74 0.8 – 0.65 – 1.5 U i Unit T Test C Conditions di i V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input p LOW Voltage g for All Inputs V VCC = MIN, IIN = – 18 mA 54 2.5 3.5 V 74 2.7 3.5 V VCC = MIN,, IOH = MAX,, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA D Input E Input 20 80 µA VCC = MAX, VIN = 2.7 V D Input E Input 0.1 0.4 mA VCC = MAX, VIN = 7.0 V D Input E Input – 0.4 –1.6 mA VCC = MAX, VIN = 0.4 V –100 mA VCC = MAX 13 mA VCC = MAX Typ Max U i Unit Propagation Delay, Data to Q 11 9.0 19 17 ns Propagation Delay, Enable to Q 10 10 18 18 ns IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current – 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits S b l Symbol tPLH tPHL tPLH tPHL P Parameter Min FAST AND LS TTL DATA 5-3 T Test C Conditions di i VCC = 5.0 V CL = 15 pF SN54/74LS75 D SN54/74LS77 LOGIC DIAGRAM DATA Q (SN54/74LS75 ONLY) Q ENABLE TO OTHER LATCH GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 74 4.0 8.0 mA AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits S b l Symbol Min P Parameter Typ Max U i Unit tW Enable Pulse Width High 20 ns ts Setup Time 20 ns th Hold Time 0 ns T Test C Conditions di i VCC = 5.0 50V AC WAVEFORMS D 1.3 V 1.3 V ts E th 1.3 V 1.3 V 1.3 V tPLH Q tPLH tPHL 1.3 V 1.3 V tPHL Q tPHL tPLH 1.3 V tPHL 1.3 V tPLH DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from HIGH-to-LOW in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from HIGH-to-LOW that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from HIGH-to-LOW and still be recognized. FAST AND LS TTL DATA 5-4