SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs. Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect. DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 632-08 LOGIC DIAGRAM (Each Flip-Flop) 14 1 SET (SD) 4 (10) Q 5 (9) CLEAR (CD) 1 (13) CLOCK 3 (11) N SUFFIX PLASTIC CASE 646-06 14 Q 6 (8) 1 D 2 (12) D SUFFIX SOIC CASE 751A-02 14 1 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD MODE SELECT — TRUTH TABLE INPUTS OUTPUTS Ceramic Plastic SOIC OPERATING MODE Set Reset (Clear) *Undetermined Load “1” (Set) Load “0” (Reset) SD SD D Q Q L H L H H H L L H H X X X h l H L H H L L H H L H * Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. If the levels at the set and clear are near VIL maximum then we cannot guarantee to meet the minimum level for VOH. H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Don’t Care i, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time i, h (q) = prior to the HIGH to LOW clock transition. LOGIC SYMBOL 4 10 2 D SD Q 3 CP CD Q 5 12 D SD Q 11 CP 6 1 13 VCC = PIN 14 GND = PIN 7 FAST AND LS TTL DATA 5-72 CD Q 9 8 SN54/74LS74A GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 74 4.0 8.0 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Min Parameter Typ Max 2.0 54 0.7 74 0.8 – 0.65 – 1.5 Output Short Circuit Current (Note 1) ICC Power Supply Current V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA 2.5 3.5 V 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA 20 40 µA VCC = MAX, VIN = 2.7 V mA VCC = MAX, VIN = 7.0 V – 0.4 – 0.8 mA VCC = MAX, VIN = 0.4 V –100 mA VCC = MAX 8.0 mA VCC = MAX Max Unit 0.1 0.2 IOS V 74 Data, Clock Set, Clear Input LOW Current Data, Clock Set, Clear Test Conditions Guaranteed Input HIGH Voltage for All Inputs 54 Input High Current Data, Clock Set, Clear IIL Unit – 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Min Typ 25 33 Clock, Clear, Set to Output MHz 13 25 ns 25 40 ns Max Unit Test Conditions Figure 1 Figure 1 VCC = 5.0 V CL = 15 pF AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol Parameter Min Typ Test Conditions tW (H) Clock 25 ns Figure 1 tW (L) Clear, Set 25 ns Figure 2 Data Setup Time — HIGH Data Setup Time — LOW 20 ns ts 20 ns th Hold Time 5.0 ns Figure 1 FAST AND LS TTL DATA 5-73 Figure 1 VCC = 5.0 V SN54/74LS74A AC WAVEFORMS 1.3 V D* 1.3 V th(H) th(L) ts(L) ts(H) tW(H) tW(L) 1.3 V 1.3 V CP 1 fMAX tPHL Q tPLH 1.3 V 1.3 V tPHL tPLH 1.3 V 1.3 V Q *The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 1. Clock to Output Delays, Data Set-Up and Hold Times, Clock Pulse Width tW SET 1.3 V 1.3 V tW CLEAR Q 1.3 V tPLH tPHL 1.3 V 1.3 V tPHL Q 1.3 V tPLH 1.3 V 1.3 V Figure 2. Set and Clear to Output Delays, Set and Clear Pulse Widths FAST AND LS TTL DATA 5-74