SEMICONDUCTOR TECHNICAL DATA The MC10E/100E016 is a high-speed synchronous, presettable, cascadable 8-bit binary counter. Architecture and operation are the same as the MC10H016 in the MECL 10H family, extended to 8-bits, as shown in the logic symbol. The counter features internal feedback of TC, gated by the TCLD (terminal count load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pull-downs), the TC feedback is disabled, and counting proceeds continuously, with TC going LOW to indicate an all-one state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TC = LOW, thus functioning as a programmable counter. The Qn outputs do not need to be terminated for the count function to operate properly. To minimize noise and power, unused Q outputs should be left unterminated. • • • • • • • • 8-BIT SYNCHRONOUS BINARY UP COUNTER 700MHz Min. Count Frequency 1000ps CLK to Q, TC Internal TC Feedback (Gated) FN SUFFIX PLASTIC PACKAGE CASE 776-02 8-Bit Fully Synchronous Counting and TC Generation Asynchronous Master Reset Extended 100E VEE Range of – 4.2V to – 5.46V 75kΩ Input Pulldown Resistors FUNCTION TABLE Pinout: 28-Lead PLCC (Top View) PE CE P7 P6 P5 VCCO TC 25 24 23 22 21 20 19 MR 26 18 Q7 CLK 27 17 Q6 TCLD 28 16 VCC VEE 1 15 Q5 NC 2 14 VCCO P0 3 13 Q4 P1 4 12 Q3 5 6 7 8 9 10 11 P2 P3 P4 VCCO Q0 Q1 Q2 CE PE TCLD MR CLK Function X L L H X X L H H H X X X L H X X X L L L L L H Z Z Z Z ZZ X Load Parallel (Pn to Qn) Continuous Count Count; Load Parallel on TC = LOW Hold Masters Respond, Slaves Hold Reset (Qn : = LOW, TC : = HIGH) Z = clock pulse (low to high); ZZ = clock pulse (high to low) PIN NAMES Pin P0 – P7 Q0 – Q7 CE PE MR CLK TC TCLD Function Parallel Data (Preset) Inputs Data Outputs Count Enable Control Input Parallel Load Enable Control Input Master Reset Clock Terminal Count Output TC-Load Control Input * All VCC and VCCO pins are tied together on the die. 12/93 Motorola, Inc. 1996 2–1 REV 2 MC10E016 MC100E016 8-BIT BINARY COUNTER LOGIC DIAGRAM Q1 Q0 Q7 PE TCLD Q0M MASTER CE Q0M SLAVE Q0 CE CE Q Q1 0 Q2 Q3 Q4 Q5 Q6 P7 BIT 1 BIT 0 PO P1 BIT 7 MR CLK BITS 2–6 TC 5 Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay. MOTOROLA 2–2 ECLinPS and ECLinPS Lite DL140 — Rev 4 MC10E016 MC100E016 DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND) 0°C Symbol Characteristic IIH Input HIGH Current IEE Power Supply Current 10E 100E min typ 25°C max min typ 150 85°C max min typ 150 max Unit 150 µA Condition mA 151 151 181 181 151 151 181 181 151 174 181 208 AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND) 0°C Symbol Characteristic min typ fCOUNT Max. Count Frequency 700 900 tPLH tPHL Propagation Delay to Output CLK to Q MR to Q CLK to TC MR to TC 600 600 550 625 725 775 775 775 ts Setup Time Pn CE PE TCLD 150 600 600 500 Hold Time Pn CE PE TCLD tRR tPW th tr tf 25°C min typ 700 900 600 600 550 625 725 775 775 775 – 30 400 400 300 150 600 600 500 350 0 0 100 100 – 400 – 400 – 300 Reset Recovery Time 900 700 Minimum Pulse Width CLK, MR 400 Rise/Fall Times 20 - 80% 300 ECLinPS and ECLinPS Lite DL140 — Rev 4 max 85°C max min typ 700 900 600 600 550 625 725 775 775 775 – 30 400 400 300 150 600 600 500 – 30 400 400 300 350 0 0 100 100 – 400 – 400 – 300 350 0 0 100 100 – 400 – 400 – 300 900 700 900 700 max Unit Condition MHz ps 1000 1000 900 1000 1000 1000 900 1000 1000 1000 1050 1000 ps ps ps 400 400 ps 510 800 300 2–3 510 800 300 510 MOTOROLA MC10E016 MC100E016 FUNCTION TABLE Function Load Count Load Hold Load On Terminal Count Reset PE CE MR TCLD CLK P7-P4 P3 P2 P1 P0 Q7-Q4 Q3 Q2 Q1 Q0 TC L H H H H L H H H H H H H H X X L L L L X H H L L L L L L X L L L L L L L L L L L L L L H X L L L L X X X H H H H H H X Z Z Z Z Z Z Z Z Z Z Z Z Z Z X H X X X X H X X H H H H H H X H X X X X H X X L L L L L L X H X X X X H X X H H H H H H X L X X X X L X X H H H H H H X L X X X X L X X L L L L L L X H H H H L H H H H H H H H H L H H H H L H H H H H H L L H L H H H H L H H H H H H H H L L L L H H L L L L L H H H H L L L H L H L L L L H L H L H L L H H H L H H H H H H L H H H H Applications Information Cascading Multiple E016 Devices For applications which call for larger than 8-bit counters multiple E016s can be tied together to achieve very wide bit width counters. The active low terminal count (TC) output and count enable input (CE) greatly facilitate the cascading of E016 devices. Two E016s can be cascaded without the need for external gating, however for counters wider than 16 bits external OR gates are necessary for cascade implementations. Figure 1 below pictorially illustrates the cascading of 4 E016s to build a 32-bit high frequency counter. Note the E101 gates used to OR the terminal count outputs of the lower order E016s to control the counting operation of the higher order bits. When the terminal count of the preceding device (or devices) goes low (the counter reaches an all 1s state) the more significant E016 is set in its count mode and will count one binary digit upon the next positive clock transition. In addition, the preceding devices will also count one bit thus sending their terminal count outputs back to a high state disabling the count operation of the more significant counters and placing them back into hold modes. Therefore, for an E016 in the chain to count, all of the lower order terminal count outputs must be in the low state. The bit width of the counter can be increased or decreased by simply adding or subtracting E016 devices from Figure 1 and maintaining the logic pattern illustrated in the same figure. The maximum frequency of operation for the cascaded counter chain is set by the propagation delay of the TC output and the necessary setup time of the CE input and the propagation delay through the OR gate controlling it (for 16-bit counters the limitation is only the TC propagation delay and the CE setup time). Figure 1 shows EL01 gates used to control the count enable inputs, however, if the frequency of operation is lower a slower, ECL OR gate can be used. Using the worst case guarantees for these parameters from the ECLinPS data book, the maximum count frequency for a greater than 16-bit counter is 500MHz and that for a 16-bit counter is 625MHz. LOAD Q0 –> Q7 LO CE Q0 –> Q7 PE CE PE TC CLK Q0 –> Q7 PE CLK TC P0 –> P7 PE E016 MSB TC CLK TC EL01 EL01 P0 –> P7 CE E016 E016 E016 LSB CLK CE Q0 –> Q7 P0 –> P7 P0 –> P7 CLOCK Figure 1. 32-Bit Cascaded E016 Counter MOTOROLA 2–4 ECLinPS and ECLinPS Lite DL140 — Rev 4 MC10E016 MC100E016 Applications Information (continued) Note that this assumes the trace delay between the TC outputs and the CE inputs are negligible. If this is not the case estimates of these delays need to be added to the calculations. where: P0 = LSB and P7 = MSB Forcing this input condition as per the setup in Figure 2 will result in the waveforms of Figure 3. Note that the TC output is used as the divide output and the pulse duration is equal to a Programmable Divider Table 1. Preset Values for Various Divide Ratios The E016 has been designed with a control pin which makes it ideal for use as an 8-bit programmable divider. The TCLD pin (load on terminal count) when asserted reloads the data present at the parallel input pin (Pn’s) upon reaching terminal count (an all 1s state on the outputs). Because this feedback is built internal to the chip, the programmable division operation will run at very nearly the same frequency as the maximum counting frequency of the device. Figure 2 below illustrates the input conditions necessary for utilizing the E016 as a programmable divider set up to divide by 113. H PE L CE H TCLD H L L L H H H H P7 P6 P5 P4 P3 P2 P1 P0 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Figure 2. Mod 2 to 256 Programmable Divider To determine what value to load into the device to accomplish the desired division, the designer simply subtracts the binary equivalent of the desired divide ratio from the binary value for 256. As an example for a divide ratio of 113: Pn’s = 256 – 113 = 8F16 = 1000 1111 Load 1001 0000 1001 0001 Ratio P7 P6 P5 P4 P3 P2 P1 P0 2 3 4 5 • • 112 113 114 • • 254 255 256 H H H H • • H H H • • L L L H H H H • • L L L • • L L L H H H H • • L L L • • L L L H H H H • • H L L • • L L L H H H H • • L H H • • L L L H H H L • • L H H • • L L L H L L H • • L H H • • H L L L H L H • • L H L • • L H L full clock period. For even divide ratios, twice the desired divide ratio can be loaded into the E016 and the TC output can feed the clock input of a toggle flip flop to create a signal divided as desired with a 50% duty cycle. A single E016 can be used to divide by any ratio from 2 to 256 inclusive. If divide ratios of greater than 256 are needed multiple E016s can be cascaded in a manner similar to that already discussed. When E016s are cascaded to build larger dividers the TCLD pin will no longer provide a means for loading on terminal count. Because one does not want to reload the counters until all of the devices in the chain have reached terminal count, external gating of the TC pins must be used for multiple E016 divider chains. TC CLK Q7 Preset Data Inputs Divide 1111 1100 1111 1101 1111 1110 1111 1111 Load ••• Clock ••• PE ••• TC DIVIDE BY 113 Figure 3. Divide by 113 E016 Programmable Divider Waveforms ECLinPS and ECLinPS Lite DL140 — Rev 4 2–5 MOTOROLA MC10E016 MC100E016 Applications Information (continued) EL01 Q0 –> Q7 LO CE PE CE Q0 –> Q7 PE CE E016 E016 LSB CLK Q0 –> Q7 TC CLK PE CE E016 TC CLK PO –> P7 PE E016 MSB TC EL01 PO –> P7 Q0 –> Q7 PO –> P7 CLK EL01 TC PO –> P7 CLOCK Figure 4. 32-Bit Cascaded E016 Programmable Divider Figure 4 on the following page shows a typical block diagram of a 32-bit divider chain. Once again to maximize the frequency of operation EL01 OR gates were used. For lower frequency applications a slower OR gate could replace the EL01. Note that for a 16-bit divider the OR function feeding the PE (program enable) input CANNOT be replaced by a wire OR tie as the TC output of the least significant E016 must also feed the CE input of the most significant E016. If the two TC outputs were OR tied the cascaded count operation would not operate properly. Because in the cascaded form the PE feedback is external and requires external gating, the maximum frequency of operation will be significantly less than the same operation in a single device. MOTOROLA Maximizing E016 Count Frequency The E016 device produces 9 fast transitioning single ended outputs, thus VCC noise can become significant in situations where all of the outputs switch simultaneously in the same direction. This VCC noise can negatively impact the maximum frequency of operation of the device. Since the device does not need to have the Q outputs terminated to count properly, it is recommended that if the outputs are not going to be used in the rest of the system they should be left unterminated. In addition, if only a subset of the Q outputs are used in the system only those outputs should be terminated. Not terminating the unused outputs will not only cut down the VCC noise generated but will also save in total system power dissipation. Following these guidelines will allow designers to either be more aggressive in their designs or provide them with an extra margin to the published data book specifications. 2–6 ECLinPS and ECLinPS Lite DL140 — Rev 4 MC10E016 MC100E016 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 776–02 ISSUE D 0.007 (0.180) B Y BRK -N- T L –M M U 0.007 (0.180) X G1 M S N T L –M S S N S D Z -L- -M- D W 28 V 1 C A 0.007 (0.180) M R 0.007 (0.180) M T L –M S T L –M S N S N S H S N S 0.007 (0.180) M T L –M N S S 0.004 (0.100) G J -T- K SEATING PLANE F VIEW S G1 T L –M S N 0.007 (0.180) M T L –M S N S VIEW S S NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). ECLinPS and ECLinPS Lite DL140 — Rev 4 T L –M K1 E S S VIEW D-D Z 0.010 (0.250) 0.010 (0.250) 2–7 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 — 0.025 — 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 — 0.020 2° 10° 0.410 0.430 0.040 — MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 — 0.64 — 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 — 0.50 2° 10° 10.42 10.92 1.02 — MOTOROLA MC10E016 MC100E016 Motorola reserves the right to make changes without further notice to any products herein. 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