MICREL SY10E136JC

6-BIT UNIVERSAL
UP/DOWN COUNTER
Micrel, Inc.
SY100E136
DESCRIPTION
FEATURES
■
■
■
■
■
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SY10E136
SY100E136
SY10E136
550MHz count frequency
Extended 100E VEE range of –4.2V to –5.5V
Look-ahead-carry input and output
Fully synchronous up and down counting
Asynchronous Master Reset
Internal 75KΩ input pull-down resistors
Available in 28-pin PLCC package
The SY10/100E136 are 6-bit synchronous, presettable,
cascadable universal counters. These devices generate
a look-ahead-carry output and accept a look-ahead-carry
input. These two features allow for the cascading of
multiple E136s for wider bit width counters that operate
at very nearly the same frequency as the stand-alone
counter.
The CLOUT output will pulse LOW for one clock cycle
one count before the E136 reaches terminal count. The
COUT output will pulse LOW for one clock cycle when
the counter reaches terminal count. For more information
on utilizing the look-ahead-carry features of the device,
please refer to the applications section of this data sheet.
The differential COUT output facilitates the E136's use in
programmable divider and self-stopping counter
applications.
Unlike the H136 and other similar universal counter
designs, the E136 carry-out and look-ahead-carry-out
signals are registered on chip. This design alleviates the
glitch problem seen on many counters where the carryout signals are merely gated. Because of this architecture,
there are some minor functional differences between the
E136 and H136 counters. The user, regardless of
familiarity with the H136, should read this data sheet
carefully. Note specifically (see block diagram) the
operation of the carry-out outputs and the look-aheadcarry-in input when utilizing the Master Reset.
When left open, all of the input pins will be pulled
LOW via an input pulldown resistor. The Master Reset is
an asynchronous signal which, when asserted, will force
the Q outputs LOW.
The Q outputs need not be terminated for the E136 to
function properly. In fact, if these outputs will not be
used in a system, it is recommended that they be left
open to save power and minimize noise. This practice
will minimize switching noise which can reduce the
maximum count frequency of the device, or significantly
reduce margins against other noise in the system.
PIN NAMES
Pin
Function
D0–D5
Preset Data Inputs
Q0–Q5
Differential Data Outputs
S1, S2
Mode Control Pins
MR
Master Reset
CLK
Clock Input
COUT, COUT
Carry Out Output (Active LOW)
CLOUT
Look-Ahead-Carry Output
CIN
Carry-In Input (Active LOW)
CLIN
Look-Ahead-Carry Input
VCCO
VCC to Output
M9999-032006
[email protected] or (408) 955-1690
Rev.: F
1
Amendment: 0
Issue Date: March 2006
SY10E136
SY100E136
Micrel, Inc.
PACKAGE/ORDERING INFORMATION
25 24 23 22 21
D2
S2
S1
VCCO
Q4
VCCO
Q5
D5
D4
D3
Ordering Information(1)
20 19
26
18
Q3
27
17
28
16
Q2
VCC
15
VCCO
14
COUT
PLCC
TOP VIEW
J28-1
Part Number
Package
Type
Operating
Range
Package
Marking
Lead
Finish
SY10E136JC
J28-1
Commercial
SY10E136JC
Sn-Pb
SY10E136JCTR(2)
J28-1
Commercial
SY10E136JC
Sn-Pb
SY100E136JC
J28-1
Commercial
SY100E136JC
Sn-Pb
SY100E136JCTR(2)
J28-1
Commercial
SY100E136JC
Sn-Pb
J28-1
Commercial
SY10E136JC
Sn-Pb
VEE
CLK
2
CIN
3
13
COUT
SY10E136JC
CLIN
4
12
CLOUT
SY10E136JCTR(2)
J28-1
Commercial
SY10E136JC
Sn-Pb
SY100E136JC
J28-1
Commercial
SY100E136JC
Sn-Pb
SY100E136JCTR(2)
J28-1
Commercial
SY100E136JC
Sn-Pb
SY10E136JZ(3)
J28-1
Commercial
SY10E136JZ with
Matte-Sn
Pb-Free bar-line indicator
SY10E136JZTR(2, 3)
J28-1
Commercial
SY10E136JZ with
Matte-Sn
Pb-Free bar-line indicator
SY100E136JZ(3)
J28-1
Commercial
SY100E136JZ with
Matte-Sn
Pb-Free bar-line indicator
SY100E136JZTR(2, 3)
J28-1
Commercial
SY100E136JZ with
Matte-Sn
Pb-Free bar-line indicator
6
7
8
9
10 11
D1
D0
VCCO
Q0
VCCO
Q1
5
MR
1
28-Pin PLCC (J28-1)
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
M9999-032006
[email protected] or (408) 955-1690
2
SY10E136
SY100E136
Micrel, Inc.
CLOUT
COUT
QM0
QM1
QM0
DQ
S
DQ
SQ
COUT
LOGIC DIAGRAM
BLOCK
DIAGRAM(1)
DQ
RQ
Q5
D5
Q2 – Q5
BITS 2 – 4
D2 – D4
DQ
RQ
Q1
D1
DQ
RQ
Q0
MR
CLK
CLIN
CIN
S1
S2
DQ
S
D0
E136 Universal Up/Down Counter Logic Diagram
Note:
1. This diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions are achieved
internally without incurring a full gate delay.
M9999-032006
[email protected] or (408) 955-1690
3
SY10E136
SY100E136
Micrel, Inc.
LOGIC DIAGRAM
TRUTH
TABLE(1)
S1
S2
CIN
MR
CLK
Function
L
L
X
L
Z
Preset Parallel Data Inputs
L
H
L
L
Z
Increment (Count Up)
L
H
H
L
Z
Hold Count
H
L
L
L
Z
Decrement (Count Down)
H
L
H
L
Z
Hold Count
H
H
X
L
Z
Hold Count
X
X
X
H
X
Reset (Qn = LOW; COUT = HIGH)
Note:
1. Expanded truth table included on following pages.
LOGIC DIAGRAM
EXPANDED
TRUTH TABLE(1)
Function
S1
S2
MR
D5
D4
D3
D2
D1
D0
Q5
Q4
Q3
Q2
Q1
Q0 COUT CLOUT
Preset
L
L
L
X
X
Z
L
L
L
L
H
H
L
L
L
L
H
H
H
H
Down
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
L
H
H
L
H
H
Preset
L
L
L
X
X
Z
H
H
H
H
L
L
H
H
H
H
L
L
H
H
Up
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
H
L
H
H
H
H
L
H
H
H
H
Hold
H
H
H
H
L
L
X
X
X
X
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
H
L
L
H
H
H
H
Down
Hold
Down
Hold
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
H
H
L
L
L
L
L
L
L
H
H
L
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
H
L
H
H
H
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
X
L
L
H
L
H
H
L
L
X
L
L
L
L
L
H
L
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
H
L
H
H
L
H
H
H
L
H
H
H
H
H
Up
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
Reset
X
X
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
Hold
Hold
Preset
Up
Hold
Up
Hold
Hold
CIN CLIN CLK
Note:
1. Z = LOW-to-HIGH transition
M9999-032006
[email protected] or (408) 955-1690
4
SY10E136
SY100E136
Micrel, Inc.
DC
LOGIC
ELECTRICAL
DIAGRAMCHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C
Symbol
Parameter
TA = +25°C
Min. Typ. Max. Min. Typ.
IIH
Input HIGH Current
IEE
Power Supply Current
10E
100E
TA = +85°C
Max. Min. Typ.
Max.
Unit
Condition
µA
—
mA
—
—
—
150
—
—
150
—
—
150
—
—
125
125
150
150
—
—
125
125
150
150
—
—
125
140
150
170
LOGIC
AC
ELECTRICAL
DIAGRAM CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C
Symbol
Parameter
TA = +25°C
TA = +85°C
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Condition
MHz
—
ps
—
ps
—
ps
—
fCOUNT
Maximum Count Frequency
550
650
—
550
650
—
550
650
—
tPD
Propagation Delay to Output
CLK to Q
MR to Q
CLK to COUT
CLK to CLOUT
850
850
800
825
1150
1150
1150
1150
1450
1450
1300
1400
850
850
800
825
1150
1150
1150
1150
1450
1450
1300
1400
850
850
800
825
1150
1150
1150
1150
1450
1450
1300
1400
Set-up Time
S1, S2
D
CLIN
CIN
1500
800
150
800
650
400
0
400
—
—
—
—
1500
800
150
800
650
400
0
400
—
—
—
—
1500
800
150
800
650
400
0
400
—
—
—
—
Hold Time
S1, S2
D
CLIN
CIN
150
150
300
150
–200
–250
0
–250
—
—
—
—
150
150
300
150
–200
–250
0
–250
—
—
—
—
150
150
300
150
–200
–250
0
–250
—
—
—
—
tRR
Reset Recovery Time
1000
700
—
1000
700
—
1000
700
—
ps
—
tPW
Minimum Pulse Width
CLK, MR
700
400
—
700
400
—
700
400
—
ps
—
tr
tf
Rise/Fall Times
20% to 80%
COUT
Other
ps
—
tS
tH
M9999-032006
[email protected] or (408) 955-1690
275
300
—
—
600
700
275
300
5
—
—
600
700
275
300
—
—
600
700
SY10E136
SY100E136
Micrel, Inc.
LOGIC DIAGRAM
APPLICATIONS
INFORMATION
having to ripple through the entire counter chain. As a
result, past counters of this type were not widely used in
large bit counter applications.
An alternative counter architecture similar to the E016
binary counter was implemented to alleviate the need to
ripple propagate the terminal count signal. Unfortunately,
these types of counters require external gating for cascading
designs of more than two devices. In addition to requiring
additional components, these external gates limit the
cascaded count frequency to a value less than the free
running count frequency of a single counter. Although there
is a performance impact with this type of architecture, it is
minor compared to the impact of the ripple propagate
designs. As a result, the E016-type counters have been
used extensively in applications requiring very high speed,
wide bit width synchronous counters.
Several improvements have been incorporated to past
universal counter designs in the E136 universal counter.
These enhancements make the E136 the unparalleled leader
in its class. With the addition of look-ahead-carry features
on the terminal count signal, very large counter chains can
be designed which function at very nearly the same clock
frequency as a single free running device. More importantly,
these counter chains require no external gating. Figure 1
below illustrates the interconnect scheme for using the lookahead-carry features of the E136 counter.
Overview
The SY10E/100E136 are 6-bit synchronous, presettable,
cascadable universal counters. Using the S1 and S2 control
pins, the user can select between preset, count up, count
down and hold count. The Master Reset pin will reset the
internal counter and set the COUT, CLOUT and CLIN flipflops. Unlike previous 136-type counters, the carry-out
outputs will go to a high state during the preset operation.
In addition, since the carry-out outputs are registered, they
will not go low if terminal count is loaded into the register.
The look-ahead-carry-out output functions similarly.
Note from the schematic the use of the master information
from the least significant bits for control of the two carry-out
functions. This architecture not only reduces the carry-out
delay, but is essential to incorporate the registered carryout functions. In addition to being faster, the resulting carryout signals are stable and glitch free because these functions
are registered.
Cascading Multiple E136 Devices
Many applications require counters significantly larger than
the 6 bits available with the E136. For these applications,
several E136 devices can be cascaded to increase the bit
width of the counter to meet the needs of the application.
In the past, cascading several 136-type universal counters
necessarily impacted the maximum count frequency of the
resulting counter chain. This performance impact was the
result of the terminal count signal of the lower order counters
Q0 – Q5
CLOCK
Q0 – Q5
CLK
Q0 – Q5
CLK
CLK
Q0 – Q5
CLK
LSB
"LO"
CIN
"LO"
CLIN
COUT
CLOUT
MSB
"LO"
CIN
CLIN
D0 – D5
111101
COUT
CLOUT
CIN
CLIN
D0 – D5
111110
111111
CLOUT
COUT
Figure 1. 24-bit Cascaded E136 Counter
6
CLOUT
D0 – D5
CLK
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COUT
000000
CIN
COUT
CLIN
CLOUT
D0 – D5
000001
SY10E136
SY100E136
Micrel, Inc.
CIN
count status for the next occurrence of terminal count on
the LSC. This ripple propagation will not affect the count
frequency as it has 26-1 or 63 clock pulses to ripple through
without affecting the count operation of the chain.
The only limiting factor which could reduce the count
frequency of the chain as compared to a free running single
device will be the set-up time of the CLIN input. This limit
will consist of the CLK to CLOUT delay of the E136, plus the
CLIN set-up time, plus any path length differences between
the CLOUT output and the clock.
ACTIVE
LOW
CLIN
D
Q
CLK
Figure 2. Look-Ahead-Carry Input Structure
Note from the waveforms that the look-ahead-carry output
(CLOUT) pulses low one clock pulse before the counter
reaches terminal count. Also note that both CLOUT and the
carry-out pin (COUT) of the device pulse low for only one
clock period. The input structure for look-ahead-carry-in
(CLIN) and carry-in (CIN) is pictured in Figure 2.
The CLIN input is registered and then OR'ed with the CIN
input. From the truth table one can see that both the CIN
and the CLIN inputs must be in a LOW state for the E136 to
be enabled to count (either count up or count down). The
CLIN inputs are driven by the CLOUT output of the lower
order E136 and, therefore, are only asserted for a single
clock period. Since the CLIN input is registered, it must be
asserted one clock period prior to the CIN input.
If the counter previous to a given counter is at terminal
count, its COUT output, and thus the CIN input of the given
counter will be in the "LOW" state. This signals the given
counter that it will need to count one upon the next terminal
count of the least significant counter (LSC). The CLOUT
output of the LSC will pulse low one clock period before it
reaches terminal count. This CLOUT signal will be clocked
into the CLIN input of the higher order counters on the
following positive clock transition. Since both CIN and CLIN
are in the LOW state, the next clock pulse will cause the
least significant counter to roll over and all higher order
counters, if signaled by the CIN inputs, to count by one.
During the clock pulse in which the higher order counter
is counting by one, the CLIN is clocking in the high signal
presented by the CLOUT of the LSC. The CINs in the higher
order counter will ripple through the chain to update the
Programmable Divider
Using external feedback of the COUT pin, the E136 can
be configured as a programmable divider. Figure 3 illustrates
the configuration for a 6-bit count-down programmable
divider. If for some reason a count-up divider is preferred,
the COUT signal is simply fed back to S2 rather than S1.
Examination of the truth table for the E136 shows that when
both S1 and S2 are LOW, the counter will parallel load on
the next positive transition of the clock. If the S2 input is
low and the S1 input is high, the counter will be in the
count-down mode and will count towards an all zero state
upon successive clock pulses. Knowing this and the
operation of the COUT output, it becomes a trivial matter to
build programmable dividers.
For a programmable divider, one must to load a
predesignated number into the counter and count to terminal
count. Upon terminal count, the counter should automatically
reload the divide number. With the architecture shown in
Figure 3, when the counter reaches terminal count, the
COUT output, and thus the S1 input, will go LOW. This,
combined with the low on S2 will cause the counter to load
the inputs present on D0–D5. Upon loading the divide value
into the counter, COUT will go HIGH as the counter is no
longer at terminal count, thereby placing the counter back
into the count mode.
Q0 – Q5
S0
CLOCK
CLK
"LO"
S1
COUT
COUT
D0 – D5
Figure 3. 6-bit Programmable Divider
M9999-032006
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Divide
Ratio
D5
D4
2
3
4
5
*
*
36
37
38
*
*
62
63
64
L
L
L
L
*
*
H
H
H
*
*
H
H
H
L
L
L
L
*
*
L
L
L
*
*
H
H
H
Preset Data Inputs
D3
D2
L
L
L
L
*
*
L
L
L
*
*
H
H
H
L
L
L
H
*
*
L
H
H
*
*
H
H
H
D1
D0
L
H
H
L
*
*
H
L
L
*
*
L
H
H
H
L
H
L
*
*
H
L
H
*
*
H
L
H
Table 1. Preset Inputs Versus Divide Ratio
7
SY10E136
SY100E136
Micrel, Inc.
LOAD
100100
100011
000011
000010
000001
000000
LOAD
CLOCK
S1
COUT
DIVIDE BY 37
Figure 4. Programmable Divider Waveforms
The exercise of building a programmable divider then
becomes simply determining what value to load into the
counter to accomplish the desired division. Since the load
operation requires a clock pulse, to divide by N, N-1 must
be loaded into the counter. A single E136 device is capable
of divide ratios of 2 to 64, inclusive. Table 1 outlines the
load values for the various divide ratios. Figure 4 presents
the waveforms resulting from a divide by 37 operation. Note
that the availability of the COUT complimentary output (COUT)
allows the user to choose the polarity of the divide by output.
For single device programmable counters, the E016
counter is probably a better choice than the E136. The
E016 has an internal feedback to control the reloading of
the counter. This not only simplifies board design, but also
will result in a faster maximum count frequency.
For programmable dividers of larger than 8 bits, the
Q0 – Q5
Q0 – Q5
CLOCK
S1
CLK
benefits of the E016 diminishes and, in fact, for very wide
dividers, the E136 will provide the capability of a faster
count frequency. Figure 5 shows the architecture of a 24bit programmable divider implemented using E136 counters.
Note the need for one external gate to control the loading of
the entire counter chain. An ideal device for the external
gating of this architecture would be the 4-input OR function
in the 8-lead SOIC ECLinPS Lite™ family. However, the
final decision as to what device to use for external gating
requires a balancing of performance needs, cost and
available board space. Note that because of the need for
external gating, the maximum count frequency of a given
sized programmable divider will be less than that of a single
cascaded counter.
Q0 – Q5
S1
CLK
Q0 – Q5
S1
CLK
S1
CLK
MSB
LSB
"LO"
"LO"
"LO"
CIN
COUT
CIN
COUT
CIN
COUT
CIN
COUT
CLIN
CLOUT
CLIN
CLOUT
CLIN
CLOUT
CLIN
CLOUT
D0 – D5
D0 – D5
D0 – D5
Figure 5. 24-bit Programmable Divider Architecture
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D0 – D5
SY10E136
SY100E136
Micrel, Inc.
28-PIN PLCC (J28-1)
Rev. 03
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The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
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Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
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© 2006 Micrel, Incorporated.
M9999-032006
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