ONSEMI MTD6N15T4

MTD6N15
Power Field Effect
Transistor DPAK
for Surface Mount
N−Channel Enhancement−Mode Silicon
Gate
This TMOS Power FET is designed for high speed, low loss power
switching applications such as switching regulators, converters,
solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds
• Low RDS(on) — 0.3 Ω Max
• Rugged — SOA is Power Dissipation Limited
• Source−to−Drain Diode Characterized for Use With
Inductive Loads
• Low Drive Requirement — VGS(th) = 4.0 V Max
• Surface Mount Package on 16 mm Tape
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V(BR)DSS
RDS(on) MAX
ID MAX
150 V
0.3 6.0 A
N−CHANNEL
D
G
S
4
4
MAXIMUM RATINGS
Value
Unit
Drain−Source Voltage
VDSS
150
Vdc
Drain−Gate Voltage (RGS = 1.0 MΩ)
VDGR
150
Vdc
Gate−Source Voltage — Continuous
Gate−Source Voltage — Non−Repetitive
(tp ≤ 50 µs)
VGS
VGSM
± 20
± 40
Vdc
Vpk
ID
IDM
6.0
20
Adc
Total Power Dissipation @ TC = 25°C
Derate above 25°C
PD
20
0.16
Watts
W/°C
Total Power Dissipation @ TA = 25°C
Derate above 25°C (Note 1)
PD
1.25
0.01
Watts
W/°C
Total Power Dissipation @ TA = 25°C (1)
Derate above 25°C (Note 2)
PD
1.75
0.014
Watts
W/°C
Operating and Storage Junction Temperature Range
TJ, Tstg
−65 to
+150
°C
Drain Current — Continuous
Drain Current — Pulsed
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
− Junction to Case
− Junction to Ambient (Note 1)
− Junction to Ambient (Note 2)
Symbol
Value
Unit
RθJC
RθJA
RθJA
6.25
100
71.4
°C/W
1 2
3
1
3
CASE 369D
DPAK
(Straight Lead)
STYLE 2
CASE 369C
DPAK
(Surface Mount)
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENTS
4 Drain
4 Drain
1
Gate
6N15
Y
WW
2
Drain
3
Source
= Device Code
= Year
= Work Week
3
Source
1
Gate
2
Drain
ORDERING INFORMATION
Package
Shipping†
DPAK
75 Units/Rail
MTD6N15−1
DPAK
Straight Lead
75 Units/Rail
MTD6N15T4
DPAK
2500 Tape & Reel
Device
MTD6N15
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
2. When surface mounted to an FR4 board using 0.5 sq. in. drain pad size.
2
YWW
T
6N15
Symbol
YWW
T
6N15
Rating
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
 Semiconductor Components Industries, LLC, 2004
March, 2004 − Rev. 2
1
Publication Order Number:
MTD6N15/D
MTD6N15
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Max
Unit
V(BR)DSS
150
—
Vdc
—
—
10
100
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Zero Gate Voltage Drain Current
(VDS = Rated VDSS, VGS = 0 Vdc)
TJ = 125°C
µAdc
IDSS
Gate−Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0)
IGSSF
—
100
nAdc
Gate−Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0)
IGSSR
—
100
nAdc
Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc)
TJ = 100°C
VGS(th)
2.0
1.5
4.5
4.0
Vdc
Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 3.0 Adc)
RDS(on)
—
0.3
Ohm
Drain−Source On−Voltage (VGS = 10 Vdc)
(ID = 6.0 Adc)
(ID = 3.0 Adc, TJ = 100°C)
VDS(on)
—
—
1.8
1.5
gFS
2.5
—
mhos
Ciss
—
1200
pF
Coss
—
500
Crss
—
120
td(on)
—
50
tr
—
180
td(off)
—
200
ON CHARACTERISTICS (Note 3)
Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc)
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz))
S Fi
See
Figure 11
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS* (TJ = 100°C)
Turn−On Delay Time
(VDD = 25 Vdc, ID = 3.0 Adc,
RG = 50 Ω)
See Figures 13 and 14
Rise Time
Turn−Off Delay Time
Fall Time
Total Gate Charge
(VDS = 0.8 Rated VDSS,
ID = Rated ID, VGS = 10 Vdc))
S Figure
See
Fi
12
Gate−Source Charge
Gate−Drain Charge
tf
—
100
Qg
15 (Typ)
30
Qgs
8.0 (Typ)
—
Qgd
7.0 (Typ)
—
VSD
1.3 (Typ)
2.0
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS*
Forward On−Voltage
(IS = 6.0
6 0 Adc,
Ad di/dt = 25 A/µs
A/
VGS = 0 Vdc,)
Forward Turn−On Time
ton
Reverse Recovery Time
trr
325 (Typ)
PD, POWER DISSIPATION (WATTS)
3. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
2.5
25
2
20
1.5
15
1
10
0.5
5
0
0
TA
TC
TC
25
50
75
100
T, TEMPERATURE (°C)
Figure 1. Power Derating
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2
125
Vdc
Limited by stray inductance
150
—
ns
MTD6N15
TYPICAL ELECTRICAL CHARACTERISTICS
I D , DRAIN CURRENT (AMPS)
10 V
VGS(th) , GATE THRESHOLD VOLTAGE (VOLTS)
24
9V
20
TJ = 25°C
16
8V
12
8
7V
4
6V
5V
0
0
10
20
30
40
50
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
60
3.6
2.8
2.4
2
− 50
TJ = 25°C
I D , DRAIN CURRENT (AMPS)
VDS = 10 V
12
10
8
6
4
100°C
− 55°C
2
0
4
6
8
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
10
1.6
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0.20
TJ = 100°C
25°C
0.15
− 55°C
0.10
0.05
0
0
4
8
12
16
ID, DRAIN CURRENT (AMPS)
VGS = 0 V
ID = 0.25 mA
1.2
0.8
0.4
0
− 50
0
50
100
150
TJ, JUNCTION TEMPERATURE (°C)
200
Figure 5. Breakdown Voltage Variation
With Temperature
0.30
0.25
150
2
Figure 4. Transfer Characteristics
VGS = 10 V
0
50
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Gate−Threshold Voltage Variation
With Temperature
V(BR)DSS , DRAIN−TO−SOURCE BREAKDOWN VOLTAGE
(NORMALIZED)
Figure 2. On−Region Characteristics
14
VDS = VGS
ID = 1 mA
3.2
2
1.6
1.2
0.8
0.4
0
− 50
20
VGS = 10 V
ID = 3 A
Figure 6. On−Resistance versus Drain Current
0
50
100
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. On−Resistance Variation
With Temperature
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3
200
MTD6N15
SAFE OPERATING AREA
20
100 µs
10 µs
10
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
20
1 ms
5
2
10 ms
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.5
0.2
0.1
dc
15
TJ ≤ 150°C
10
5
TC = 25°C
VGS = 20 V SINGLE PULSE
0.05
0.03
0.3 0.5 0.7 1
2 3 5 7 10
20 30 50 70 100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0
200 300
0
20
Figure 8. Maximum Rated Forward Biased
Safe Operating Area
40
60
80
100
120
140
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
160
Figure 9. Maximum Rated Switching
Safe Operating Area
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 9 is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, IDM and the breakdown voltage, V(BR)DSS.
The switching SOA shown in Figure 8 is applicable for both
turn−on and turn−off of the devices for switching times less
than one microsecond.
The power averaged over a complete switching cycle
must be less than:
FORWARD BIASED SAFE OPERATING AREA
r(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE (NORMALIZED)
The FBSOA curves define the maximum drain−to−source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned
on. Because these curves include the limitations of
simultaneous high voltage and high current, up to the rating
of the device, they are especially useful to designers of linear
systems. The curves are based on a case temperature of 25°C
and a maximum junction temperature of 150°C. Limitations
for repetitive pulses at various case temperatures can be
determined by using the thermal response curves. Motorola
Application Note, AN569, “Transient Thermal
Resistance−General Data and Its Use” provides detailed
instructions.
0.7
0.5
D = 0.5
0.3
0.2
TJ(max) − TC
RθJC
0.2
0.1
P(pk)
0.1 0.05
0.07
0.02
0.05
0.03
0.02
0.01
0.01
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.02 0.03
0.05
0.1
0.2 0.3
0.5
1
2 3
5
10
t, TIME OR PULSE WIDTH (ms)
Figure 10. Thermal Response
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4
20
RθJC(t) = r(t) RθJC
RθJC(t) = 6.25°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RθJC(t)
50
100
200
500
1000
MTD6N15
2000
TJ = 25°C
VGS = 0
1600
C, CAPACITANCE (pF)
VGS, GATE SOURCE VOLTAGE (VOLTS)
16
1200
800
400
0
15
Ciss
VDS = 0
10
5
0
VGS
5
10
15
Coss
Crss
25
30
20
TJ = 25°C
ID = 6 A
12
75 V
VDS = 50 V
8
4
0
35
120 V
0
4
VDS
8
12
Qg, TOTAL GATE CHARGE (nC)
16
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Capacitance Variation
Figure 12. Gate Charge versus
Gate−To−Source Voltage
RESISTIVE SWITCHING
VDD
ton
td(on)
RL
Vout
Vin
PULSE GENERATOR
Rgen
50 Ω
tr
td(off)
tf
90%
OUTPUT, Vout
INVERTED
DUT
z = 50 Ω
toff
90%
10%
90%
50 Ω
INPUT, Vin
50%
50%
10%
PULSE WIDTH
Figure 13. Switching Test Circuit
Figure 14. Switching Waveforms
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5
20
MTD6N15
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE O
−T−
SEATING
PLANE
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
4
Z
A
S
1
2
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
E
R
3
U
K
F
J
L
H
D
G
2 PL
0.13 (0.005)
M
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
0.180 0.215
0.025 0.040
0.020
−−−
0.035 0.050
0.155
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
T
SOLDERING FOOTPRINT*
6.20
0.244
3.0
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
SCALE 3:1
mm inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.57
5.45
0.63
1.01
0.51
−−−
0.89
1.27
3.93
−−−
MTD6N15
PACKAGE DIMENSIONS
DPAK
CASE 369D−01
ISSUE O
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
H
D
G
3 PL
0.13 (0.005)
M
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
T
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7
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
MTD6N15
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Phone: 81−3−5773−3850
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8
For additional information, please contact your
local Sales Representative.
MTD6N15/D