NTD32N06L Power MOSFET 32 Amps, 60 Volts, Logic Level N−Channel DPAK Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. http://onsemi.com Features • • • • • Smaller Package than MTB30N06VL Lower RDS(on), VDS(on), and Total Gate Charge Lower and Tighter VSD Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge VDSS RDS(ON) TYP ID MAX 60 V 23.7 m 32 A N−Channel D Typical Applications Power Supplies Converters Power Motor Controls Bridge Circuits G S 4 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) 4 Drain Symbol Value Unit Drain−to−Source Voltage VDSS 60 Vdc 3 Drain−to−Gate Voltage (RGS = 10 M) VDGR 60 Vdc VGS VGS 20 30 DPAK CASE 369C (Surface Mount) Style 2 Gate−to−Source Voltage − Continuous − Non−Repetitive (tp10 ms) Drain Current − Continuous @ TA = 25°C − Continuous @ TA = 100°C − Single Pulse (tp10 s) Total Power Dissipation @ TA = 25°C Derate above 25°C Total Power Dissipation @ TA = 25°C (Note 1) Total Power Dissipation @ TA = 25°C (Note 2) ID ID IDM PD Vdc 32 22 90 Adc 93.75 0.625 2.88 1.5 W W/°C W W TJ, Tstg −55 to +175 °C Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (Note 3) (VDD = 50 Vdc, VGS = 5 Vdc, L = 1.0 mH, IL(pk) = 25 A, VDS = 60 Vdc, RG = 25 ) EAS 313 mJ Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds °C/W RJC RJA RJA 1.6 52 100 TL 260 April, 2004 − Rev. 3 4 Drain 1 2 3 DPAK CASE 369D (Straight Lead) Style 2 32N06L Y WW 1 2 3 Gate Drain Source Device Code = Year = Work Week ORDERING INFORMATION Package Shipping† DPAK 75 Units/Rail NTD32N06L−1 DPAK Straight Lead 75 Units/Rail NTD32N06LT4 DPAK 2500/Tape & Reel Device °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to FR4 board using 0.5″ pad size. 2. When surface mounted to FR4 board using minimum recommended pad size. 3. Repetitive rating; pulse width limited by maximum junction temperature. Semiconductor Components Industries, LLC, 2004 2 1 3 Drain Gate Source 4 Apk Operating and Storage Temperature Range Thermal Resistance − Junction−to−Case − Junction−to−Ambient (Note 1) − Junction−to−Ambient (Note 2) 1 2 YWW 32N06L Rating MARKING DIAGRAMS YWW 32N06L • • • • 1 NTD32N06L †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: NTD32N06L/D NTD32N06L ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 − 70 62 − − − − − − 1.0 10 − − ±100 1.0 − 1.7 4.8 2.0 − − 23.7 28 − − − 0.48 0.78 0.61 0.67 − − gFS − 27 − mhos pF OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Note 4) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C Adc nAdc ON CHARACTERISTICS (Note 4) Gate Threshold Voltage (Note 4) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 4) (VGS = 5 Vdc, ID = 16 Adc) RDS(on) Static Drain−to−Source On−Resistance (Note 4) (VGS = 5 Vdc, ID = 20 Adc) (VGS = 5 Vdc, ID = 32 Adc) (VGS = 5 Vdc, ID = 16 Adc, TJ = 150°C) VDS(on) Forward Transconductance (Note 4) (VDS = 6 Vdc, ID = 16 Adc) Vdc mV/°C m Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Transfer Capacitance Ciss − 1214 1700 Coss − 343 480 Crss − 87 180 td(on) − 12.8 30 SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 30 Vdc, ID = 32 Adc, VGS = 5 Vdc, Vdc RG = 9.1 )) ((Note 4)) Fall Time Gate Charge (VDS = 48 Vdc, ID = 32 Adc, VGS = 5 Vdc) (Note 4) ns tr − 221 450 td(off) − 37 80 tf − 128 260 QT − 23 50 Q1 − 4.5 − Q2 − 14 − VSD − − − 0.89 0.95 0.74 1.0 − − Vdc trr − 56 − ns ta − 31 − tb − 25 − QRR − 0.093 − nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 4) (IS = 32 Adc, VGS = 0 Vdc) (Note 4) (IS = 20 Adc, VGS = 0 Vdc, TJ = 150°C) Reverse Recovery Time (IS = 32 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 4) Reverse Recovery Stored Charge 4. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2%. 5. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 C NTD32N06L 60 60 VDS > = 10 V VGS = 4.5 V 50 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) VGS = 10 V VGS = 5 V VGS = 4 V 40 VGS = 6 V 30 VGS = 3.5 V 20 VGS = 8 V VGS = 3 V 10 50 40 30 20 TJ = 25°C 10 TJ = 100°C 0 1 3 2 4 2.6 3 3.4 3.8 4.2 4.6 Figure 2. Transfer Characteristics 0.034 TJ = 100°C 0.03 TJ = 25°C 0.026 0.022 TJ = −55°C 0.018 0.014 0 10 20 30 40 50 60 RDS(on), DRAIN−TO−SOURCE RESISTANCE () Figure 1. On−Region Characteristics 0.038 5 0.042 VGS = 10 V 0.038 0.034 0.03 0.026 TJ = 100°C 0.022 TJ = 25°C 0.018 TJ = −55°C 0.014 0.01 0 10 20 30 40 50 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Drain Current Figure 4. On−Resistance vs. Drain Current 60 10000 1.8 VGS = 0 V ID = 16 A VGS = 5 V TJ = 150°C IDSS, LEAKAGE (nA) 1.6 2.2 TJ = −55°C VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) VGS = 5 V 0.01 0 1.8 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.042 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE () 0 1.4 1.2 1 1000 TJ = 125°C 100 TJ = 100°C 0.8 0.6 −50 −25 10 0 25 50 75 100 125 150 175 0 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 60 4000 3600 3200 C, CAPACITANCE (pF) VGS = 0 V VDS = 0 V TJ = 25°C Ciss 2800 2400 Crss 2000 Ciss 1600 1200 800 Coss 400 Crss 0 10 5 VGS 0 VDS 5 10 15 25 20 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) NTD32N06L 4 3 2 1 ID = 32 A TJ = 25°C 0 0 4 8 12 16 20 Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge 24 32 IS, SOURCE CURRENT (AMPS) t, TIME (ns) VGS Q2 Q1 Qg, TOTAL GATE CHARGE (nC) VDS = 30 V ID = 32 A VGS = 5 V tr tf 100 td(off) td(on) 1 10 24 20 16 12 8 4 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 0.96 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current RDS(on) Limit Thermal Limit Package Limit 100 dc 10 10 ms 1 ms 100 s 1 Mounted on 3″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with one die operating,10 s max 1 10 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) RG, GATE RESISTANCE () VGS = 20 V SINGLE PULSE TC = 25°C 0.1 0.1 VGS = 0 V TJ = 25°C 28 0 0.6 100 1000 ID, DRAIN CURRENT (AMPS) QT 5 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1000 10 6 350 ID = 32 A 300 250 200 150 100 50 0 25 50 75 100 125 150 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 4 175 NTD32N06L EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 10 Normalized to RJC at Steady State 1 r(t), 0.1 0.01 0.00001 0.0001 0.001 0.01 0.1 1 10 t, TIME (s) Figure 13. Thermal Response EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED) 10 Normalized to RJA at Steady State, 1″ square Cu Pad, Cu Area 1.127 in2, 3 x 3 inch FR4 board 1 r(t), 0.1 0.01 0.00001 0.0001 0.001 0.01 0.1 1 t, TIME (s) Figure 14. Thermal Response http://onsemi.com 5 10 100 1000 NTD32N06L PACKAGE DIMENSIONS DPAK−3 CASE 369C−01 ISSUE O SEATING PLANE −T− C B V E R 4 Z A S 1 2 DIM A B C D E F G H J K L R S U V Z 3 U K F J L H D G 2 PL 0.13 (0.005) M T INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 −−− 0.035 0.050 0.155 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT 6.20 0.244 3.0 0.118 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 SCALE 3:1 http://onsemi.com 6 mm inches MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 −−− 0.89 1.27 3.93 −−− NTD32N06L PACKAGE DIMENSIONS C B V DPAK−3 CASE 369D−01 ISSUE B E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F H D G NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN T http://onsemi.com 7 MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− NTD32N06L ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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