VISHAY SI4511DY_09

Si4511DY
Vishay Siliconix
N- and P-Channel 20-V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
N-Channel
20
P-Channel
- 20
RDS(on) (Ω)
ID (A)
0.0145 at VGS = 10 V
9.6
0.017 at VGS = 4.5 V
8.6
0.033 at VGS = - 4.5 V
- 6.2
0.050 at VGS = - 2.5 V
-5
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• Compliant to RoHS directive 2002/95/EC
APPLICATIONS
• Level Shift
• Load Switch
SO-8
S1
1
8
D1
G1
2
7
D1
S2
3
6
D2
G2
4
5
D2
D1
S2
G2
G1
Top View
Ordering Information: Si4511DY-T1-E3 (Lead (Pb)-free)
Si4511DY-T1-GE3 (Lead (Pb)-free and Halogen-free)
D2
S1
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Symbol
VDS
VGS
Drain-Source Voltage
Gate-Source Voltage
TA = 25 °C
TA = 70 °C
Continuous Drain Current (TJ = 150 °C)a, b
Pulsed Drain Current
a
Continuous Source Current (Diode Conduction)
TA = 25 °C
Maximum Power Dissipationa
TA = 70 °C
Operating Junction and Storage Temperature Range
ID
IDM
IS
PD
TJ, Tstg
10 s
9.6
7.7
1.7
2
1.3
N-Channel
P-Channel
Steady State
10 s
Steady State
20
- 20
± 16
± 12
7.2
- 6.2
- 4.6
5.8
- 4.9
- 3.7
40
- 40
0.9
- 1.7
- 0.9
1.1
2
1.1
0.7
1.3
0.7
- 55 to 150
Unit
V
A
W
°C
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambienta
Maximum Junction-to-Foot (Drain)
Symbol
t ≤ 10 s
Steady State
Steady State
RthJA
RthJF
N-Channel
Typ.
Max.
50
62.5
85
110
30
40
P-Channel
Typ.
Max.
50
62.5
90
110
30
35
Unit
°C/W
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
b. t ≤ 10 s.
Document Number: 72223
S09-0867-Rev. E, 18-May-09
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Si4511DY
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward Transconductanceb
Diode Forward Voltagb
VGS(th)
IGSS
IDSS
ID(on)
RDS(on)
gfs
VDS = VGS, ID = 250 µA
N-Ch
0.6
1.8
VDS = VGS, ID = - 250 µA
P-Ch
- 0.6
- 1.4
VDS = 0 V, VGS = ± 16 V
N-Ch
± 100
VDS = 0 V, VGS = ± 12 V
P-Ch
± 100
VDS = 20 V, VGS = 0 V
N-Ch
1
VDS = - 20 V, VGS = 0 V
P-Ch
-1
VDS = 20 V, VGS = 0 V, TJ = 55 °C
N-Ch
5
VDS = - 20 V, VGS = 0 V, TJ = 55 °C
P-Ch
-5
VDS = 5 V, VGS = 10 V
N-Ch
40
VDS = - 5 V, VGS = - 4.5 V
P-Ch
- 40
VGS = 10 V, ID = 9.6 A
N-Ch
0.0115
VGS = - 4.5 V, ID = - 6.2 A
P-Ch
0.022
0.033
VGS = 4.5 V, ID = 8.6 A
N-Ch
0.0135
0.017
VGS = - 2.5 V, ID = - 5 A
P-Ch
0.035
0.050
VDS = 15 V, ID = 9.6 A
N-Ch
33
VDS = - 15 V, ID = - 6.2 A
P-Ch
17
IS = 1.7 A, VGS = 0 V
N-Ch
0.8
1.2
IS = - 1.7 A, VGS = 0 V
P-Ch
- 0.8
- 1.2
N-Ch
11.5
18
P-Ch
17
20
N-Ch
3.7
P-Ch
4.1
VSD
V
nA
µA
A
0.0145
Ω
S
V
Dynamica
Total Gate Charge
Gate-Source Charge
Qg
Qgs
Gate-Drain Charge
Qgd
Turn-On Delay Time
td(on)
Rise Time
Turn-Off Delay Time
Fall Time
Source-Drain Reverse Recovery Time
N-Channel
VDS = 10 V, VGS = 4.5 V, ID = 9.6 A
tr
td(off)
tf
trr
P-Channel
VDS = - 10 V, VGS = - 4.5 V, ID = - 6.2 A
N-Channel
VDD = 10 V, RL = 10 Ω
ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω
nC
N-Ch
3.3
P-Ch
4.3
N-Ch
12
P-Ch
25
40
N-Ch
12
20
20
P-Ch
30
45
N-Ch
55
85
P-Ch
70
105
N-Ch
15
25
P-Ch
50
75
IF = 1.7 A, dI/dt = 100 A/µs
N-Ch
50
100
IF = - 1.7 A, dI/dt = 100 A/µs
P-Ch
40
80
P-Channel
VDD = - 10 V, RL = 10 Ω
ID ≅ - 1 A, VGEN = - 4.5 V, Rg = 6 Ω
ns
Notes:
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 72223
S09-0867-Rev. E, 18-May-09
Si4511DY
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
40
40
VGS = 10 V thru 4 V
3V
32
ID - Drain Current (A)
ID - Drain Current (A)
32
24
16
8
24
16
TC = 125 °C
8
25 °C
2V
0
0.00
0.25
0.50
0.75
1.00
1.25
1.50
- 55 °C
0
0.0
1.75
0.5
VDS - Drain-to-Source Voltage (V)
1.5
2.0
2.5
3.0
3.5
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.020
2000
1600
0.015
VGS = 4.5 V
C - Capacitance (pF)
RDS(on) - On-Resistance ( Ω )
1.0
VGS = 10 V
0.010
Ciss
1200
800
Coss
0.005
Crss
400
0.000
0
0
8
16
24
32
40
0
4
ID - Drain Current (A)
8
16
20
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
Capacitance
10
1.6
VDS = 10 V
ID = 9.6 A
8
1.4
R DS(on) - On-Resistance
(Normalized)
VGS - Gate-to-Source Voltage (V)
12
6
4
2
VGS = 10 V
ID = 9.6 A
1.2
1.0
0.8
0
0
3
6
9
12
15
18
Qg - Total Gate Charge (nC)
Gate Charge
Document Number: 72223
S09-0867-Rev. E, 18-May-09
21
24
0.6
- 50
- 25
0
25
50
75
100
125
150
TJ - Junction Temperature (°C)
On-Resistance vs. Junction Temperature
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Si4511DY
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.05
RDS(on) - On-Resistance ( )
IS - Source Current (A)
40
10
TJ = 150 °C
TJ = 25 °C
0.04
ID = 9.6 A
0.03
ID = 3 A
0.02
0.01
0.00
1
0.00
0.2
0.4
0.6
0.8
1.0
0
1.2
1
4
5
On-Resistance vs. Gate-to-Source Voltage
0.4
30
ID = 250 µA
0.2
25
20
0.0
Power (W)
V GS(th) Variance (V)
3
VGS - Gate-to-Source Voltage (V)
VSD - Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
- 0.2
15
- 0.4
10
- 0.6
5
- 0.8
- 50
2
- 25
0
25
50
75
100
125
0
10-2
150
10-1
TJ - Temperature (°C)
1
10
100
600
Time (s)
Threshold Voltage
Single Pulse Power
100
IDM Limited
Limited by RDS(on)*
P(t) = 0.0001
ID - Drain Current (A)
10
P(t) = 0.001
1
P(t) = 0.01
ID(on)
Limited
P(t) = 0.1
0.1
P(t) = 1
P(t) = 10
TC = 25 °C
Single Pulse
DC
BVDSS Limited
0.01
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
* VDS > minimum VGS at which RDS(on) is specified
Safe Operating Area
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Document Number: 72223
S09-0867-Rev. E, 18-May-09
Si4511DY
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
0.05
t1
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = RthJA = 85 °C
3. TJM − TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10 -4
10 -3
10 -2
10 -1
1
Square Wave Pulse Duration (s)
10
100
600
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10 -4
10 -3
10 -2
10 -1
Square Wave Pulse Duration (s)
1
10
Normalized Thermal Transient Impedance, Junction-to-Foot
Document Number: 72223
S09-0867-Rev. E, 18-May-09
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Si4511DY
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
40
40
TC = - 55 °C
3V
VGS = 5 V thru 3.5 V
25 °C
32
24
ID - Drain Current (A)
ID - Drain Current (A)
32
2.5 V
16
2V
8
125 °C
24
16
8
1.5 V
0
0.0
0.4
0.8
1.2
1.6
0
0.0
2.0
0.5
1.0
VDS - Drain-to-Source Voltage (V)
2.0
2.5
3.0
3.5
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
3000
0.10
2500
0.08
C - Capacitance (pF)
R DS(on) - On-Resistance (Ω)
1.5
0.06
VGS = 2.5 V
0.04
Ciss
2000
1500
1000
VGS = 4.5 V
0.02
Coss
500
Crss
0
0.00
0
8
16
24
32
0
40
4
8
16
20
VDS - Drain-to-Source Voltage (V)
ID - Drain Current (A)
On-Resistance vs. Drain Current
Capacitance
1.6
5
VGS = 4.5 V
ID = 6.2 A
VDS = 10 V
ID = 6.2 A
1.4
4
R DS(on) - On-Resistance
(Normalized)
VGS - Gate-to-Source Voltage (V)
12
3
2
1.2
1.0
0.8
1
0
0
3
6
9
12
Qg - Total Gate Charge (nC)
Gate Charge
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6
15
18
0.6
- 50
- 25
0
25
50
75
100
125
150
TJ - Junction Temperature (°C)
On-Resistance vs. Junction Temperature
Document Number: 72223
S09-0867-Rev. E, 18-May-09
Si4511DY
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.10
R DS(on) - On-Resistance (Ω)
I S - Source Current (A)
40
TJ = 150 °C
10
TJ = 25 °C
0.08
0.06
ID = 6.2 A
0.04
0.02
0.00
1
0.0
0.3
0.6
0.9
1.2
1.5
0
1
3
4
5
On-Resistance vs. Gate-to-Source Voltage
Source-Drain Diode Forward Voltage
0.6
30
25
0.4
20
ID = 250 µA
0.2
Power (W)
V GS(th) Variance (V)
2
VGS - Gate-to-Source Voltage (V)
VSD - Source-to-Drain Voltage (V)
0.0
15
10
- 0.2
5
- 0.4
- 50
- 25
0
25
50
75
100
125
0
10 -2
150
10 -1
1
10
TJ - Temperature (°C)
Time (s)
Threshold Voltage
Single Pulse Power
100
600
100
IDM Limited
Limited by RDS(on)*
ID - Drain Current (A)
10
P(t) = 0.001
P(t) = 0.01
1
0.1
ID(on)
Limited
P(t) = 0.1
P(t) = 1
TC = 25 °C
Single Pulse
P(t) = 10
DC
BVDSS Limited
0.01
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
* VDS > minimum VGS at which RDS(on) is specified
Safe Operating Area
Document Number: 72223
S09-0867-Rev. E, 18-May-09
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Si4511DY
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
0.05
t1
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = RthJA = 85 °C
3. TJM − TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10 -4
10 -3
10 -2
10 -1
1
Square Wave Pulse Duration (s)
10
100
600
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10 -4
10 -3
10 -2
10 -1
Square Wave Pulse Duration (s)
1
10
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?72223.
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8
Document Number: 72223
S09-0867-Rev. E, 18-May-09
Package Information
Vishay Siliconix
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
8
6
7
5
E
1
3
2
H
4
S
h x 45
D
C
0.25 mm (Gage Plane)
A
e
B
All Leads
q
A1
L
0.004"
MILLIMETERS
INCHES
DIM
Min
Max
Min
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.20
0.004
0.008
B
0.35
0.51
0.014
0.020
C
0.19
0.25
0.0075
0.010
D
4.80
5.00
0.189
0.196
E
3.80
4.00
0.150
e
0.101 mm
1.27 BSC
0.157
0.050 BSC
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.50
0.93
0.020
0.037
q
0°
8°
0°
8°
S
0.44
0.64
0.018
0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
Document Number: 71192
11-Sep-06
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VISHAY SILICONIX
TrenchFET® Power MOSFETs
Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
0.288
7.3
0.050
1.27
0.196
5.0
0.027
0.69
0.078
1.98
0.2
5.07
Figure 1. Single MOSFET SO-8 Pad
Pattern With Copper Spreading
Document Number: 70740
Revision: 18-Jun-07
0.050
1.27
0.088
2.25
0.088
2.25
0.027
0.69
0.078
1.98
0.2
5.07
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
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APPLICATION NOTE
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a single MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
0.288
7.3
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-8
0.172
(4.369)
0.028
0.022
0.050
(0.559)
(1.270)
0.152
(3.861)
0.047
(1.194)
0.246
(6.248)
(0.711)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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22
Document Number: 72606
Revision: 21-Jan-08
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Vishay
Disclaimer
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including but not limited to the warranty expressed therein.
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Document Number: 91000
Revision: 11-Mar-11
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