128M DDR SDRAM K4D28163HD 128Mbit DDR SDRAM 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM Revision 1.4 August 2002 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev. 1.4(Aug. 2002) 128M DDR SDRAM K4D28163HD Revision History Revision 1.4 (August 13, 2002) • Changed ICC3P • Typo corrected • Changed refresh period of K4D28163HD-TC36/40 from 4K/64ms to 4K/32ms. Revision 1.3 (May 29, 2002) • Added K4D28163HD-TC36 (275MHz) Revision 1.2 (May 8, 2002) • Typo corrected Revision 1.1 (January 7, 2002) • Increased Icc2N by 20mA Revision 1.0 (December 22, 2001) • Defined DC spec. Revision 0.4 (December 10, 2001) - Target Spec • Removed Full page Burst Length from the spec. Revision 0.3 (November 6, 2001) - Target Spec • Removed K4D28163HD-TC45/55 from the spec. Revision 0.2 (October 25, 2001) - Target Spec • Removed K4D28163HD-TC33/36 from the spec. Revision 0.1 (October 12, 2001) - Target Spec • Changed V DD from 3.3V + 10% to 3.3V + 5% Revision 0.0 (October 10, 2001) - Target Spec • Defined Target Specification - 2 - Rev. 1.4(Aug. 2002) 128M DDR SDRAM K4D28163HD 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL FEATURES • 3.3V + 5% power supply for device operation • 2 DQS’s ( 1DQS / Byte ) • 2.5V + 5% power supply for I/O interface • Data I/O transactions on both edges of Data strobe • SSTL_2 compatible inputs/outputs • DLL aligns DQ and DQS transitions with Clock transition • 4 banks operation • Edge aligned data & data strobe output • MRS cycle with address key programs • Center aligned data & data strobe input -. Read latency 3 (clock) • DM for write masking only -. Burst length (2, 4 and 8) • Auto & Self refresh -. Burst type (sequential & interleave) • 32ms refresh period (4K cycle) for -36/-40 • All inputs except data & DM are sampled at the positive going edge of the system clock • 64ms refresh period (4K cycle) for -50/-60 • 66pin TSOP-II • Differential clock input • Maximum clock frequency up to 275MHz • No Wrtie-Interrupted by Read Function • Maximum data rate up to 550Mbps/pin ORDERING INFORMATION Part NO. Max Freq. Max Data Rate K4D28163HD-TC36 275MHz 550Mbps/pin K4D28163HD-TC40 250MHz 500Mbps/pin K4D28163HD-TC50 200MHz 400Mbps/pin K4D28163HD-TC60 166MHz 333Mbps/pin Interface Package SSTL_2 66pin TSOP-II GENERAL DESCRIPTION FOR 2M x 16Bit x 4 Bank DDR SDRAM The K4D28163HD is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2.097,152 words by 16 bits, fabricated with SAMSUNG ’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 1.1GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. - 3 - Rev. 1.4(Aug. 2002) 128M DDR SDRAM K4D28163HD PIN CONFIGURATION (Top View) V DD 1 66 VS S DQ 0 2 65 DQ 1 5 VD D Q 3 64 VS S Q DQ 1 4 63 DQ 1 4 DQ 2 5 62 DQ 1 3 VS S Q 6 61 V DDQ DQ 3 7 60 DQ 1 2 DQ 4 8 59 DQ 1 1 VD D Q 9 58 VS S Q DQ 5 10 57 DQ 1 0 DQ 6 11 56 DQ 9 VS S Q 12 55 V DDQ DQ 7 13 54 DQ 8 NC 14 53 NC VD D Q 15 52 VS S Q LDQS 16 51 UDQS NC 17 50 NC V DD 18 49 VR E F NC 19 48 VS S LDM 20 47 UDM WE 21 46 CK CAS 22 45 CK RAS 23 44 CKE CS 24 43 NC NC 25 42 NC BA 0 26 41 A1 1 BA 1 27 40 A9 AP/A1 0 28 39 A8 A0 29 38 A7 A1 30 37 A6 A2 31 36 A5 A3 32 35 A4 V DD 33 34 VS S 66 PIN TSOP(II) (400mil x 875mil) (0.65 mm Pin Pitch) PIN DESCRIPTION CK,CK Differential Clock Input BA 0 , BA 1 Bank Select Address CKE Clock Enable A 0 ~A 11 Address Input CS Chip Select D Q0 ~ DQ1 5 Data Input/Output RAS Row Address Strobe V DD Power CAS Column Address Strobe VS S Ground WE Write Enable V DDQ Power for DQ’s LDQS,UDQS Data Strobe V SSQ Ground for DQ’s LDM,UDM Data Mask NC No Connection RFU Reserved for Future Use - 4 - Rev. 1.4(Aug. 2002) 128M DDR SDRAM K4D28163HD INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Function The differential system clock Input. CK, CK*1 Input CKE Input All of the inputs are sampled on the rising edge of the clock except D Q’s and DM ’s that are sampled on both edges of the DQS. Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS enables the command decoder when low and disabled the com- CS Input mand decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS Input CAS Input WE Input Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Input/Output Data input and output are synchronized with both edge of DQS. For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15. Input Data in Mask. Data In is masked by DM Latency=0 when DM is high in burst write. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15. Input/Output Data inputs/Outputs are multiplexed on the same pins. BA 0, BA 1 Input Selects which bank is to be active. A 0 ~ A 11 Input Row/Column addresses are multiplexed on the same pins. Row addresses : RA 0 ~ RA 1 1, Column addresses : CA 0 ~ CA8. V DD/V SS Power Supply Power and ground for the input buffers and core logic. V DDQ/V SSQ Power Supply Isolated power supply and ground for the output buffers to provide improved noise immunity. V REF Power Supply Reference voltage for inputs, used for SSTL interface. No connection/ Reserved for future use This pin is recommended to be left "No connection" on the device LDQS,(U)DQS LDM,UDM DQ 0 ~ DQ 15 NC/RFU *1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply V REF to CK pin. - 5 - Rev. 1.4(Aug. 2002) 128M DDR SDRAM K4D28163HD BLOCK DIAGRAM (2Mbit x 16I/O x 4 Bank) 16 Intput Buffer I/O Control CK, CK Data Input Register LWE LDMi Serial to parallel Bank Select 2Mx16 16 Output Buffer 2Mx16 32 2-bit prefetch S ense AMP Row Decoder Refresh Counter Row Buffer ADDR Address Register CK,CK 2Mx16 x16 DQi 2Mx16 Column Decoder Col. Buffer LCBR LRAS Latency & Burst Length Strobe G en. Programming Register DLL LCKE LRAS LCBR Data Strobe LWE LCAS LWCBR CK,CK LDMi Timing Register CK,CK CKE CS RAS CAS WE - 6 - LDM UDM Rev. 1.4(Aug. 2002) 128M DDR SDRAM K4D28163HD FUNCTIONAL DESCRIPTION • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high . 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. * 1,2 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6&7 is regardless of the order. Power up & Initialization Sequence 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ~ precharge ALL Banks EMRS MRS DLL Reset precharge 1st Auto ALL Banks Refresh ~ ~ tRP tRFC t RFC 200 Clock min. Inputs must be stable for 200us - 7 - 2nd Auto Refresh ~ ~ ~ ~ 2 Clock min. 2 Clock min. Mode Register Set Any Command ~ ~ 2 Clock min. ~ ~ ~ t RP Command ~ ~ CK,CK Rev. 1.4(Aug. 2002) 128M DDR SDRAM K4D28163HD MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE (The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A 0 ~ A 1 1 and BA 0, BA 1 in the same cycle as CS, RAS, CAS and W E going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A 3, CAS latency(read latency from column address) uses A 4 ~ A 6. A 7 is used for test mode. A 8 is used for DLL reset. A 7, A 8, BA 0 and BA 1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA 1 BA 0 RFU 0 A1 1 A1 0 A9 RFU DLL A8 A8 A7 DLL TM A6 A5 A3 CAS Latency A2 BT A1 A0 Burst Length Address Bus Mode Register Burst Type Test Mode DLL Reset A4 A7 mode A3 Type 0 No 0 Normal 0 Sequential 1 Yes 1 Test 1 Interleave Burst Length CAS Latency BA 0 An ~ A0 A6 A5 A4 MRS 0 0 0 Reserved 1 EMRS 0 0 1 Reserved 0 1 0 Reserved 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 A1 A0 Sequential Interleave 0 0 0 Reserve Reserve 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserve Reserve 1 0 1 Reserve Reserve 1 1 0 Reserve Reserve 1 1 1 Reserve Reserve Latency 0 * RFU(Reserved for future use) should stay "0" during MRS cycle. Burst Type A2 1 Reserved MRS Cycle 0 1 2 3 4 5 6 7 8 CK, CK Command NOP Precharge All Banks NOP NOP MRS tRP NOP Any Command NOP NOP tMRD=2 t CK *1 : MRS can be issued only at all banks precharge state. *2 : Minimum t RP is required to issue MRS command. - 8 - Rev. 1.4(Aug. 2002) 128M DDR SDRAM K4D28163HD EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BA 1 BA 0 RFU 1 A1 1 A1 0 A9 A8 A7 RFU A6 A5 A4 D.I.C BA 0 An ~ A0 A6 A1 0 MRS 0 1 1 EMRS 1 A3 A2 RFU Output Driver Impedence Control 1 A1 A0 D.I.C DLL A0 Address Bus Extended Mode Register DLL Enable Weak 0 Enable Matched 1 Disable *1 : RFU(Reserved for future use) should stay "0" during EMRS cycle. - 9 - Rev. 1.4(Aug. 2002) 128M DDR SDRAM K4D28163HD ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit V IN, V OUT -0.5 ~ 3.6 V Voltage on V DD supply relative to Vss V DD -1.0 ~ 3.6 V Voltage on V DD supply relative to Vss V DDQ -0.5 ~ 3.6 V Storage temperature T STG -55 ~ +150 °C Power dissipation PD 1.0 W Short circuit current IOS 50 mA Voltage on any pin relative to Vss Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to V SS=0V, T A =0 to 65°C) Parameter Symbol Min Typ Max Unit Note Device Supply voltage V DD 3.135 3.3 3.465 V 1 Output Supply voltage V DDQ 2.375 2.50 2.625 V 1 Reference voltage V REF 0.49*V DDQ - 0.51*V DDQ V 2 Vtt V REF-0.04 V REF V REF+0.04 V 3 Input logic high voltage V IH(DC) V REF+0.15 - V DDQ +0.30 V 4 Input logic low voltage V IL(DC) -0.30 - V REF-0.15 V 5 Output logic high voltage VO H Vtt+0.76 - - V IO H=-15.2mA Output logic low voltage V OL - - Vtt-0.76 V IOL =+15.2mA Input leakage current IIL -5 - 5 uA 6 Output leakage current IOL -5 - 5 uA 6 Termination voltage Note : 1. Under all conditions V DDQ must be less than or equal to V DD . 2. V REF is expected to equal 0.50*V DDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the V REF may not exceed + 2% of the DC value. Thus, from 0.50*V DDQ, VREF is allowed + 25mV for DC error and an additional + 25mV for AC noise. 3. V tt of the transmitting device must track V REF of the receiving device. 4. V I H(max.)= V DDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 5. V IL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V < V IN < V DD is acceptable. For all other pins that are not under test V I N=0V. - 10 - Rev. 1.4(Aug. 2002) 128M DDR SDRAM K4D28163HD DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, T A =0 to 65° C) Version Parameter Symbol Test Condition -36 -40 -50 -60 200 190 170 165 Unit Note mA 1 Operating Current (One Bank Active) ICC1 Burst Lenth=2 t RC ≥ tRC(min) IOL =0mA, tCC= tCC(min) Precharge Standby Current in Power-down mode ICC2 P CKE ≤ V IL (max), t CC= t CC(min) Precharge Standby Current in Non Power-down mode ICC2 N CKE ≥ V I H(min), CS ≥ V I H(min), tCC= tCC(min) 70 65 60 60 mA Active Standby Current power-down mode ICC3 P CKE ≤ V IL(max), tCC= tCC(min) 100 90 75 70 mA Active Standby Current in in Non Power-down mode ICC3 N CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC (min) 130 120 110 90 mA 380 350 310 280 mA 250 220 210 200 mA 5 tRC ≥ tRFC(min) tRC ≥ tRFC(min) Operating Current ( Burst Mode) ICC4 Refresh Current ICC5 tRC ≥ tRFC(min) Self Refresh Current ICC6 CKE ≤ 0.2V Page Burst, All Banks activated. mA 2 mA Note : 1. Measured with outputs open. AC INPUT OPERATING CONDITIONS Recommended operating conditions(Voltage referenced to V SS =0V, V DD=3.3V+ 5%, V DDQ=2.5V+ 5%,T A=0 to 65°C) Parameter Symbol Min Typ Max Unit Input High (Logic 1) Voltage; DQ V IH V REF +0.35 Input Low (Logic 0) Voltage; DQ V IL - Clock Input Differential Voltage; CK and CK V ID Clock Input Crossing Point Voltage; CK and CK V IX Note - - V - V REF -0.35 V 0.7 - V DDQ+0.6 V 1 0.5*VDDQ-0.2 - 0.5*V DDQ +0.2 V 2 Note : 1. V I D is the magnitude of the difference between the input level on CK and the input level on CK 2. The value of V IX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same - 11 - Rev. 1.4(Aug. 2002) 128M DDR SDRAM K4D28163HD AC OPERATING TEST CONDITIONS (V DD =3.3V±5%, T A = 0 to 65 °C) Parameter Value Unit Input reference voltage for CK(for single ended) 0.50*V DDQ V 1.5 V CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels(V IH /V IL) 1.0 V/ns V REF +0.35/V REF -0.35 V V REF V V tt V Input timing measurement reference level Output timing measurement reference level Output load condition Note See Fig.1 V tt =0.5*V DDQ R T=50Ω Output Z0=50Ω V REF =0.5*VDDQ C LOAD =30pF (Fig. 1) Output Load Circuit CAPACITANCE (V DD =3.3V, T A = 25°C, f=1MHz) Symbol Min Max Unit Input capacitance( CK, CK ) Parameter C IN1 1.0 5.0 pF Input capacitance(A 0 ~A11 , BA0 ~BA1 ) C IN2 1.0 4.0 pF Input capacitance ( CKE, CS, RAS,CAS, WE ) C IN3 1.0 4.0 pF Data & DQS input/output capacitance(DQ 0~ D Q31) C OUT 1.0 6.5 pF Input capacitance(DM0 ~ DM3) C IN4 1.0 6.5 pF DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. Symbol Value Unit Decoupling Capacitance between V DD and V SS Parameter C DC1 0.1 + 0.01 uF Decoupling Capacitance between V DDQ and V SSQ C DC2 0.1 + 0.01 uF Note : 1. V DD and V DDQ pins are separated each other. All V DD pins are connected in chip. All VDDQ pins are connected in chip. 2. V SS and V SSQ pins are separated each other All V SS pins are connected in chip. All V SSQ pins are connected in chip. - 12 - Rev. 1.4(Aug. 2002) 128M DDR SDRAM K4D28163HD AC CHARACTERISTICS Symbol Parameter CK cycle time CL=3 CK high level width CK low level width DQS out access time from CK Output access time from CK Data strobe edge to Dout edge Read preamble Read postamble tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL tIS tI H tDS tDH -36 Min -40 Max Min -50 Max Min -60 Max Min Max Unit Note 3.6 6 4.0 7 5.0 10 6.0 10 ns 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK -0.6 0.6 -0.6 0.6 -0.7 0.7 -0.75 0.75 ns -0.6 0.6 -0.6 0.6 -0.7 0.7 -0.75 0.75 ns - 0.4 - 0.4 - 0.45 - 0.5 ns 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK 1 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0.85 1.15 0.85 1.15 0.8 1.2 0.75 1.25 tCK 0 - 0 - 0 - 0 - ns 0.35 - 0.35 - 0.3 - 0.25 - tCK 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0.9 - 0.9 - 1.0 - 1.1 - ns 0.9 - 0.9 - 1.0 - 1.1 - ns 0.4 - 0.4 - 0.45 - 0.5 - ns 0.4 - 0.4 - 0.45 - 0.5 - ns tHP tCLmin or tCHmin - tCLmin or tCHmin - tCLmin or tCHmin - tCLmin or tCHmin - ns 1 Data output hold time from DQS tQ H tHP-0.4 - tHP-0.4 - tHP-0.45 - tHP-0.5 - ns 1 CK to valid DQS-in DQS-In setup time DQS-in hold time DQS write postamble DQS-In high level width DQS-In low level width Address and Control input setup Address and Control input hold DQ and DM setup time to DQS DQ and DM hold time to DQS Clock half period Note 1 : - The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55% - A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax - 13 - Rev. 1.4(Aug. 2002) 128M DDR SDRAM K4D28163HD AC CHARACTERISTICS (I) Parameter Symbol -36 -40 -50 -60 Unit Note Min Max Min Max Min Max Min Max tRC tRFC tRAS tRCD tRP tRRD 15 - 14 - 12 - 10 - 17 - 16 - 14 - 12 - 10 100K 9 100K 8 100K 7 100K 5 - 5 - 4 - 3 - tCK tCK 5 - 5 - 4 - 3 - tCK 2 - 2 - 2 - 2 - tCK tWR 3 - 3 - 2 - 2 - tCK 1 tWR_A 3 - 3 - 3 - 3 - tCK 1 tCDLR tCCD tMRD 2 - 2 - 2 - 2 - - 1 - 1 - 1 - tCK tCK 1 1 2 - 2 - 2 - 2 - tCK Auto precharge write recovery + Precharge Exit self refresh to read com- tDAL 8 - 8 - 7 - 6 - tCK Power down exit time tPDEX tREF Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active Last data in to Row precharge @Normal Precharge Last data in to Row precharge @Auto Precharge Last data in to Read command Col. address to Col. address Mode register set cycle time Refresh interval time tXSR tCK tCK 200 - 200 - 200 - 200 - tCK 1tCK+tIS - 1tCK+tIS - 1tCK+tIS - 1tCK+tIS - ns 7.8 - 7.8 - 15.6 - 15.6 - us Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM AC CHARACTERISTICS (II) (Unit : Number of Clock) K4D28163HD-TC36 Frequency Cas Latency 275MHz ( 3.6ns ) 3 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3 tRC 15 14 12 10 tRFC 17 16 14 12 tRAS 10 9 8 7 tRCD 5 5 4 3 tRP 5 5 4 3 tRRD 2 2 2 2 tDAL 8 8 7 6 Unit K4D28163HD-TC40 Frequency Cas Latency 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3 tRC 14 12 10 tRFC 16 14 12 tRAS 9 8 7 tRCD 5 4 3 tRP 5 4 3 tRRD 2 2 2 tDAL 8 7 6 Unit K4D28163HD-TC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3 tRC 12 10 tRFC 14 12 tRAS 8 7 tRCD 4 3 tRP 4 3 tRRD 2 2 tDAL 7 6 Unit - 14 - tCK tCK tCK tCK tCK tCK tCK tCK tCK Rev. 1.4(Aug. 2002) 128M DDR SDRAM K4D28163HD K4D28163HD-TC60 Frequency Cas Latency 166MHz ( 6.0ns ) 3 tRC 10 tRFC 12 tRAS 7 tRCD 3 tRP 3 tRRD 2 tDAL 6 Unit tCK Simplified Timing @ BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 BAa BAb BAa BAb Ra Rb Ra Rb Ca Cb 17 18 19 20 21 22 CK, CK B A [ 1 : 0 ] BAa A10/AP ADDR (A0~A11) BAa BAa Ra Ra Ra Ca WE DQS Da0 Da1 Da2 Da3 DQ Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 DM COMMAND ACTIVEA WRITEA PRECH ACTIVEA ACTIVEB WRITEA WRITEB tRCD tRAS tRP tRC Normal Write Burst (@ BL=4) tRRD Multi Bank Interleaving Write Burst (@ BL=4) - 15 - Rev. 1.4(Aug. 2002) 128M DDR SDRAM K4D28163HD PACKAGE DIMENSIONS (66pin TSOP-II) 0.65TYP 0.65± 0.08 0.30±0.08 (10× ) NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS ’Y OUT QUALITY - 16 - (10.76) 0.075 MAX ] (0.50) 5) (R 0 (4 .2 ×) 1.20MAX 1.00± 0.10 0.10 MAX [ (R 0 .2 (R (0.71) 0.05 MIN 0.210± 0.05 (10× ) 5) 0. 15 ) 0.665± 0.05 22.22± 0.10 (R 0 .1 0.125 +0.075 -0.035 5) (0.80) #33 (1.50) (10×) 0.45~0.75 (1.50) (10 × ) #1 11.76± 0.20 (0.80) #34 10.16± 0.10 #66 (0.50) Units : Millimeters 0.25TYP 0×~8× Rev. 1.4(Aug. 2002)