PRELIMINARY K6T1008C2C Family CMOS SRAM Document Title 128K x8 bit Low Power CMOS Static RAM Revision History History Draft Date Remark 0.0 Initial draft November 22, 1995 Design target 0.1 First revision - Seperate read and write at ICC, ICC1 ICC = ICC1 → Read : 15mA, Write : 35mA April 15, 1996 Preliminary 1.0 Finalized - Add 70ns speed bin for commercial product and 85ns speed bin for industrial. September 5, 1996 Final 2.0 Revised - Improved operating current Add typical value. ICC Read : 15mA → 10mA(Remove write current) ICC2 : 90mA → 60mA - Speed bin change Remove 45ns from commercial part Remove 55ns and 100ns from industrial part. November 5, 1997 Final Revision No. The attached data sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 2.0 November 1997 PRELIMINARY K6T1008C2C Family CMOS SRAM 128K x8 bit Low Power CMOS Static RAM FEATURES GENERAL DESCRIPTION • Process Technology: TFT • Organization: 128K x8 • Power Supply Voltage: 4.5~5.5V • Low Data Retention Voltage: 2V(Min) • Three state output and TTL Compatible • Package Type: 32-DIP-600, 32-SOP-525, 32-TSOP1-0820F/R The K6T1008C2C families are fabricated by SAMSUNG′s advanced CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The families also support low data retention voltage for battery backup operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature K6T1008C2C-L Vcc Range Speed Commercial(0~70°C) K6T1008C2C-B Standby (ISB1, Max) 55/70ns 50µA 10µA 70ns 50µA 15µA 60mA Industrial(-40~85°C) K6T1008C2C-F 24 A11 A9 A8 VCC A13 WE A15 CS2 CS2 A15 VCC WE N.C A13 A16 A14 A8 A12 A9 A7 A6 A11 A5 OE A4 10 23 A10 A1 11 22 CS1 16 17 A0 12 21 I/O8 15 18 I/O1 13 20 I/O7 14 19 13 20 12 21 11 22 N.C 1 32 A16 2 31 A14 3 30 A12 4 29 A7 5 28 A6 6 27 A5 7 26 A4 8 A3 9 A2 25 I/O2 14 19 I/O3 15 18 VSS 16 17 A4 A5 A6 A7 I/O6 A12 I/O5 A14 A16 I/O4 N.C VCC A15 CS2 WE A13 A8 A9 A11 32-SOP 32-TSOP1-F/R FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION 32-DIP 32-SOP 32-DIP, 32-SOP 32-TSOP1-F/R 4.5~5.5V K6T1008C2C-P PKG Type Operating (ICC2, Max) 1 32 2 31 3 30 4 29 5 28 6 27 26 7 8 9 10 32-TSOP Type1 - Forward 25 24 23 11 22 12 21 13 20 14 19 15 18 16 17 Clk gen. OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 Precharge circuit. VCC VSS A4 A5 A6 A7 A8 A12 Row select Memory array 1024 rows 128×8 columns Data cont Column select A13 A14 A15 A16 10 9 8 7 23 32-TSOP Type1 - Reverse 24 25 26 6 27 5 28 4 29 3 30 2 31 1 32 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS1 A10 OE I/O1 I/O8 I/O Circuit Data cont A0 A1 A2 A3 A9 A10 A11 CS1 CS2 Name Function Name CS1,CS2 Chip Select Inputs I/O 1~I/O8 Function Control logic OE Data Inputs/Outputs OE Output Enable Vcc Power WE Write Enable Input Vss Ground Address Inputs N.C No Connection A0~A16 WE SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 2.0 November 1997 PRELIMINARY K6T1008C2C Family CMOS SRAM PRODUCT LIST Commercial Temperature Products(0~70°C) Part Name Industrial Temperature Products(-40~85°C) Function K6T1008C2C-DL55 K6T1008C2C-DL70 K6T1008C2C-DB55 K6T1008C2C-DB70 32-DIP, 55ns, L-pwr 32-DIP, 70ns, L-pwr 32-DIP, 55ns, LL-pwr 32-DIP, 70ns, LL-pwr K6T1008C2C-GL55 K6T1008C2C-GL70 K6T1008C2C-GB55 K6T1008C2C-GB70 32-SOP, 55ns, L-pwr 32-SOP, 70ns, L-pwr 32-SOP, 55ns, LL-pwr 32-SOP, 70ns, LL-pwr K6T1008C2C-TB55 K6T1008C2C-TB70 32-TSOP1-F, 55ns, LL-pwr 32-TSOP1-F, 70ns, LL-pwr K6T1008C2C-RB55 K6T1008C2C-RB70 32-TSOP1-R, 55ns, LL-pwr 32-TSOP1-R, 70ns, LL-pwr Part Name Function K6T1008C2C-GP70 K6T1008C2C-GF70 32-SOP, 70ns, L-pwr 32-SOP, 70ns, LL-pwr K6T1008C2C-TF70 K6T1008C2C-RF70 32-TSOP1-F, 70ns, LL-pwr 32-TSOP1-R, 70ns, LL-pwr FUNCTIONAL DESCRIPTION CS 1 CS2 OE WE I/O Pin Mode Power H X1) X1) X1) High-Z Deselected Standby X1) L X1) X1) High-Z Deselected Standby L H H H High-Z Output Disable Active L H L H Dout Read Active L H X1) L Din Write Active 1. X means don′t care(Must be in high or low status.) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Symbol Ratings Unit Remark VIN, VOUT -0.5 to 7.0 V - Voltage on Vcc supply relative to Vss VCC -0.5 to 7.0 V - Power Dissipation PD 1.0 W - TSTG -65 to 150 °C - 0 to 70 °C K6T1008C2C-L -40 to 85 °C K6T1008C2C-P 260°C, 10sec (Lead Only) - - Storage temperature Operating Temperature Soldering temperature and time TA TSOLDER 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 2.0 November 1997 PRELIMINARY K6T1008C2C Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Item Symbol Min Typ Max Unit Supply voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 Input high voltage VIH 2.2 - Vcc+0.5 Input low voltage VIL -0.53) - 0.8 V V 2) V Note 1. Commercial Product : TA=0 to 70°C and Industrial Product :TA=-40 to 85°C, otherwise specified. 2. Overshoot : Vcc+3.0V for≤30ns pulse width. 3. Undershoot : -3.0V for≤30ns pulse width. 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25°C) Symbol Test Condition Min Max Unit Input capacitance Item CIN VIN=0V - 6 pF Input/Output capacitance CIO VIO=0V - 8 pF 1. Capacitance is sampled not, 100% tested. DC AND OPERATING CHARACTERISTICS Item Min Typ Max Unit ILI VIN=Vss to Vcc -1 - 1 µA Output leakage current ILO CS1=VIH or CS 2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 µA Operating power supply current ICC IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL, Read - 5 10 mA ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS 1≤0.2V, CS2≥VCC-0.2V, V IN≤0.2V or VIN≥VCC-0.2V Input leakage current Average operating current Symbol Test Conditions Read - Write 2 5 20 35 mA ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL or VIH - 45 60 mA Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.4 - - V Standby Current(TTL) ISB CS1=VIH, CS2=VIL, Other input=VIL or VIH - - 3 mA ISB1 CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or CS 2≤0.2V Other input =0~Vcc K6T1008C2C-L Standby Current (CMOS) K6T1008C2C-B K6T1008C2C-P K6T1008C2C-F 4 Low Power - 1 50 Low Low Power - 0.3 10 Low power - 1 50 Low Low Power - 0.3 15 µA Revision 2.0 November 1997 PRELIMINARY K6T1008C2C Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level : 0.8 to 2.4V Input rising and falling time : 5ns Input and output reference voltage : 1.5V Output load (See right) :CL=100pF+1TTL CL1) 1. Including scope and jig capacitance AC CHARACTERISTICS Speed Bins Parameter List Symbol 55ns Min Write Max Min Max Read cycle time tRC 55 - 70 - ns Address access time tAA - 55 - 70 ns Chip select to output tCO1, tCO2 - 55 - 70 ns tOE - 25 - 35 ns Chip select to low-Z output tLZ 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - ns Chip disable to high-Z output tHZ 0 20 0 25 ns Output disable to high-Z output tOHZ 0 20 0 25 ns Output hold from address change tOH 10 - 10 - ns Write cycle time tWC 55 - 70 - ns Chip select to end of write tCW 45 - 60 - ns Output enable to valid output Read Units 70ns Address set-up time tAS 0 - 0 - ns Address valid to end of write tAW 45 - 60 - ns tWP 40 - 50 - ns tWR1,tWR2 0 - 0 - ns Write pulse width Write recovery time Write to output high-Z tWHZ 0 20 0 25 ns Data to write time overlap tDW 25 - 30 - ns Data hold from write time tDH 0 - 0 - ns End write to output low-Z tOW 5 - 5 - ns Typ Max Unit V DATA RETENTION CHARACTERISTICS Item Vcc for data retention Data retention current Symbol VDR IDR Test Condition Min CS ≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V 2.0 - 5.5 K6T1008C2C-L - 1 20 K6T1008C2C-B - 1 10 K6T1008C2C-P - - 25 11) Vcc=3.0V, CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V K6T1008C2C-F Data retention set-up tSDR Recovery time tRDR See data retention waveform - - 10 0 - - 5 - - µA ms 1. CS1≥Vcc-0.2v, CS2 ≥Vcc-0.2V or CS2 ≤0.2V 5 Revision 2.0 November 1997 PRELIMINARY K6T1008C2C Family CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, WE=VIH) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO1 CS 1 tHZ(1,2) CS 2 tCO2 tOE OE Data out High-Z tOLZ tLZ tOHZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 2.0 November 1997 PRELIMINARY K6T1008C2C Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS1 tAW CS2 tCW(2) tWP(1) WE tAS(3) tDW tDH Data Valid Data in tWHZ Data out tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS1 tAW CS2 tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z 7 Revision 2.0 November 1997 PRELIMINARY K6T1008C2C Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS 1 tAW CS 2 tCW(2) tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap of a low CS1, a high CS 2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the begining of write to the end of write. 2. t CW is measured from the CS1 going low or CS2 going high to the end of write. 3. t AS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2) applied in case a write ends as CS2 going to low. DATA RETENTION WAVE FORM CS1 controlled VCC tSDR Data Retention Mode tRDR 4.5V 2.2V VDR CS1≥VCC-0.2V CS1 GND CS2 controlled Data Retention Mode VCC 4.5V CS2 tSDR tRDR VDR CS 2≤0.2V 0.4V GND 8 Revision 2.0 November 1997 PRELIMINARY K6T1008C2C Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeter(inch) 32 DUAL INLINE PACKAGE (600mil) 0.25 +0.10 -0.05 0.010+0.004 -0.002 #17 15.24 0.600 #32 13.60±0.20 0.535±0.008 #16 #1 0~15° 3.81±0.20 0.150±0.008 42.31 1.666 MAX 5.08 0.200 MAX 41.91±0.20 1.650±0.008 3.30±0.30 0.130±0.012 0.46±0.10 0.018±0.004 1.52±0.10 0.060±0.004 ( 1.91 ) 0.075 2.54 0.100 0.38 MIN 0.015 32 PLASTIC SMALL OUTLINE PACKAGE (525mil) 0~8° #17 14.12±0.30 0.556±0.012 #1 #16 2.74±0.20 0.108±0.008 3.00 0.118 MAX 20.87 MAX 0.822 20.47±0.20 0.806±0.008 11.43±0.20 0.450±0.008 +0.10 0.20 -0.05 0.008+0.004 -0.002 13.34 0.525 #32 0.80±0.20 0.031±0.008 0.10 MAX 0.004 MAX ( 0.71 ) 0.028 +0.100 -0.050 +0.004 0.016 -0.002 0.41 1.27 0.050 0.05 0.002 MIN 9 Revision 2.0 November 1997 PRELIMINARY K6T1008C2C Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeter(inch) 32 THIN SMALL OUTLINE PACKAGE TYPE1 (0820F) 0.20 +0.10 -0.05 0.008+0.004 -0.002 20.00±0.20 0.787±0.008 #1 #32 8.40 0.331 MAX 0.50 0.0197 #17 #16 0.25 0.010 TYP 0.25 ) 0.010 8.00 0.315 ( 1.00±0.10 0.039±0.004 1.20 0.047 MAX 18.40±0.10 0.724±0.004 +0.10 -0.05 0.006+0.004 -0.002 0.05 0.002 MIN 0~8° 0.45 ~0.75 0.018 ~0.030 ( 0.10 MAX 0.004 0.15 0.50 ) 0.020 32 THIN SMALL OUTLINE PACKAGE TYPE1 (0820R) 0.20 +0.10 -0.05 0.008+0.004 -0.002 20.00±0.20 0.787±0.008 #16 #17 0.50 0.0197 #1 0.25 ) 0.010 8.00 0.315 8.40 0.331 MAX ( #32 1.00±0.10 0.039±0.004 0.05 0.002 MIN 1.20 0.047 MAX 18.40±0.10 0.724±0.004 +0.10 -0.05 0.006 +0.004 -0.002 0.15 0~8° 0.45 ~0.75 0.018 ~0.030 ( 10 0.10 MAX 0.004 0.25 0.010 TYP 0.50 ) 0.020 Revision 2.0 November 1997