MARCH. 1998 DATA SHEET KB2511B DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2511B DEFLECTION PROCESSOR 32-SDIP-400 The KB2511B is a monolithc integrated circuit assembled in 32 pins shrunk dual in line plastic package. This IC controls all the functions related to the horizontal and vertical deflection in multimodes or multi-frequency computer display monitors. The internal sync processor, combined with the very powerful geometry correction block make the KB2511 suitable for very high performance monitors with very few external components. The horizontal jitter level is very low. It is particularly well suited for high-end 15” and 17” monitors. FUNCTIONS • Defiection Processor • I2C BUS Control ORDERING INFORMATION Device Package Operating Temperature KB2511B 32-SDIP 0 °C ~ 70 °C • B+ Regulator • Vertical Parabola Generator • Horizontal and Vertical dynamic focus FEATURES (HORIZONTAL) • Self-adaptative • Dual PLL concept • 150kHz maximum frequency • Horizontal Dynamic Phase (Side Pin balance & parallelogram) • Horizontal and vertical dynamic focus (Horizontal Focus Amplitude, Horizontal Focus Symmetry, Vertical Focus Amplitude) • X-RAY protection input • I2C controls : Horizontal duty-cycle, H-position,free running frequency, frequency generator for burn-in mode. (VERTICAL) (GENERAL) • Sync Processor • 12V supply voltage • Vertical ramp generator • 50 to 165Hz AGC loop • Geometry tracking with V-POS & AMP • I2C Controls : V-AMP, V-POS, S-CORR, C-CORR (I2C GEOMETRY CORRECTIONS) • Vertical parabola generator (Pincushion-E/W, Keystone) • Hor. & Vert, lock/unlock outputs • Read/Write I2C interface • Vertical moire • B+ Regulator -Internal PWM generator for B+ current mode step-up converter. - Switchable to step-down converter - I2C adjustable B+ reference voltage - Output pulses synchronized on horizontal frequency 1 KB2511B DEFLECTION PROCESSOR FOR MULTISYNC MONITORS HREF HGND 13 VREF 11 HLOCKOUT R0 C0 HFLY PLL2C HOUT 7 H POSITION PLL1F BLOCK DIAGRAM 8 3 6 5 12 4 26 PHASE/ FREQUENCY COMPARATOR H-PHASE(7 bits) LOCK/UNLOCK IDENTIFICATION VSYNC IN 1 2 29 XRAY 25 VGND 21 SYNC INPUT SELECT (1bit) X + Spin Bal 6 bits 2 Key Bal 6 bits Amp & symmetry 2x5 bits MOIRE CANCEL 5 BITS+ON/OFF V REF B+ CONTROLLER 2 X GEOMETRY TRACKING 19 32 XRAY B+ ADJUST 7 bits SYNC PROCESSOR 6 bits 5V Vcc SAFETY PROCESSOR Free running 5 bits HOUT BUFFER + VAMP 6 bits 8 bits RESET GENERATOR VAMP 7 bits X SDA SCL 31 30 S AND C CORRECTION VERTICAL OSCILLATOR RAMP GENERATOR 2 I 2 C INTERFACE PCC 7 bits + keyst 6 bits X + 2 27 22 20 18 23 24 VACCAP BREATH VOUT EWOUT VPOS 7bits VCAP GND 14 COMP 28 B+ OUT 15 REGIN 16 ISENSE 17 BGND 9 HFOCUS CAP 10 FOCUS 2 VREF Forced Freq. 2 bits H-DUTY (5 bits) X VCC PHASE SHIFTER VSYNC H/HVIN PHASE COMPARATOR VCO DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2511B PIN CONFIGURATIONS H/HVIN 5V 32 2 VSYNCIN SDA 31 3 HLOCKOUT SCL 30 4 PLL2C VCC 29 5 C0 BOUT 28 6 R0 GND 27 7 PLL1F HOUT 26 8 HPOSITION XRAY 25 9 HFOCUSCAP EWOUT 24 10 FOCUSOUT VOUT 23 11 HGND VCAP 22 12 HFLY VREF 21 13 HREF VAGCCAP 20 14 COMP VGND 19 15 REGIN BREATH 18 16 ISENSE KB2511B 1 B+GND 17 3 KB2511B DEFLECTION PROCESSOR FOR MULTISYNC MONITORS PIN DESCRIPTION Table 1. Pin Description 4 No Pin Name Description 1 H/HVIN 2 VSYNCIN TTL compatible vertical sync input (for separated H&V) 3 HLOCKOUT First PLL lock/unlock output (0V unlocked - 5V locked) 4 PLL2C 5 C0 Horizontal oscillator capacitor 6 R0 Horizontal oscillator resistor 7 PLL1F 8 HPOSITION 9 HFOCUSCAP 10 FOCUSOUT 11 HGND Horizontal Section Ground 12 HFLY Horizontal Flyback Input (positive polarity) 13 HREF Horizontal Section Reference Voltage (to be filtered) 14 COMP B+ error amplifier output for frequency compensation and gain setting 15 REGIN Regulation input of B+ control loop 16 ISENSE Sensing of external B+ switching transistor current or switch for step-down converter 17 B+GND Ground (related to B+ reference adjustment) 18 BREATH DC breathing input control(Compensation of vertical amplitude against EHV variation) 19 VGND 20 VAGCCAP 21 VREF Vertical section reference voltage (to be filtered) 22 VCAP Vertical sawtooth generator capacitor 23 VOUT Vertical ramp output (with frequency independant amplitude and S or C corrections if any). It is mixed with vertical position voltage and vertical moire. 24 EWOUT 25 XRAY X-RAY protection input (with internal latch function) 26 HOUT Horizontal drive output (internal transistor, open collector) 27 GND General ground (referenced to Vcc) 28 BOUT B+ PWM regulator output 29 Vcc Supply voltage (12V typ) 30 SCL I2C clock input 31 SDA I2C data input 32 5V TTL compatible horizontal sync input(Separate or composite) Second PLL loop filter First PLL loop filter Horizontal position filter(Capacitor to be connected to HGND) Horizontal dynamic focus oscillator capacitor Mixed horizontal and vertical dynamic focus output Vertical section ground Memory capacitor for automatic gain control loop in vertical ramp generator Pincushion-East/West correction parabola output Supply voltage (5V typ) DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2511B REFERENCE DATA Table 2. Reference Data Parameter Value Unit Horizontal frequency 15 to 150 kHz Autosynch frequency (for given R0 and C0) 1 to 4.5FO FH ± Horizontal sync polarity input YES Polarity detection (on both horizontal and vertical section) YES TTL Composite synch YES Lock/Unlock identification (on both horizontal 1st PLL and vertical section) YES I2C control for H-Position ±10 XRay protection YES I2C horizontal duty cycle adjust I2C free running frequency adjustment % 30 to 60 % 0.8 to 1.3FO FH Stand-by function YES Dual polarity H-Drive outputs NO Supply voltage monitoring YES PLL1 inhibition possibility NO Blanking output NO Vertical frequency 35 to 200 Hz Vertical autosync (for 150nF on Pin22 and 470nF on Pin20) 50 to 165 Hz Vertical S-Correction YES Vertical C-Correction YES Vertical amplitude adjustment YES DC breathing control on Vertical amplitude YES East/West parabola output(also known as Pin cushion output) YES East/West correction amplitude adjustment YES Keystone adjustment YES Internal dynamic horizontal phase control YES Side pin balance amplitude adjustment YES Parallelogram adjustment YES Tracking of geometric corrections with vertical amplitude and position YES 5 KB2511B DEFLECTION PROCESSOR FOR MULTISYNC MONITORS Table 2. Reference Data (Continued) Parameter 6 Value Reference voltage (both on horizontal and vertical) YES Dynamic focus (both on horizontal and vertical) YES I2C horizontal dynamic focus amplitude adjustment YES I2C horizontal dynamic focus symmetry adjustment YES I2C vertical dynamic focus amplitude adjustment YES Deflection of input Sync type(biased from 5V alone) YES Vertical moire output YES I2C controlled V-moire amplitude YES Frequency generator for burn-in YES Fast I2C read/write 400 B+ regulation adjustable by I2C YES Unit kHz DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2511B ABSOLUTE MAXIMUM RATINGS No Item Symbol Value Unit 1 Supply voltage (pin 29) VCC 13.5 V 2 Supply voltage (pin 32) VDD 5.7 V 3 Maximum voltage on Pin 4 Pin 9 Pin 5 Pins 6,7,8,14,15,16,20,22 Pins 10,18,23,24,25,26,28 Pins 1,2,3,30,31 VIN 4.0 5.5 6.4 8.0 VCC VDD V V V 4 ESD susceptibillty Human body model, 100pF discharge through 1.5KΩ EIAJ norm, 200pF discharge through 0Ω VESD 2 kV 300 V 5 Storage temperature Tstg - 40, +150 °C 6 Operating temperature Topr 0, +70 °C Symbol Value Unit THERMAL CHARACTERISTICS No Item 1 Junction temperature Tj +150 °C 2 Junction-ambient thermal resistance θja 65 °C/W SYNC PROCESSOR OPERATING CODNITIONS Table 3. Sync Processor Operating Codnitions Parameter Symbol Conditions Min Horizontal sync input voltage HsVR Pin 1 0 Minimum horizontal input pulse duration MinD Pin 1 0.7 Maximum horizontal input signal duty cycle Mduty Pin 1 Vertical sync input voltage VsVR Pin 2 0 Minimum vertical sync pulse width VSW Pin 2 5 Maximum vertical sync input duty cycle VSmD Pin 2 15 % Maximum vertical sync width on TTL H/V composite VextM Pin 1 750 µs IHLOCKOUT Pin 3 250 µA Sink and source current Typ Max Unit 5 V µs 25 % 5 V µs 7 KB2511B DEFLECTION PROCESSOR FOR MULTISYNC MONITORS ELECTRICAL CHARACTERISTICS ( VDD = 5V, Tamb = 25 °C ) Table 4. Sync Processor Electrical Characteristics Parameter Symbol Conditions Min Horizontal and vertical input threshold voltage (pin 1, 2) VINTH Low level High level 2.2 Horizontal and vertical pull-up resister RIN pins 1,2 Falling and rising output CMOS buffer TfrOut pin 3, Cout = 20pF Horizontal 1st PLL lock output status (pin 3) VHlock Locked, ILOCKOUT= -250µA Unlocked, ILOCKOUT= +250µA Extracted vsync integration time (% of TH(9)) on H/V composite VoutT C0 = 820pF Typ Max Unit 0.8 V V 200 KΩ 0 5 26 200 ns 0.5 V V 35 % I2C READ/WRITE(See also I2C table control and I2C sub address control) OPERATING CONDITIONS Table 5. I2C Read/Write Operating Conditions Parameter 8 Symbol Min Typ Max Unit Input High Level Voltage VinH 3.0 - 5.0 V Input Low Level Voltage VinL 0 - 1.5 V SCL Clock frequency fSCL - - 200 kHz Hold time before a new transmission can start tBUF 1.3 - - uS Hold time for Start conditions tHDS 0.6 - - uS Set-Up time for Stop conditions tSUP 0.6 - - uS The Low Period of SCL tLOW 1.3 - - uS The High Period of SCL tHIGH 0.6 - - uS Hold time data tHDAT 0.3 - - uS Set-Up time data tSUPDAT 0.25 - - uS Rise time of SCL tR - - 1.0 uS Fall time of SCL tF - - 3.0 uS DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2511B I2C BUS Timing Requirement Stop:Clock High tBUF Start:Clock High tHDAT SDA tHDS tSUPDAT tSUP SCL tLOW tHIGH Data Change:Clock Low ELECTRICAL CHARACTERISTICS ( VDD = 5V, Tamb = 25 °C) Table 6. I2C Read/Write Electrical Characteristics Parameter Symbol Conditions Min Typ Max Unit Maximum clock frequency Fscl Pin 30 400 kHz Low period of the SCL clock Tlow Pin 30 1.3 µs High period of the SCL clock Thigh Pin 30 0.6 µs SDA and SCL input threshold Vinth Pin 30, 31 Acknowledge output voltage on SDA input with 3mA VACK Pin 31 I2C PROCESSOR 2.2 V 0.4 V Max Unit HORIZONTAL SECTION OPERATING CONDITIONS Table 7. Horizontal Section Operating Conditions Parameter Symbol Conditions Min Typ Minimum oscillator resistor R0(Min.) Pin 6 6 KΩ Minimum oscillator capacitor C0(Min.) Pin 5 390 pF Maximum oscillator frequency F(Max.) VCO 150 kHz OUTPUT SECTION Maximum input peak current I12m Pin 12 5 mA Horizontal drive output maximum current HOI Pin26, sunk current 30 mA 9 KB2511B DEFLECTION PROCESSOR FOR MULTISYNC MONITORS ELECTRICAL CHARACTERISTICS ( VDD = 5V, Tamb = 25 °C) Table 8. Horizontal Section Electrical Characteristics Parameter Symbol Conditions Min Typ Max Unit SUPPLY AND REFERENCE VOLTAGE Supply voltage Vcc Pin 29 10.8 12 13.2 V Supply voltage VDD Pin 32 4.5 5 5.5 V Supply current ICC Pin 29 50 mA Supply current IDD Pin 32 5 mA Horizontal reference voltage VREF-H Pin 13, I=-2mA 7.4 8 8.6 V Vertical reference voltage VREF-V Pin 21, I=-2mA 7.4 8 8.6 V Max. sourced current on VREF-H IREF-H Pin 13 5 mA Max. sourced current on VREF-V IREF-V Pin 21 5 mA Polarity integration delay HpoIT Pin 1 VCO control voltage (pin 7) VVCO VREF-H=8V f0 fH (Max.) 1st PLL SECTION VCO gain (pin 7 ) Horizontal phase adjustment(11) Horizontal phase setting value(Pin 8)(11) Minimum current value Typical value Maximum value PLL1 filter current charge Free running frequency Free running frequency thermal drift 0.75 ms 1.3 6.2 V V 17 kHz/V % of horizontal period ± 10 % Hphmin Hphtyp Hphmax Sub-address 01 Byte x 1111111 Byte x 1000000 Byte x 0000000 2.6 3.2 3.8 V V V IPII1U IPII1L PLL1 is unlocked PLL1 is locked ±140 ±1 µA mA R0=6.49KΩ,C0=820pF, f0=0.97/8R0C0 ±140 ±1 µA mA -150 ppm/c 0.8 1.3 F0 F0 VCOG Hph fo R0=6.49KΩ, C0=820pF, dF/dV=1/11R0C0 dF0/dT (no drift on external components)(7) Free running frequency adjustment Minimum value Maximum value PLL1 capture range Safe forced frequency SF1 Byte 11 x x x x x x SF2 Byte 10 x x x x x x f0(Min.) f0(Max.) CR SFF Sub-address 02 Byte x x x 11111 Byte x x x 00000 R0=6.49KΩ,C0=820pF, from f0+0.5KHz to 4.5Fo fH(Min.) fH(Max.) Sub-address 02 2ND PLL SECTION HORIZONTAL OUTPUT SECTION 10 23.5 100 2F0 3F0 KHz KHz DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2511B Table 8. Horizontal Section Electrical Characteristics (Continued) Parameter Symbol Flyback input threshold voltage (pin12) FBth Horizontal jitter Hjit Min Typ Max Unit 0.65 0.75 V 70 ppm % % Sub-address 00 Horizontal drive output duty-cycle (pin 26) (1, 2) Low level High level Conditions HDmin HDmax Byte xxx11111 Byte xxx00000 30 60 X-RAY protection input threshold voltage XRAYth Pin 25(12) 8 V Internal clamping levels on 2nd PLL loop filter (pin 4 ) Vphi2 Low level High level 1.6 3.7 V V Threshold voltage to stop H-out, V-out when VCC < VSCinh VSCinh Pin 29 7.5 V Horizontal drive output (low level) HDvd Pin 26 IOUT=30mA (2) 0.4 V HORIZONTAL DYNAMIC FOCUS FUNCTION Horizontal dynamic focus sawtooth Minimum level Maximum level HDFst Horizontal dynamic focus sawtooth Discharge width Capacitor on HfocusCap and C0=820pF, TH=20µS, Pin 9 2 4.7 V V HDFdis Start by Hfly center 400 ns Bottom DC output level HDFDC RLOAD=10KΩ, pin 10 2 V DC output voltage thermal drift TDHDF 200 ppm/C Horizontal dynamic focus amplitude Min Byte xxx11111 Typ Byte xxx10000 Max Byte xxx00000 HDFamp 1 1.5 3 Vpp Vpp Vpp Horizontal dynamic focus keystone Min A/B Byte xxx11111 Typ Byte xxx10000 Max Byte xxx00000 HDFkeyst Sub-address 03, pin 10, FH=50kHz, Keystone Typ Sub-address 04, FH = 50kHz, Typ amp B/A A/B A/B 2.2 2.2 3.5 1.0 3.5 VERTICAL DYNAMIC FOCUS FUNCTION (POSITIVE PARABOLA) Vertical dynamic focus parabola (added to horizontal one) amplitude with VOUT and VPOS typical Min. Byte 000000 Typ. Byte 100000 Max. Byte 111111 AMPVDF Parabola amplitude function of VAMP (tracking between VAMP and VDF) with VDFAMP VPOS typ. (see figure 1) (3) Parabola assymetry function of VPOS control (tracking between VPOS and VDF) with VAMP Max. VHDFKeyt Sub-address 0F 0 0.5 1 Vpp Vpp Vpp Sub-address 05 Byte 10000000 Byte 11000000 Byte 11111111 0.6 1 1.5 Vpp Vpp Vpp Sub-address 06 Byte x0000000 Byte x1111111 0.52 0.52 Vpp Vpp 11 KB2511B DEFLECTION PROCESSOR FOR MULTISYNC MONITORS VERTICAL SECTION OPERATING CONDITIONS Table 9. Vertical Section Operating Conditions Parameter Symbol Conditions Min Typ Max Unit 6.5 V OUTPUTS SECTION Maximum EW output voltage VEWM Pin 24 Minimum EW output voltage VEWm Pin 24 1.8 V Minimum load for less than 1% vertical amplitude drift RLOAD Pin 20 65 MΩ ELECTRICAL CHARACTERISTICS (VCC = 12V, Tamb = 25 °C) Table 10. Vertical Section Electrical Characteristics Parameter Symbol Conditions Min Typ Max Unit VERTICAL RAMP SECTION Voltage at ramp bottom point VRB VREF-V=8V, pin 22 2 V Voltage at ramp top point (with sync) VREF-V VRT VREF-V=8V, Pin 22 5 V Voltage at ramp top point (without sync) VRTF Pin 22 VRT-01 V Vertical sawtooth discharge time duration (pin 22) VSTD With 150nF cap 70 µs Vertical free running frequency VFRF COSC(pin22) =150nF measured on pin 22 100 Hz ASFR C22=150nF ± 5% see (4, 5) AUTO -SYNC frequency(13) See Ramp amplitude drift versus frequency at Maximum vertical amplitude RAFD Ramp linearity on pin 22 (∆I22/I22) RIin V20=4.3v, 2.5<V27 & V27<4.5V Vpos Sub address 06 Byte x0000000 Byte x1000000 Byte x1111111 Vertical output voltage (peak-to-peak on pin 23 ) VOR Vertical output Maximum current(Pin 23) VOI Max vertical S-correction amplitude(14) XOXXXXXX inhibits S-CORR X1111111 gives max S-CORR dVS 12 165 Hz C22=150nF 200 TBD ppm/ Hz 50Hz<f and f<165Hz see (4, 5) Vertical position adjustment voltage (pin 23 - VOUT centering) 50 (6) Sub address 05 Byte x0000000 Byte x1000000 Byte x1111111 0.5 % 3.3 3.65 3.2 3.5 3.8 V V V 2.5 3.5 2.25 3 3.75 V V V ±5 mA -4 +4 % % Sub address 07 ∆V/Vpp at TV/4 ∆V/Vpp at 3TV/4 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2511B Table 10. Vertical Section Electrical Characteristics (Continued) Parameter Vertical C-Corr amplitude XOXXXXXX inhibits C-corr Symbol Ccorr Conditions Min Typ Max Unit Sub address 08 ∆V/Vpp at TV/2 Byte X1000000 Byte X1100000 Byte X1111111 -3 0 3 % % % EAST/WEST FUNCTION DC output voltage with typ Vpos, keystone, corner and corner balance inhibited EWDC pin 24, see figure 2 2.5 V DC output voltage thermal drift TDEWDC see note 7 100 ppm/ C Parabola amplitude with Vamp Max. V-Pos typ, keystone ilhibited EWpara Sub address 0A Byte 1111111 Byte 1010000 Byte 1000000 2.5 1.25 0 V V V Parabola amplitude function of V-AMP control (tracking between V-AMP and E/W) with typ Vpos EWtrack Sub address 05 Byte 1000000 Byte 1100000 Byte 1111111 0.45 0.8 1.25 V V V 1 1 Vpp Vpp ketstone, EW Typ amplitude (8) Keystone adjustment capability with typ Vpos, EW typ amplitude and vertical amplitude max, KeyAdj Sub address 09 (8) Byte 1x000000 Byte 1x111111 A/B Ratio(see figure 2) B/A Ratio Intrinsic keystone function of V-POS control (tracking between V-pos and EW) Max amplitude KeyTrack and vertical amplitude max. (10) A/B Ratio B/A Ratio Sub address 09 Byte x0000000 Byte x1111111 0.52 0.52 INTERNAL HORIZONTAL DYNAMIC PHASE CONTROL FUNCTION Side pin balance parabola amplitude (figure3) with Vamp max, V-POS typ and parallelogram inhibited SPBpara (8,9) Side pin balance parabola amplitude function of Vamp control (tracking between Vamp and SPB) with SPB max, V-POS typ and parallelogram SPBtrack inhibited(8,9) Parallelogram adjustment capability with Vamp max, V-POS typ and SPB A/B Ratio B/A Ratio ParAdj Sub address 0D Byte x1111111 Byte x0000000 +1.4 -1.4 %TH %TH Sub address 05 Byte 10000000 Byte 11000000 Byte 11111111 0.5 0.9 1.4 %TH %TH %TH +1.4 -1.4 %TH %TH Sub address 0E max (8,9) Intrinsic parallelogram function of Vpos control (tracking between V-pos and DHPC) with Vamp max, SPB max and parallelogram inhibited(8, 9) A/B Ratio B/A Ratio Byte x1111111 Byte x1000000 Partrack Sub address 06 Byte x0000000 Byte x1111111 0.52 0.52 13 KB2511B DEFLECTION PROCESSOR FOR MULTISYNC MONITORS Table 10. Vertical Section Electrical Characteristics (Continued) Parameter Symbol Conditions Min Typ Max Unit VERTICAL MOIRE Vertical moire (measured on VOUTDC) pin 23 VMOIRE Sub address 0C Byte 01x11111 6 mV BREATHING COMPENSATION DC breathing control range(15) BRRANG V18 Vertical output variation versus DC breathing control (Pin 23) BRADj V18≥VREF-V V18=4V 1 12 0 -10 V % % B+ SECTION OPERATING CONDITIONS Table 11. B+ Section Operating Conditions Parameter Symbol Minimum feedback resistor FeedRes Conditions Min Resistor between pins 15 and 14 Typ Max 5 Unit KΩ ELECTRICAL CHARACTERISTICS (VCC = 12V, Tamp = 25 °C ) Table 12. B+ Section Electrical Characteristics Parameter Symbol Conditions Min Typ Max Unit Error amplifier open loop gain OLG At low frequency (10) 85 dB Unity gain band width UGBW see (7) 6 MHz Regulation input bias current IRI Current sourced by pin 15 (PNP base) 0.2 µA Maximum guaranted error amplifier output current EAOI Current sourced by pin 14 Current sunk by pin 14 Current sense input voltage gain CSG Pin 16 3 Max current sense input thres hold voltage MCEth Pin 16 1.2 V Current sense input bias current ISI Current sunk by pin 16 (NPN base ) 1 µA Maxmum external power transistor on time Tonmax % of H-period 100 % B+ output low level saturation voltage B+OSV V28 with I28=10mA 0.25 V Internal reference voltage IVREF On error amp (+) input for subaddress 0B byte 1000000 4.8 V 14 @ 0.5 2 mA mA f0=27kHz (16) DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2511B Table 12. B+ Section Electrical Characteristics Internal reference voltage adjustment range VREFADJ Byte 111111 Byte 000000 +20 -20 % % Threshold for step-up/step-down selection DWMSEL Pin 16 6 V Falling time tFB+ Pin 28 100 ns 15 KB2511B DEFLECTION PROCESSOR FOR MULTISYNC MONITORS NOTES; 1.Duty cycle is the ratio of power transistor OFF time period. Power transistor is OFF when output transistor is OFF. 2.Initial condition for safe operation start up. 3.S and C correction are inhibited so the output sawtooth has a linear shape. 4.With register 07 at byte x0xxxxxx (s-correction control is inhibited) then the S correction is inhibited, consequently the sawtooth has a linear shape. 5.With register 08 at byte x0xxxxxx (C-Correction control is inhibited) then the C correction is inhibited, consequently the sawtooth has a linear shape. 6.It is frequency range for which the vertical oscillator will automatically synchronize, using a single capacitor value on pin 22, and with a constant ramp amplitude. 7.These parameters are not tested on each unit. They are measured during out internal qualification. 8.Refers to notes 4 & 5 from last section. 9.TH is the Horizontal period. 10.These parameters are not tested on each unit. They are measured during our internal qualification procedure which incudes characterization on batches comming from corners of our processes and also temperature char acterization. 11. See Figure 11 for explanation of reference phase. 12. See Figure 15. 13. This is the frequency range for which the vertical oscillator will automatically synchronize, using a single capacitor value on Pin 22 and with a constant ramp amplitude. 14. TV is the vertical period. 15. When not used the DC breathing control pin must be connected to 12V. 16. The external power transistor is OFF during 400ns of the HFOCUSCAP discharge. 16 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS VDFDC KB2511B VDFAMP B A Figure 1. Vertical Dynamic Focus Function EWPARA B A EWDC Figure 2. E/W Output EWPARA B A SPBPARA DHPCPC Figure 3. Dynamic Horizontal Phase Control Output 17 KB2511B Function DEFLECTION PROCESSOR FOR MULTISYNC MONITORS Sub address Pin Byte 10000000 Vertical Size 05 Specification VOUTDC 2.25V 23 VOUTDC 3.75V 11111111 Vertical Position DC Control Vertical S Linearity 06 23 x0000000 x1000000 x1111111 3.2V 3.5V 3.8V x0xxxxxx Inhibited 07 ∆V 23 x1111111 Vpp ∆V =4% Vpp ∆V x1000000 Vpp Vertical C Linearity 08 ∆V =3% Vpp 23 ∆V Vpp x1111111 ∆V =3% Vpp Figure 4. Typical Vertical Output Waveforms 18 Picture Image DEFLECTION PROCESSOR FOR MULTISYNC MONITORS Function Sub address Pin Byte KB2511B Specification Picture Image EWamp Typ. Key Stone (Trapezoid) Control 10000000 09 1.0V 2.5V 1.0V 2.5V 24 1111111 Keystone Inhibited E/W (Pin Cushion) Control 0A 2.5V 0V 1x000000 24 2.5V 1x111111 SPB Inhibited 3.7V Parallelogram Control 0E Internal x1000000 1.4% TH 3.7V 1.4% TH 3.7V 1.4% TH 3.7V 1.4% TH x111111 Parallelogram Inhibited Side Pin Balance Control 0D Internal x0000000 x1111111 Vertical Dynamic Focus with Horizontal 32 2V Figure 5. Geometry Output Waveforms 19 KB2511B DEFLECTION PROCESSOR FOR MULTISYNC MONITORS I2C BUS ADDRESS TABLE Slave Address (8C): Write Mode Sub Address Definition D8 D7 D6 D5 D4 D3 D2 D1 0 0 0 0 0 0 0 0 0 Horizontal drive selection/horizontal duty cycle 1 0 0 0 0 0 0 0 1 Horizontal position 2 0 0 0 0 0 0 1 0 Forced frequcny /free running frequency 3 0 0 0 0 0 0 1 1 Synchro priority / horizontal focus amplitude 4 0 0 0 0 0 1 0 0 Refresh /horizontal focus keystone 5 0 0 0 0 0 1 0 1 Vertical ramp amplitude 6 0 0 0 0 0 1 1 0 Vertical position adjustment 7 0 0 0 0 0 1 1 1 S Correction 8 0 0 0 0 1 0 0 0 C Correction 9 0 0 0 0 1 0 0 1 E/W keystone A 0 0 0 0 1 0 1 0 E/W amplitude B 0 0 0 0 1 0 1 1 B+ reference adjustment C 0 0 0 0 1 1 0 0 Vertical moire D 0 0 0 0 1 1 0 1 Side pin balance E 0 0 0 0 1 1 1 0 Parallelogram F 0 0 0 0 1 1 1 1 Vertical dynamic focus amplitude Slave Address (8D): Read Mode No Sub Address needed 20 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2511B I2C BUS ADDRESS TABLE c ( ontinued) D8 D7 D6 D5 D4 D3 D2 D1 [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] WRITE MODE 01 Horizontal duty cycle HDrive 0, off [1],on 00 Xray 1,reset [0] [0] Horizontal phase adjustment [1] [0] [0] Forced frequency 02 1,on, [0],off 03 Sync 0, comp [1], sep 04 Detect refresh [0], off 05 Vramp 0, off [1], on [0] Free running frequency 1,F0x2 [0],F0x3 [0] [0] [0] Horizontal focus amplitude [1] [0] [0] Horizontal focus keystone [1] [0] [0] Vertical ramp amplitude adjustment [1] [0] [0] [0] Vertical position adjustment 06 [1] 07 S Select 1, on [0] 08 C Select 1, on [0] 09 EW key 0, off [1] 0A EW sel 0, off [1] 0B Test H 1, on [0], off 0C Test V 1, on [0], off 0D SPB sel 0, off [1] 0E Parallelo 0, off [1] 0F [0] [0] [0] [0] S Correction [1] [0] [0] C Correction [1] [0] [0] East/West keystone [1] [0] [0] East/West amplitude [1] [0] [0] [0] B+ reference adjustment [1] [0] [0] [0] Vertical Moire Moire 1, on [0] [0] [0] [0] Side pin balance [1] [0] [0] Parallelogrm [1] [0] [0] Vertical dynamic focus amplitude [1] [0] [0] [0] 21 KB2511B DEFLECTION PROCESSOR FOR MULTISYNC MONITORS READ MODE 00 Hlock 0, on [1], no Vlock 0, on [1], no Xray 1,on [0],off Polarity detection H/V pol [1],negative V pol [1], negative Synchro detection Vext det [0],no det H/V det [0],no det V det [0], nodet [ ] initlal value OPERATING DESCRIPTION GENERAL CONSIDERATIONS Power Supply The typical values of the power supply voltages Vcc and VDD are respectively 12V and 5V. Perfect operation is obtained if Vcc and VDD are maintened in the limits: 10.8 to 13.2V and 4.5 to 5.5V. In order to avoid erratic operation of the circuit during transient phase of Vcc switching on, or switching off, the value of Vcc is monitored and the outputs of the circuit are inhibited if Vcc is less than 7.5V typically. In the same manner, VDD is monitored and internal set-up is made until VDD reaches 4V (see I2C control table for power on reset). In order to have a very good power supply rejection, the circuit is internally powered by several internal voltage references (the unigue typical value of which is 8V). Two of these voltage references are externally accessible, one for the vertical part and on one for the horizontal one. If needed, these voltage references can be used (until Iload is less than 5mA). Furthermore it is necessary to filter the a.m. voltage references by the use of external capacitor connected to ground, in order to minimize the noise and consequently the “jitter” on vertical and horizontal output signals. I2C Control KB2511 belongs to the I2C controlled device family, instead of being controlled by DC voltage on dedicated control pins, each adjustment can be realized through the I2C interface. The I2C bus is a serial bus with a clock and a data input. The general function and the bus protocol are specified in the philips-bus data sheets. The interface (data and clock) is TTL-level compatible. The internal threshold level of the input comparator is 2.2V (when VDD is 5V). Spikes of up to 500ns are filtered by an integrator and maximum clock speed is limited to 400kHz. The data line (SDA) can be used in a bidirectional way that means in read-mode the IC clocks out a reply information (1byte) to the micro-processor. The bus protocol prescribes always a full-byte transmission. The first byte after the start condition is used to transmit the IC-address (hexa 8C for write, 8D for read). Write Mode In write mode the second byte sent contains the subaddress of the selected function to adjust (or controls to affect) and the third byte the corresponding data byte. It is possible to send more than one data byte to the IC. If after the third byte no stop or start condition is detected, the circuit increments automatically the momentary subaddress in the subaddress counter by one (auto-increment mode). So it is possible to transmit immediately the next data bytes without sending the IC address or subaddress. It can be useful so as to reinitialize the whole controls very quickly (flash manner). This procedure can be finished by a stop condition. The circuit has 16 adjustment capabilities: 3 for horizontal part, 4 for vertical one, 2 for E/W correction, 2 for the dynamic horizontal phase control, 1 for moire option, 3 for horizontal and vertical dynamic focus and 1 for B+ reference adjustment. 17 bits are also dedicated to several controls (ON/OFF, horizontal forced frequency, sync priority, detection refresh and Xray reset). 22 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2511B Read Mode During read mode the second byte transmits the reply information. The reply byte contains horizontal and vertical lock/unlock status, Xray activated or not, the horizontal and vertical polarity detection. It also contains synchro detection status that is useful for µP to assign sync priority. A stop condition always stops all activities of the bus decoder and switches the data and the clock line (SDA and SCL) to high impedance. See I2C subaddress and control tables. Sync processor The internal sync processor allows the KB2511B to accept any kind of input synchro signals: - separated horizontal & vertical TTL-compatible sync signals, - composite horizontal & vertical TTL-compatible sync signals. Sync identification Status The MCU can read (address read mode : 8D) the status register via the I2C bus, and then select the sync priority depending on this status. Among other data this register indicates the presence of sync pulses on H/HVIN, VSYNCIN and(when 12V is supplied) whether a Vext has been extracted from H/HVIN. Both horizontal and vertical sync are detected even if only 5V is supplied. In order to choose the right sync priority the MCU may proceed as follows(see I2C Address Table): - refresh the status register, - wait at least for 20ms(MAX. vertical period), - read this status register, Sync priotity choice should be: Vext det H/V det V det Sync priority subaddress 03 (D8) Comment sync type No Yes Yes 1 Separated H & V Yes Yes No 0 Composite TTL H & V Of course, when choice is made, one can refresh the sync detections and verify that extracted Vsync is present and that no sync change occured. Sync processor is also giving sync polarity information. IC status The IC can inform the MCU about the 1st horizontal PLL and vertical section status, and about the Xary protection (activated or not). Resetting the XRAY internal latch can be done either by decreasing the Vcc supply or directly resetting it via the I2C interface. Sync Inputs Both H/HVin and Vsyncin inputs are TTL compatible trigger with hysterisis to avoid erratic detection. Both inputs include a pull up register connected to VDD. Sync Processor Output The sync processr indicates on the HLOCKOUT Pin whether 1st PLL is locked to an incoming horizontal sync. HLOCKOUT is a TTL compatible CMOS output. Its level goes to high when locked. In the same time the D8 bit of the status regiser is set to 0. This information is mainly used to trigger safety procedures(like reducing B+ value) as soon as a change is detected on the incoming sync. Further to this, it may be used in an automatic procedure for 23 KB2511B DEFLECTION PROCESSOR FOR MULTISYNC MONITORS free running frequency(fo) adjustment. Sending the desired fo on the sync input and progressively decreasing the free running frequently I2C register value(address 02), the HLOCKOUT Pin will go high as soon as the proper setting is reached. Setting the free running frequency this way allows to fully exploit the KB2511B horizontal frequency range. HORIZONTAL PART Internal input conditions Horizontal part is internally fed by synchro processor with a digital signal corresponding to horizontal synchro pulses or to TTL composite input. concerning the duty cycle of the input signal, the following signals (positive or negative)may be applied to the circuit. Using internal integration, both signals are recognized on condition that Z/T < 25%, synchronisation occurs on the leading edge of the internal sync signal. The minimum value of Z is 0.7µs. Z T Z Figure 6. An other integration is able to extract vertical pulse of composite synchro if duty cycle is more than 25% (typically d = 35%) (7) c TRAMEXT d d Figure 7. The last feature performed is the equalizing pulses removing to avoid parasitic pulse on phase comparator input which is intolerent to wrong or missing pulse. PLL1 The PLL1 is composed of a phase comparator, an external filter and a voltage control oscillator (VCO). The phase comparator is a phase frequency type designed in CMOS technology. This kind of phase detector avoids locking on false frequencies. It is followed by a charge pump, composed of two current sources sunk and sourced (I = 1mA typ. when locked, I = 140mA when unlocked). This difference between lock/unlock permits a smooth catching of horizontal frequency by PLL1. This effect is reinforced by an internal original slow down system when PLL1 is locked avoiding horizontal too fast frequency change. The dynamic bahaviour of the PLL is fixed by an external filter which integrates the current of the charge pump. A CRC filter is generally used (see figure 8 ) 24 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2511B PLL1F 7 1.8KΩ 4.7uF 1uF Figure 8. PLL1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing pulses or wrong pulse on phase comparator. The inhibition results from the opening of a switch located between the charge pump and the filter (see figure 9 ). The VCO uses an external RC network. It delivers a linear sawtooth obtained by charge and discharge of the capacitor, by a current proportionnal to the current in the resistor. Typical thresholds of sawtooth are 1.6V and 6.4V. PLL1F R0 H-LOCKCAP LOCK/UNLOCK STATUS 8 INPUT INTERFACE 8 9 I2C SMFE TRAMEXT MODE LOCKDET HSYNC 7 C0 High COMP1 E2 Low CHARGE PUMP TRAMEXT PHASE ADJUST PLL INHIBITION VCO I2C OSC HPOS Adj. Figure 9. Block Diagram 25 KB2511B DEFLECTION PROCESSOR FOR MULTISYNC MONITORS I2C Free running Adjustment + ID 2 6.4V - + Loop Filter 7 a + - ID (0.80<a<1.30) (1.3V < V7 < 6V) 6 1.6V - 4 I0 2 6.4V 5 R0 RS FLIP FLOP Co 1.6V 0 0.84T T Figure 10. Details of VCO The control voltage of the VCO is typically comprised between 1.33V and 6V (see figure 10). The theorical frequency range of this VCO is in the ratio 1 to 4.5, the effective frequency range has to be smaller 1 to 4.2 due to clamp intervention on filter lowest value. To avoid spread of external components and the circuit itself, it is possible to adjust free running frequency through I2C. This adjustment can be made automatically on the manufacturing line without manual operation by using hlock/unlodk information. The adjustment range is 0.8 to 1.3 F0 (where 1.3 F0 is the free running frequency at power on reset). The sync frequency has to be always higher than the free running frequency. As an example for a synchro range from 24kHz to 100kHz, the suggested free running frequency is 23kHz. An other feature is the capability for MCU to force horizontal frequency throw I2C to 2xF0 or 3xF0 (for burn in mode or safety requirement). In this case, inhibition switch is opened leaving PLL1 free but voltage on PLL1 filter is forced to 2.66V for 2xF0 or 4.0V for 3xF0. The PLL1 ensures the coincidence between the leading edge of the synchro signal and a phase reference obtained by comparism between the sawtooth of the VCO and an internal DC voltage I2C adjustable between 2.65V and 3.75V (corresponding to ±10%) (see figure 11) H Osc Sawtooth 7/8TH 1/8TH 6.4V 2.65V < Vb < 3.75V Vb Phase REF1 1.6V Phase REF1 is obtained by comparision between the sawtooth and a DC voltage adjustable between 2.6V and 3.8V. The PLL1 ensures the exact coindidence between the signals phase REF and HSYNS. A ±TH/10 phase adjustment is possible H Synchro Figure 11. PLL1 Timing Diagram 26 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2511B The KB2511B also includes a lock/unlock identification block which senses in real time whether PLL1 is locked or not on the incoming horizontal sync signal. The resulting information is available on Hlockout (see sync processor). The block function is described in figure 12. When PLL1 is unlocked, It forces Hlockout to leave high. The lock/unlock information is also available throw I2C read. PLL2 The PLL2 ensures a constant position of the shaped flyback signal in comparism with the sawtooth of the VCO (figure 12). The phase comparator of PLL2 (phase type comparator) is followed by a charge pump(typical output current:0.5mA). The flyback input is composed of an NPN transistor. This input must be current driven. The maximum recommanded input current is 5mA (see figure 13). The dury cycle is adjustable through I2C from 30% to 60%. For startup safe operation, initial duty cycle (after power on reset) is 60% in order to avoid having a too long conduction period of the horizontal scanning transistor. The maximum storage time(Ts MAX.) is (0.38TH-TFLY/2). Typically, TFLY/TH is around 20% which means that Ts max is around 28% of TH. H Osc Sawtooth 1/8TH 7/8TH 6.4V 3.7V 1.6V Flyback Internally Shaped Flyback H drive Ts Duty Cycle Figure 12. PLL2 Timing Diagram 400Ω HFLY 12 Q1 20KΩ GND 0V Figure 13. Flyback Input Electrical Diagram 27 KB2511B DEFLECTION PROCESSOR FOR MULTISYNC MONITORS Output Section The H-drive signal is transmitted to the output through a shaping block ensuring TS and I2C adjustable duty cycle. In order to secure scanning power part operation, the output is inhibited in the following circumstances: - Vcc too low - Xray protection activated - During horizontal flyback - H Drive I2C bit control is off. The output stage is composed of a NPN bipolar transistor. Only the collector is accessible (see figure 14). 26 H-DRIVE Figure 14. The output NPN is in off-state when the power scanning transistor is also in off-state. The maximum output current is 30mA, and the corresponding voltage drop of the output VCEsat is 0.4V typically. It is evident that the power scanning transistor cannot be directly driven by the integrated circuit. An interface has to be designed between the circuit and the power transistor which can be of bipolar or MOS type. X-RAY protection The activation of the X-ray protection is obtained by application of a high level on the X-ray input (8V on pin 25). It inhibits the H-Drive and B+ outputs. This protection is latched; It may be reset either by Vcc switch off or by I2C(see figure 15). Horizontal and vertical dynamic focus The KB2511B delivers and horizontal parabola added on a vertical parabola wavefrom on pin 10. This horizontal parabola is performed from a sawtooth in phase with flyback pulse middle. This sawtooth is present on pin 9 where the horizontal focus capacitor is the same as C0 to obtain a controlled amplitude (from 2 to 4.7V typically). Symmetry (keystone) and amplitude are I2C adjustable (see figure 16). Vertical dynamic focus is tracked with VPOS and VAMP. Its amplitude can be adjusted. It is also affected by S and C corrections. This positive signal has to be connected to the CRT focusing grids. 28 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS I2C Drive on/off Vcc checking Vcc - VSCinh + HORIZONTAL OUTPUT INHIBITION XRAY protection Xray S I2C ramp on/off Q Vcc off or I2C reset R Horizontal flyback - 0.7V + KB2511B VERTICAL OUTPUT INHIBITION BOUT Figure 15. Safety Functions Block Diagram Horizontal flyback Internal triggerd Horizontal flyback 4.7V 2V Horizontal focus Cap Sawtooth Horizontal dynamic focus parabola output 400ns 2V Moire output Figure 16. 29 KB2511B DEFLECTION PROCESSOR FOR MULTISYNC MONITORS VERTICAL PART Geometric Corrections The principle is represented in figure 17. Parabola Generator V.Focus AMP Horizontal Dynamic Focus + VDCMID(3.5V) 23 2 I 10 EW amp + VDCMID (3.5V) Vertical Ramp VOUT Dynamic focus 24 EW output keystone sidepin amp VDCMID (3.5V) To horizontal + phase Parallelogram Sidepin balance output current Figure 17. Geometric Correcitions Principle Starting from the vertical ramp, a parabola shaped current is generated for E/W correction, dynamic horizontal phase control correction, and vertical dynamic focus correction. The base of the parabola generator is an analog multiplier, the output current of which is equal to: ∆I = k• ( VOUT - VDCMID ) 2 Where Vout is the vertical output ramp(typically between 2 and 5V) and VDCMID is 3.5V(for VREF-V=8V). The VOUT sawtooth is typically centered on 3.5V. By changing the vertical position, the sawtooth shifts by ±0.3V. In order to keep a good screen geometry for any end user preference adjustment we implemented the geometry tracking. Due to large output stages voltage range (E/W, FOCUS), the combination of tracking function with maximum vertical amplitude max or min vertical position and maximum gain on the DAC control may lead to the output stages saturation. This must be avoided by limiting the output voltage by appropriate I2C registers values. For E/W part and Dynamic Horizontal phase control part, a sawtooth shaped differential current in the following form is generated: ∆I’ = k’ • ( VOUT - VDCMID )2 Then ∆I and ∆I’are added together and converted into voltage for the E/W part. Each of the two E/W components or the two Dynamic horizontal phase control ones may be inhibited by their own I2C select bit. The E/W parabola is available on pin 24 by the way of an emitter follower which has to be biased by an external resistor (10KΩ). It can be DC coupled with external circuitry. Vertical dynamic focus is combined with horizontal one on output pin 10. Dynamic horizontal phase control current drives internally the H-position, moving the Hfly position on the horizontal sawtooth in the ± 1.4% Th both on side pin balance and parallelogrm. 30 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2511B EW EWOUT = 2.5V + K1 ( VOUT - VDCMID )2 + K2 ( VOUT - VDCMID ) K1 is adjustable by EW amplitude I2C register K2 is adjustable by keystone I2C register Dynamic horizontal phase control IOUT = K3 ( VOUT - VDCMID ) 2 + K4 ( VOUT - VDCMID ) K4 is adjustable by side pin balance I2C register K3 is adjustable by parallelogram I2C register. Function When the synchronisation pulse is not present, an internal current source sets the free running frequency. For an external capacitor, COSC = 150nF, the typical free running frequency is 100Hz. Typical free running frequency can be calculated by: 1 f0 (Hz)= 1.5•10-5 • C OSC A negative or positive TTL level pulse applied on pin 2 (VSYNC) as well as a TTL composite sync on pin 1 can synchronise the ramp in the range [fmin, fmax]. This frequency range depends on the external capacitor connected on pin 22. A capacitor in the range [150nF, 220nF] ± 5% is recommanded for application in the following range: 50Hz to 165Hz. Typical maximum and minimum frequency, at 25°C and without any correction (S correction or C correction), can be calculated by: f(Max.) = 2.5 x f0 and f(Min.) = 0.33 x f0 If S or C corrections are applied, these values are slighty affected. If a synchronisation pulse is applied, the internal oscillator is automaticaly caught but the amplitude is no more constant. An internal correction is activated to adjust it in less than a half a second : the highest voltage of the ramp pin 22 is sampled on the sampling capacitor connected on pin 20 at each clock pulse and a transconductance amplifier generates the charge current of the capacitor. The ramp amplitude becomes again constant. The read status register enables to have the vertical lock-unlock and the vertical sync polarity informations. It is recommanded to use a AGC capacitor with low leakage current. A value lower than 100nA is mandatory. Good stability of the internal closed loop is reached by a 470nF ± 5% capacitor value on pin 20 (VAGC) 31 KB2511B DEFLECTION PROCESSOR FOR MULTISYNC MONITORS TRANSCONDUCTANCE AMPLIFIER CHARGE CURRENT 22 DISCH. 2 SYNCHRO V-SYNC + REF SAMPLING 20 S CORRECTION SAMP CAP OSC CAP VS_AMP SUB07/8bits COR-C SUB08/6bits OSCILLATOR POLARITY C CORRECTION + - Vlow Switch Dlech 23 VOUT 18 BREATH VERT_AMP SUB05/7BITS VMOIRE SUB0C/5BITS VOSITION SUB06/7BITS Figure 18. AGC Loop Block Diagram I2C Control Adjustments Then, S and C correction shapes can be added to this ramp. This frequency independent S and C corrections are generated internally. Their amplitude are adjustable by their respective I2C register. They can also be inhibited by their select bit. Endly, the amplitude of this S and C corrected ramp can be adjusted by the vertical ramp amplitude control register. The adjusted ramp is available on pin 23 (VOUT) to drive an external power stage. The gain of this stage is typically 25% depending on its register value. The mean value of this ramp is driven by its own I2C register (vertical position). Its value is VPOS = 7/16 • VREF ± 300mV. Usually VOUT is sent through a resistive divider to the inverting input of the booster. Since VPOS derives from VREF-V, the bias voltage sent to the non-inverting input of booster should also derive from VREF-V to optimize the accuracy(see Application Diagram). Basic Equations In first approximation, the amplitude of the ramp on pin 23 (Vout) is: VOUT - VPOS = ( VOSC - VDCMID ) • ( 1 + 0.25 (VAMP) ) with: - VDCMID = 7/16•VREF( typically 3.5V, the middle value of the ramp on pin 22) - VOSC = V22 ( ramp with fixed amplitude) - VAMP = - 1 for minimum vertical amplitude register value and +1 for maximum - VPOS is calculated by : VPOS = VDCMID + 0.3Vp with Vp equals -1 for minimum vertical position register value and +1 for maximum The current available on Pin 22 is : IOSC = 32 3 8 • VREF • COSC • f DEFLECTION PROCESSOR FOR MULTISYNC MONITORS KB2511B with COSC: capacitor connected on pin 22 f: synchronisation frequency. Vertical Moire By using the vertical moire, VPOS can be modulated from to frame. This function is intended to cancel the fringes which appear when line to line interval is very close to the CRT vertical pitch. The amplitude pf the modulation is controlled by register VMOIRE on sub-off via the control bit D7. DC/DC CONVERTER PART This unit controls the switch-mode DC/DC con-verter. It converts a DC constant voltage into the B+ voltage (roughly proportional to the horizontal frequency)necessary for the horizontal scanning. This DC/DC converter can be configured either in step-up or step-down mode. In both cases it oper-ates very similarly to the well known UC3842. Step-up Mode Operating Description - The powerMOSisswitched-onduringthe flyback (at the beginning of the positive slope of the horizontal focus sawtooth). - The power MOS is switched-off when its current reachesa predeterminedvalue. Forthispurpose, a sense resistor is inserted in its source. The voltage on this resistor is sent to Pin16 (ISENSE). - The feedback(coming either from the EHV or from the flyback) is divided to a voltage close to 4.8V and compared pared to the internal 4.8V reference(IVREF). The difference is amplified by an error amplifier, the output of which controls the power MOS switch-off current. Main Features - Switching synchronized on the horizontal fre-quency, - B+ voltage always higher than the DC source, - Current limited on a pulse-by-pulse basis. Step-down Mode In step-down mode, the Isense information is not used any more and therefore not sent to the Pin16. This mode is selected by connecting this Pin16 to a DC voltage higher than 6V (for example VREF-V). Operating Description - The powerMOSis switched-onas for thestep-up mode. - The feedbackto the error amplifier is done as for the step-up mode. - The power MOS is switched-off when the HFOCUSCAP voltage get higher than the error amplifier output voltage Main Features - Switching synchronized on the horizontal fre-quency, - B+ voltage always lower than the DC source, - No current limitation. 33 KB2511B DEFLECTION PROCESSOR FOR MULTISYNC MONITORS APPLICATION CIRCUIT VCC=12V HSYNC 5V 1K VSYNC 1 1K 2 3 22nF 100V 4 HSYNC_IN 32 5V VSYNC_IN SDA H_LOCKOUT SCL PLL2C VCC + 100uF 31 6.8K 6 4.7uF 50V 1.8K 7 CO B+OUT RO GND SDA 100 30 100 SCL 29 + 100uF 1% P 820pF 50V 5 0.1uF 0.1uF 10K 28 27 1K + PLL1F 26 H_OUT HOUT 10nF 100V MP 1uF 820pF 10K 22K 8 HPOSITION 25 XRAY 50K KB2511B 9 10 11 HFOCUSCAP EWOUT H_FOCUS VOUT HGND 24 10K 23 10K 22 VSCAP 150nF 100V 1% P AFC 12 HFLY 21 V_REF AFC 4.7uF 13 + H_REF VAGCCAP COMP VGND REGIN BREATH +47uF 50V 0.1uF 20 470nF 63V P 0.1uF 14 10K 19 1K 1M 22K 50K 15 50K 18 33K 1K 22K 16 50K I_SENSE 17 B+GND 3.3K 12V SCLK 1 74HCT125 SDAT 2 1 47pF 5V 14 ACK 3 2 100K 13 4 3 12 4 11 HOUT 1 16 2 15 47pF 3 14 4 5 5 6 7 13 MC14528 12 10 + 0.1uF 100uF 9 8 SCL SDA 34 100K 6 11 7 10 10K 8 9 33pF AFC