STMICROELECTRONICS TDA9105A

TDA9105A
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
PRODUCT PREVIEW
VERTICAL
VERTICAL RAMP GENERATOR
50 TO 185Hz AGC LOOP
DCCONTROLLEDV-AMP,V-POS,S-AMP& C-COR
ON/OFF SWITCH
EWPCC
VERTICAL PARABOLA GENERATOR WITH
DC CONTROLLED KEYSTONE & AMPLITUDE
AUTO TRACKING WITH V-POS & V-AMP
CORNER CORRECTION WITH DC CONTROLLED AMPLITUDE
GEOMETRY
WAVE FORM GENERATOR FOR PARALELLOGRAM & SIDE PIN BALANCE CONTROL
AUTO TRACKING WITH V-POS & V-AMP
DYNAMIC FOCUS
VERTICAL PARABOLA OUTPUT FOR VERTICAL DYNAMIC FOCUS
AUTO TRACKING WITH V-POS & V-AMP
GENERAL
ACCEPT POSITIVE OR NEGATIVE HORIZONTAL & VERTICAL SYNC POLARITIES
SEPARATE H & V TTL INPUT
COMPOSITE BLANKING OUTPUT
DESCRIPTION
The TDA9105A is a monolithic integrated circuit
assembled in a 42 pins shrink dual in line plastic
package.
This IC controls all the functions related to the
horizontal and vertical deflection in multimodes or
multisync monitors.
This IC, combined with TDA9205 (RGB preamp),
STV942x(OSD processor), ST727x(micro controller) and TDA817x (vertical booster), allows to realize very simple and high quality multimodes or
multisync monitors.
SHRINK42
(Plastic Package)
ORDER CODE : TDA9105A
PIN CONNECTIONS
V-FOCUS
1
42
SPINBAL
H-LOCKOUT
2
41
KEYBAL
PLL2C
3
40
GEOMOUT
H-DUTY
4
39
EWAMP
H-FLY
5
38
KEYST
H-GND
6
37
EWOUT
H-REF
7
36
V-FLY
FC2
8
35
VDCIN
FC1
9
34
V-SYNC
C0
10
33
V-POS
R0
11
32
VDCOUT
PLL1F
12
31
V-AMP
H-LOCKCAP
13
30
V-OUT
PLL1INHIB
14
29
C-CORR
H-POS
15
28
VS-AMP
XRAY-IN
16
27
V-CAP
H-SYNC
17
26
V-REF
VCC
18
25
V-AGCCAP
GND
19
24
V-GND
H-OUTEM
20
23
CORNER
H-OUTCOL
21
22
BLK-OUT
July 1997
This is advance information on a new product now in developme ntor undergoing evaluation . Details are subject to ch ange without notice.
9105A-01.EPS
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HORIZONTAL
DUAL PLL CONCEPT
150kHz MAXIMUM FREQUENCY
SELF-ADAPTATIVE
X-RAY PROTECTION INPUT
DC ADJUSTABLE DUTY-CYCLE
1st PLL LOCK /UNLOCK INFORMATION
WIDE RANGE DC CONTROLLED H-POSITION
ON/OFF SWITCH (FOR PWR MANAGEMENT)
TWO H-DRIVE POLARITIES
1/31
TDA9105A
PIN DESCRIPTION
Pin
1
Name
V-FOCUS
2
3
4
H-LOCKOUT
PLL2C
H-DUTY
5
H-FLY
First PLL Lock/Unlock Output
Second PLL Loop Filter
DC Control of Horizontal Drive Output Pulse Duty-cycle. If this Pin is grounded, the Horizontal
and Vertical Outputs are inhibited. By connecting a Capacitor on this Pin a Soft-start function
may be realized on H-drive Output.
Horizontal Flyback Input (positive polarity)
6
7
8
H-GND
H-REF
FC2
Horizontal Section Ground
Horizontal Section Reference Voltage, must be filtered
VCO Low Threshold Filtering Capacitor
9
10
11
FC1
C0
R0
12
13
PLL1F
H-LOCKCAP
14
15
PLL1INHIB
H-POS
16
17
18
XRAY-IN
H-SYNC
VCC
19
20
21
GND
H-OUTEM
H-OUTCOL
22
BLK OUT
23
24
CORNER
V-GND
25
V-AGCCAP
26
27
28
V-REF
V-CAP
VS-AMP
Vertical Section Reference Voltage
Vertical Sawtooth Generator Capacitor
DC Control of Vertical S-Shape Amplitude
29
30
31
C-CORR
V-OUT
V-AMP
DC Control of Vertical C-Correction
Vertical Ramp Output (with frequency independant amplitude and S-Correction)
DC Control of Vertical Amplitude Adjustment
32
33
34
VDCOUT
V-POS
V-SYNC
Vertical Position Reference Voltage Output
DC Control of Vertical Position Adjustment
TTL-Compatible Vertical Sync Input
35
36
37
VDCIN
V-FLY
EWOUT
Geometric Correction Reference Voltage Input
Vertical Flyback Input (positive polarity)
East /West Pincushion Correction Parabola Output
38
39
40
KEYST
EWAMP
GEOMOUT
41
42
KEYBAL
SPINBAL
2/31
Function
Vertical Dynamic Focus Output
VCO High Threshold Filtering Capacitor
Horizontal Oscillator Capacitor
Horizontal Oscillator Resistor
First PLL Loop Filter
First PLL Lock/Unlock Time Constant Capacitor. When Frequency is changing, a Blanking
Pulse is generated on Pin 23, the duration of this Pulse is proportionnal to the Capacitor on
Pin 13.
TTL-Compatible Input for PLL1 Output Current Inhibition
DC Control for Horizontal Centering
X-RAY protection Input (with internal latch function)
TTL compatible Horizontal Sync Input
Supply Voltage (12V Typ.)
Ground
Horizontal Drive Output (emiter of internal transistor)
Horizontal Drive Output (open collector of internal transistor)
Blanking Output, activated during frequency changes, when X-RAY Input is triggered, when
VS is too low, or when Device is in stand-by mode (through H-DUTY Pin 2) and during H-FLY,
V-FLY, V-SYNC, VSawth retrace.
DC Control of Corner Correction Amplitude
Vertical Section Signal Ground
DC Control of Keystone Correction
DC Control East/West Pincushion Correction Amplitude
Side Pin Balance & Parallelogram Correction Parabola Output
DC Control of Parallelogram Correction
DC Control of Side Pin Correction Amplitude
9105A-01.TBL
Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator
9105A-02.EPS
PULSE
SHAPER
POL
DETECT
TDA9105A
V-SYNC 34
V-GND 24
H-FLY
35
22
36
32
33
30
31
25
27
V-SYNC
BLK
GEN
29
VERT OSC
RAMP
GENERATOR
V-MID
28
S
CORR
V-REF
X2
VS-AMP
X2
C-CORR
V-REF 26
SAFETY
PROCESSOR
VCAP
H-LOCKCAP 13
VS
H
OUTPUT
BUFFER
20
21
VAGCCAP
PLL1
INHIB
VIDEO UNLOCK
PULSE
SHAPER
4
V-AMP
PHASE
SHIFTER
16
2
V-OUT
PLL1INHIB 14
LOCK
UNLOCK
IDENT
PLL2C
3
H-LOCKOUT
V-POS
PULSE
SHAPER
POL
DETECT
5
FC1
PHASE
COMP
H-FLY
9
XRAY-IN
VDCOUT
H-SYNC 17
8
R0
VCO
FC2
11
H-DUTY
V-FLY
H-GND 6
PHASE
FREQUENCY
COMP
C0
10
H-OUTCOL
BLK-OUT
V-REF
PLL1F
12
H-OUTEM
VDCIN
H-REF 7
H-POS
15
V-FOCUS
42 SPINBAL
40 GEOMOUT
41 KEYBAL
39 EWAMP
37 EWOUT
38 KEYST
1
23 CORNER
18 VCC
19 GND
TDA9105A
BLOCK DIAGRAM
3/31
TDA9105A
QUICK REFERENCE DATA
Notes : 1. Provided PLL inhibition input is used, see application diagram on page 27.
2. One for Horizontal section and one for Vertical section.
4/31
Value
15 to 150
1 to 3.7
YES
YES (see note 1)
YES
YES
YES
YES
YES
YES
YES
YES
YES
NO
35 to 200
50 to 185
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES (see note 2)
NO
YES
Unit
kHz
FH
Hz
Hz
9105A-02.TBL
Parameter
Horizontal Frequency
Autosynch Frequency (for Given R0, C0)
± Hor Sync Polarity Input
Compatibility with Composite Sync on H-SYNC Input
Lock/Unlock Identification on 1st PLL
DC Control for H-Position
X-RAY Protection
Hor DUTY Adjust
Stand-by Function
Two Polarities H-Drive Outputs
Supply Voltage Monitoring
PLL1 Inhibition Input
Composite Blanking Output
Horizontal Moire Output
Vertical Frequency
Vertical Autosync (for 150nF)
Vertical S-Correction
Vertical C-Correction
Vertical Amplitude Adjustment
Vertical Position Adjustment
East/West Parabola Output
PCC (Pin Cushion Correction) Amplitude Adjustment
Keystone Adjustment
Corner Correction Adjustment
Dynamic Horizontal Phase Control Output
Side Pin Balance Amplitude Adjustment
Parallelogram Adjustment
Tracking of Geometric Corrections with V-AMP and V-POS
Reference Voltage
Mode Detection
Vertical Dynamic Focus
TDA9105A
ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Unit
V CC
Supply Voltage (Pin 18)
13.5
V
V IN
Max Voltage on Pins 4, 15, 28, 29, 31, 33, 38, 39, 41, 42
Pin 5
Pins 17, 34
Pin 16, 2, 22
Pin 14
8
1.8
6
12
5
V
V
V
V
V
ESD Succeptibility
Human Body Model, 100pF Discharge through 1.5kΩ
EIAJ Norm, 200pF Discharge through 0Ω
2
300
kV
V
-40, +150
°C
150
°C
0, +70
°C
VESD
Tstg
Tj
Toper
Storage Temperature
Max Operating Junction Temperature
Operating Temperature
9105A-03.TBL
Symbol
Symbol
Rth (j-a)
Parameter
Junction-Ambient Thermal Resistance
Max.
Value
Unit
65
°C/W
9105A-04.TBL
THERMAL DATA
HORIZONTAL SECTION
Operating Conditions
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VCO
R0min
Oscillator Resistor Min Value (Pin 11)
6
C0min
Oscillator Capacitor Min Value (Pin 10)
390
Fmax
Maximum Oscillator Frequency
HsVR
Horizontal Sync Input Voltage (Pin 17)
0
kΩ
pF
150
kHz
5.5
V
INPUT SECTION
MinD
Minimum Input Pulses Duration (Pin 17)
Mduty
Maximum Input Signal Duty Cycle (Pin 17)
µS
0.7
25
%
5
mA
20
20
mA
mA
6
V
I5m
Maximum Input Peak Current (Pin 5)
HOI1
HOI2
Horizontal Drive Output Max Current
Pin 20
Pin 21
Sourced current
Sink current
DC CONTROL VOLTAGES
DCadj
DC Voltage on DC Controls (Pins 4-15)
VREF-H = 8V
2
5/31
9105A-05.TBL
OUTPUT SECTION
TDA9105A
HORIZONTAL SECTION (continued)
Electrical Characteristics (VCC = 12V, Tamb = 25°C)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
10.8
12
13.2
V
45
65
mA
8
8.6
V
5
mA
SUPPLY AND REFERENCE VOLTAGES
VCC
Supply Voltage (Pin 18)
ICC
Supply Current (Pin 18)
See Figure 1
VREF-H
Reference Voltage for Horizontal Section (Pin 7)
I = 2mA
IREF-H
Max Sourced Current on V REF-H (Pin 7)
VREF-V
Reference Voltage for Vertical Section (Pin 26)
IREF-V
Max Sourced Current on V REF-V (Pin 26)
I = 2mA
7.4
7.4
8
8.6
V
5
mA
0.8
V
INPUT SECTION/PLL1
VINTH
Horizontal Input Threshold Voltage (Pin 17)
Low level voltage
High level voltage
VVCO
VCO Control Voltage (Pin 12)
VREF-H = 8V
VCOG
VCO Gain, dF/dV (Pin 12)
R0 = 6.49kΩ, C0 = 680pF
Horizontal Phase Adjust (Pin 15)
% of Horizontal period
Hph
f0
CR
Free Running Frequency (adjustable by changing R0) R0 = 6.49kΩ, C0 = 680pF
PLL1 Capture Range
2
PLL 1 Inhibition (Pin 14)
(Typ. Threshold = 1.6V)
V
17
kHz/V
±12.5
25
27
%
29
kHz
R0 = 6.49kΩ, C0 = 680pF
See conditions on Fig. 1
Fh Min
Fh Max
PLLinh
1.6 to 6.2
PLL ON
PLL OFF
f0
3.7 x f0
V14
V14
IHLock0
Max Output Current on HLock Output
I2
VHLock0
Low Level Voltage on HLock Output
V2 with I2 = 10mA
kHz
kHz
0.8
V
V
10
mA
0.5
V
2
0.25
SECOND PLL AND HORIZONTAL OUTPUT SECTION
Hjit
HDmin
HDmax
Flyback Input Threshold Voltage (Pin 5)
See Figure 14
Horizontal Jitter
See Application Diagram
(Pins 8-9)
Horizontal Drive Output Duty-cycle
(Pin 20 or 21) (see Note)
Minimum
Maximum
V4 = 2V
V4 = 6V
V4 = VREF - 500mV
HDvd
Horizontal Drive Low Level Output Voltage
HDem
Horizontal Drive High Level Output Voltage Pin 21 to VCC,
(output on Pin 20)
IOUT = 20mA
0.60
31
54.5
Pin 20 to GND,
V21-V20 , IOUT = 20mA
XRAYth X-RAY Protection Input Threshold Voltage (Pin 16)
0.70
V
80
ppm
33.2
57
61.5
35.5
59.5
%
%
%
1.1
1.7
V
9.5
10
TBD
8
ISblkO
Maximum Output Current on Composite Blanking I22
Output
VSblkO
Low-Level Voltage on Composite Blanking Output V22 with I22 = 10mA
(Blanking ON)
0.25
Vphi2
Internal Clamping Voltage on 2nd PLL Loop Filter Vmin
Output (Pin 3)
Vmax
1.6
4.0
VOFF
Threshold Voltage to Stop H-out, V-out and to V4
activate BLKout (OFF mode when V4 < VOFF)
(Pin 4)
VSCinh
Supply Voltage to Stop H-out, V-out when
VCC < VSCinh (Pin 18)
TBD
V
10
mA
0.5
V
V
V
1
TBD
7.5
Note : If H-drive is taken on Pin 20 (Pin 21 connected to supply), H-D is the ratio of low level duration t o horizontal period.
If H-drive is taken on Pin 21 (Pin 20 grounded), H-D is the ratio of high level duration to horizontal period.
In both cases, H-D period driving horizontal scanning transistor off.
6/31
V
V
V
9105A-06.TBL
FBth
TDA9105A
Symbol
VSVR
VEWM
VDHPCM
VDHPCm
VDFm
Rload
Parameter
Vertical Sync Input Voltage (Pin 34)
Maximum EW Output Voltage (Pin 37)
Maximum Dynamic Horizontal Phase Control Output Voltage (Pin 40)
Minimum Dynamic Horizontal Phase Control Output Voltage (Pin 40)
Minimum Vertical Dynamic Focus Output Voltage (Pin 1)
Minimum Load for less than 1% Vertical Amplitude Drift (Pin 25)
Min.
0
Typ.
Max.
5.5
6.5
6.5
0.9
0.9
65
Unit
V
V
V
V
V
MΩ
9105A-07.TBL
VERTICAL SECTION
Operating Conditions
Electrical Characteristics (VCC = 12V, Tamb = 25°C)
IBIASP
IBIASN
VSth
VSBI
VRB
Parameter
VRT
VRTF
Voltage at Ramp Top Point (with Sync) (Pin 27)
Voltage at Ramp Top Point (without Sync)
(Pin 27)
VSW
VSmDut
VFRF
Minimum Vertical Sync Pulse Width (Pin 34)
Vertical Sync Input Maximum Duty-cycle
(Pin 34)
Vertical Sawtooth Discharge Time Duration
(Pin 27)
Vertical Free Running Frequency
ASFR
RAFD
AUTO-SYNC Frequency (see Note 1)
Ramp Amplitude Drift Versus Frequency
VSTD
Rlin
Ramp Linearity on Pin 30
Vpos
Vertical Position Adjustment Voltage (Pin 32)
IVPOS
Max Current on Vertical Position Control Output
(Pin 32)
Vertical Output Voltage (Pin 30)
(peak-to-peak voltage on Pin 30)
VOR
VOUTDC
V0I
dVS
Ccorr
Test Conditions
BiasCurrent (currentsourced by PNPBase)(Pin28) For V28 = 2V
Bias Current (Pins 29-31) (sinked by NPN base) For V31 = 6V, V 29 = 6V
Vertical Sync Input Threshold Voltage (Pin 34) High-level
Low-level
Vertical Sync Input Bias Current
V34 = 0.8V
(Current Sourced by PNP Base)
Voltage at Ramp Bottom Point (Pin 27)
DC Voltage on Vertical Output (Pin30)
Vertical Output Maximum Current (Pin 30)
Max Vertical S-Correction Amplitude
V28 = 2V inhibits S-CORR
V28 = 6V gives maximum S-CORR
Max Vertical C-Correction Amplitude
Min.
Typ.
Max.
Unit
0.8
µA
µA
V
V
2
0.5
2
1
µA
2/8
VREF-V
5/8
VRT-0.1
VREF-V
V
5
15
µS
%
With 150nF cap
70
µS
V28 = 2V, V29 grounded,
Measured on Pin 27
Cosc (Pin27) = 150nF
100
Hz
With C27 = 150nF
V31 = 6V, C27 = 150nF
50Hz < f < 185Hz
V28, V29 grounded
V33 = 2V
V33 = 4V
V33 = 6V
50
185
100
0.5
3.65
3.2
3.5
3.8
%
3.3
±2
V31 = 2V
V31 = 4V
V31 = 6V
See Note 2
3.75
2
3
4
7/16
VFly Th
VFly Inh
Vertical Flyback Threshold (Pin 36)
Inhibition of Vertical Flyback Input (Pin 36)
See Note 1
IBIAS DCIN
Bias Current (Pin 35) (sourced by PNP base)
For V35 = V32
V
V
V
mA
2.2
V
V
V
VREF-V
mA
±5
∆V/V30pp at T/4
∆V/V30pp at 3T/4
V29 = 2V
V29 = 4V
V29 = 6V
Hz
ppm/Hz
-4
+4
TBD
TBD
%
%
TBD
TBD
-1.6
0
1.6
%
%
%
1
TBD
VREF- 0.5
V
V
2
µA
Notes : 1. It is the frequency range for which the VERTICAL OSCILLATOR will automatically synchronize, using a single capacitor value on
Pin 27 and with a constant ramp amplitude.
2. Typically 3.5V for Vertical reference voltage typical value (8V).
7/31
9105A-08.TBL
Symbol
TDA9105A
VERTICAL SECTION (continued)
East/West Function
Parameter
Test conditions
Min.
Typ.
Max.
Unit
EWDC
DC Output Voltage (see Figure 2)
V33 = 4V, V35 = V32 ,
V38 = 4V, V23 = 4V
2.5
V
TDEWDC
DC Output Voltage Thermal Drift
See Note 2
100
ppm/°C
Parabola Amplitude
V28 = 2V, V29 grounded,
V31 = 6V, V33 = 4V,
V35 = V32, V38 = 4V, V23 = 4V
V39 = 6V
V39 = 2V
1.70
0
V
V
0.45
1.0
1.7
V
V
V
EW para
EWtrack
Keytrack
KeyAmp
Parabola Amplitude versus V-AMP
Control (tracking between V-AMP
and E/W)
TBD
V28 = 2V, V29 grounded
V33 = 4V, V35 = V32
V38 = 4V, V39 = 6V, V23 = 4V
V31 = 2V
V31 = 4V
V31 = 6V
= 4V, V28 = 2V, V29 grounded,
= 6V, V38 = 4V, V39 = 6V
= 2V, V35 = V32
= 6V, V35 = V32
Keystone versus V-POS control
(tracking between V-POS and EW)
A/B Ratio
B/A Ratio
V23
V31
V33
V33
Keystone Amplitude Adjustment
V23 = 4V, V31 = 6V, V39 = 2V
V38 = 4V
V38 = 2V
V38 = 6V
0.54
0.54
0
1.3
1.3
V
V
V
9105A-09.TBL
Symbol
Notes : 1. When Pin 36 > VREF - 0.5V, Vfly input is inhibited and vertical blanking on composite blanking output is replaced by vertical sawtooth
discharge time.
2. These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes
characterization on batches comming from corners of our processes and also temperature characterization.
Dynamic Horizontal Phase Control Function
Parameter
Test Conditions
DC Ouput Voltage (see Figure 3)
V33 = 4V, V35 = V32 , V41 = 4V
TDDHPCDC
DC Output Voltage Thermal Drift
See Note
Side Pin Balance Parabola Amplitude
(see Figure 3)
V28 = 2V, V29 grounded,
V31 = 6V, V33 = 4V,
V35 = V32, V41 = 4V
V42 = 6V
V42 = 2V
SPBpara
SPBtrack
ParAdj
Side Pin balance Parabola Amplitude
versus V-amp Control (tracking
between V-amp and SPB )
Parallelogram Adjustment Capability
A/B ratio (see Figure.3)
B/A ratio
Partrack
8/31
Parallelogram versus V-pos Control
(tracking between V-pos and DHPC)
A/B ratio
B/A ratio
Min.
TBD
V28 = 2V, V29 grounded,
V33 = 4V, V35 = V32 ,
V41 = 4V, V42 = 6V
V31 = 2V
V31 = 4V
V31 = 6V
V28 = 2V, V29 grounded,
V31 = 6V, V33 = 4V,
V35 = V32, V42 = 6V
V41 = 6V
V41 = 2V
V28
V31
V33
V33
= 2V, V29 grounded,
= 6V, V41 = 4V, V42 = 6V
= 2V, V35 = V32 ,
= 6V, V35 = V32
Typ.
Unit
V
100
ppm/°C
+1.45
- 1.45
0.36
0.82
1.45
TBD
TBD
Max.
4
TBD
V
V
V
V
V
0.12
0.12
0.53
0.53
9105A-10.TBL
Symbol
DHPCDC
TDA9105A
VERTICAL SECTION (continued)
Vertical Dynamic Focus Function
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VDF DC
DC Output Voltage (see Figure 4)
V33 = 4V, V35 = V32
TDVDFDC
DC Output Voltage Thermal Drift
See Note
VDFAMP
Parabola Amplitude versus V-amp
(tracking between V-amp and VDF)
(see Figure 4)
V28 = 2V, V29 grounded,
V33 = 4V, V35 = V32,
V31 = 2V
V31 = 4V
V31 = 6V
Parabola Assymetry versus V-pos
Control (tracking between V-pos
and VDF)
A/B ratio
B/A ratio
V28 = 2V, V29 grounded,
V31 = 6V,
Corner Amplitude Adjustment
V31 = 4V, V38 = 4V, V39 = 2V
V23 = 2V
V23 = 4V
V23 = 6V
0.55
0
0.55
VPP
VPP
VPP
V23 = 6V
V31 = 2V
V31 = 4V
V31 = 6V
0.2
0.55
1.7
VPP
VPP
VPP
VDFKEY
Corner
Amplitude
Tracking Corner with V-amp
V33 = 2V, V35 = V32,
V33 = 6V, V35 = V32
6
V
100
ppm/C
-0.84
-1.78
-3.14
-0.72
-1.57
-2.85
-0.6
-1.36
-2.56
0.42
0.42
0.54
0.54
0.64
0.64
V
V
V
Note : These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes
characterization on batches comming from corners of our processes and also temperature characterization.
9/31
9105A-11.TBL
Symbol
220nF
9105A-03.EPS
2.2µF
2.2µF
14
TDA9105A
34
24
26
PULSE
SHAPER
POL
DETECT
PLL1
INHIB
13
PULSE
SHAPER
POL
DETECT
V-REF
17
6
7
10nF
12
1µF
28
29
S
CORR
680pF 1%
150nF
1%
27
25
6.49kΩ 0.1%
31
V-MID
470nF
1%
VERT OSC
RAMP
GENERATOR
8
47nF
5
47nF
PHASE
COMP
9
30
VIDEO UNLOCK
11
VCO
10
LOCK
UNLOCK
IDENT
V-REF
PHASE
FREQUENCY
COMP
15
1.8kΩ
4.7µF
10/31
33
3
10kΩ
32
V-SYNC
H-FLY
PHASE
SHIFTER
2
16
VS
36
BLK
GEN
10kΩ
VCC
22
1kΩ
20
X
2
H
OUTPUT
BUFFER
21
SAFETY
PROCESSOR
PULSE
SHAPER
4
VCC
35
18
12V VCC
X2
42
40
41
39
37
38
1
19
10kΩ
10kΩ
10kΩ
23 CORNER
100nF
VCC
TDA9105A
Figure 1 : Testing Circuit
2.2µF
22nF
TDA9105A
Figure 2 : Exampleof VerticalPositionTrackingEffect
Figure 3 : Keystone Effect on E/W Output
V38 = 6V
B
EWPARA
EWDC
Figure 5 : E/W Output with or without Corner
V23 = 6V
Figure 6 :
without
corner
with corner
amplitude
V23 < 4V
9105A-06.EPS
V23 = 2V
with corner
amplitude
V23 > 4V
Dynamic Horizontal Phase Control
Output
9105A-07.EPS
Figure 4 : Corner Effect on E/W Output
V38 = 2V
9105A-05.EPS
9105A-04.EPS
A
Figure 7 : Vertical Dynamic Focus Function
V42 = 6V
A
B
VDFDC
SPBPARA
V42 = 2V
DHPCDC
9105A-08.EPS
A
VDFAMP
B
9105A-09.EPS
V41 = 6V
V33 = 2V
11/31
TDA9105A
TYPICAL VERTICAL OUTPUT WAVEFORMS
Function
Vertical Size
Vertical
Position
DC
Control
Vertical
DC
In/Out
Control
Pin
31
Output
Pin
Control
Voltage
Specification
Picture Image
2V
2V
6V
4V
30
33
32
35
1
37
40
2V
4V
6V
3.2V
3.5V
3.8V
T hi s t e rm i na l is a Pin
controlling the center position
of g eo m et r ic co r re c ti on
signals. When connected to
Pin 32, “Autotracking” occurs.
2V
25
30
∆V
6V
2V
Vertical
C
Linearity
29
V PP
∆V
= 4%
VPP
VPP
∆V
∆V = 1.6%
V PP
30
∆V
6V
VPP
∆V = 1.6%
V PP
12/31
9105A-13.TBL / 9105A-10.EPS TO 9105A-16.EPS
Vertical
S
Linearity
TDA9105A
TYPICAL GEOMETRY OUTPUT WAVEFORMS
Function
Control
Pin
Output
Pin
Control
Voltage
Specification
Picture Image
V38 = 4V
2V
Trapezoid
Control
38
1.3V
37
6V
1.3V
V39 = 4V
Pin Cushion
Control
2V
39
2.5V
0V
37
1.7V
6V
V42 = 4V
Parrallelogram
Control
41
2V
4V
3V
6V
4V
3V
40
V41 = 4V
2V
Side Pin
Balance
Control
42
4V
1.45V
40
1.45V
6V
Corner
1
23
37
9105A-14.TBL / 9105A-17.EPS TO 9105A-27.EPS
6V
Vertical
Dynamic
Focus
3V
1.7V
2.5V
Note : The specification of Output voltage is indicated on 4VPP vertical sawtooth output condition.The output voltage depends on vertical
sawtooth output voltage.
13/31
TDA9105A
OPERATING DESCRIPTION
GENERAL CONSIDERATIONS
Power Supply
In order to have a good tracking with the voltage
reference value, it’s better to maintain the control
voltages between VREF/4 and 3/4 ⋅ VREF .
The input current of the DC control inputs is typically very low (about a few µA). Depending on the
internal structure of the inputs, it can be positive or
negative (sink or source).
The typical value of the power supply voltage VCC
is 12V. Perfect operation is obtained if VCC is maintained in the limits : 10.8V → 13.2V.
In order to avoid erratic operation of the circuit
during the transient phase of VCC switching on, or
switching off, the value of VCC is monitored and the
outputs of the circuit are inhibited if VCC < 7.6 typically.
In order to have a verygood powersupply rejection,
the circuit is internally powered by several internal
voltage references (The unique typical value of
which is 8V). Two of these voltage references are
externally accessible, one for the vertical part and
one for the horizontal part. These voltage references can be used for the DC control voltages
applied on the concerned pins by the way of potentiometers or digital to analog converters (DAC’s).
Furthermore it is necessaryto filter the a.m. voltage
references by the use of external capacitor connected to ground, in order to minimize the noise
and consequently the “jitter” on vertical and horizontal output signals.
HORIZONTAL PART
Input section
The horizontal input is designed to be sensitive to
TTL signals typically comprised between 0 and 5V.
The typical threshold of this input is 1.6V.This input
stage uses an NPN differential stage and the input
current is very low.
Figure 9 : Input Structure
DC Control Adjustments
The circuit has 10 adjustment capabilities : 2 for the
horizontal part, 2 for the E/W correction, 4 for the
vertical part, 2 for the Dynamic Horizontal phase
control.
The corresponding inputs of the circuit has to be
driven with a DC voltage typically comprised between 2 and 6V for a value of the internal voltage
reference of 8V.
Figure 8 :
1.6V
9105A-29.EPS
H-SYNC
Concerning the duty cycle of the input signal, the
following signals may be applied to the circuit.
Using internal integration, both signals are recognized on conditionthat Z/T ≤ 25%. Synchronisation
occurs on the leading edge of the internal sync
signal. The minimum value of Z is 0.7µs.
Figure 10
Example of Practical DC Control
Voltage Generation
DC Control
Voltage
9105A-28.EPS
PWM
DAC
Output
9105A-30.EPS
VREF
14/31
PLL1
The PLL1 is composed of a phase comparator, an
external filter and a Voltage Controlled Oscillator
(VCO).
The phase comparator is a “phasefrequency”type,
designed in CMOS technology. This kind of phase
detector avoids locking on false frequencies. It is
followed by a “charge pump”, composed of 2 current sources sink and source (I = 1mA typ.)
TDA9105A
OPERATING DESCRIPTION (continued)
Figure 11 : Principle Diagram
H-LOCKCAP
13
H-LOCKOUT
2
PLL1INHIB PLL1F R0
14
12
11
C0
10
LOCKDET
High
CHARGE
PUMP
COMP1
E2
PLL
INHIBITION
VCO
Low
H-POS
15
OSC
9105A-31.EPS
H-SYNC 17
INPUT
INTERFACE
3.2V
PHASE
ADJUST
tive frequency range has to be smaller (e.g. 30kHz
→ 85kHz). In the absence of synchronisationsignal
the control voltageis equal to 1.6V typ.and the VCO
oscillates on its lowest frequency (free frequency).
The synchro frequencyhasto be alwayshigherthan
the free frequencyand a margin has to be taken. As
an example for a synchro range from 30kHz to
85kHz, the suggested free frequency is 27kHz.
Figure 12
PLL1F
12
9105A-32.EPS
The dynamic behaviour of the PLL is fixed by an
external filter which integrates the current of the
charge pump. A “CRC” filter is generally used (see
Figure 9).
PLL1 is inhibited by applying a high level on Pin 14
(PLLinhib)which is a TTL compatibleinput. The inhibition results from the opening of a switch located between the charge pump and the filter (see Figure 8).
The VCO uses an external RC network. It delivers
a linear sawtooth obtained by charge and discharge of the capacitor, by a current proportionnal
to the current in the resistor. typical thresholds of
sawtooth are 1.6V and 6.4V (see Figure 10).
The control voltage of the VCO is typically comprised between 1.6V and 6V (see Figure 10). The
theoreticalfrequencyrangeof thisVCO isin the ratio
1 → 3.75, but due to spread and thermal drift of
external componentsand the circuit itself, the effecFigure 13 : Details of VCO
I0
6.4V
2
RS
FLIP FLOP
I0
Loop
Filter 12
4 I0
1.6V
2
10
R0
6.4V
9105A-33.EPS
11
(1.6V < V12 < 6V)
C0
1.6V
0
0.75T T
15/31
TDA9105A
OPERATING DESCRIPTION (continued)
The PLL1 ensures the coincidence between the
leading edge of the synchro signal and a phase
reference obtained by comparison between the
sawtooth of the VCO and an internal DC voltage
adjustable between 2.4V and 4V (by Pin 15). So a
±45° phase adjustment is possible (see Figure 11).
Figure 14 : PLL1 Timing Diagram
H Osc
Sawtooth
0.75T
0.25T
6.4V
2.4V<Vb<4V
Vb
1.6V
Phase REF1
Phase REF1 is obtained by comparison between the sawtooth and
a DC voltage adjustable between 2.4V and 4V. The PLL1 ensures
the exact coincidence between the signals phase REF and
HSYNS. A ± T/8 phase adjustment is possible.
The two VCO threshold can be filtered by connecting capacitor on Pins 8-9.
The TDA9103 also includes a LOCK/UNLOCK
identification block which senses in real-time
9105A-34.EPS
H Synchro
whether the PLL is locked on theincoming horizontal sync signal or not. The resulting information is
available on HLOCKOUT output (Pin 2). The block
diagram of the LOCK/UNLOCK function is described in Figure 12.
The NOR1 gate is receiving the phase comparator
output pulses (which also drive the charge pump).
When the PLL is locked, on point A there is a very
small negative pulse (100ns) at each horizontal
cycle, so after R-C filter, there is a high level on
Pin 13 which force HLOCKOUT to high level (provided that HLOCKOUT is pulled up to VCC).
When the PLL is unlocked, the 100ns negative
pulse on A becomesmuch larger and consequently
the average level on Pin 13 will decrease. When it
reaches 6.5V, point B goes to low level forcing
HLOCKOUT output to “0”.
The status of Pin 13 is approximately the following :
- Near 0V when there is no H-SYNC,
- Between 0 and 4V with H-SYNC frequency different from VCO,
- Between 4 and 8V when H-SYNC frequency
= VCO frequency but not in phase,
- Near to 8V when PLL is locked.
It is important to notice that Pin 13 is not an output
pin and must only be used for filtering purpose (see
Figure 12).
Figure 15 : LOCK/UNLOCK Block Diagram
2
16/31
NOR1
A
20kΩ H-Lock CAP
13
6.5V
220nF
B
HLOCKOUT
9105A-35.EPS
From
Phase
Comparator
TDA9105A
OPERATING DESCRIPTION (continued)
PLL2
The PLL2 ensures a constant position of the
shaped flyback signal in comparison with the sawtooth of the VCO (see Figure 13).
The phase comparator of PLL2 is followed by a
charge pump with a ±0.5mA (typ.) output current.
Theflyback input is composedof an NPNtransistor.
This input has to be current driven.
The maximum recommanded input current is 2mA
(see Figures 14 and 15).
Figure 16 : PLL2 Timing Diagram
H Osc
Sawtooth
0.75T
0.25T
6.4V
4V
1.6V
Figure 17 : Flyback Input Electrical Diagram
Flyback
Internally
Shaped Flyback
400Ω
Q1
HFLY 5
H Drive
9105A-36.EPS
Duty Cycle
The duty cycle of H-drive is adjustable between 30% and 50%.
9105A-37.EPS
20kΩ
Ts
GND 0V
Figure 18 : Dual PLL Block Diagram
PLL1INHIB Filter R0 C0
14
12 11 10
C Lockdet HLOCKOUT
2
13
LOCKDET
High
INPUT
INTERFACE
E2
Adjust
Rapcyc
4
CHARGE
PUMP
COMP1
PLL
INHIBITION
Horizontal
Adjust
15
Low
Cap
PHi2
3
PHASE
ADJUST
VCO
OSC
3.2V
4V
High
RAP
CYC
CHARGE
PUMP
Low
VA
COMP2
EN
FLYBACK 5 Flyback
VB
PWM
LOGI
PWM
BUFFER
21 SortCOLL
20 SortEM
17/31
9105A-38.AI
Horizontal
17
Input
TDA9105A
OPERATING DESCRIPTION (continued)
X-RAY PROTECTION : the activation of the X-ray
protectionis obtained by application of a high level
on the X-ray input (>8V). Consequences of X-ray
protection are :
- Inhibition of H drive output,
- Activation of composite blanking output.
The reset of this protection is obtained by VCC
switch off (see Figure 17).
Figure 19 : Output stage simplified diagram,
showing the two possibilities of
connection
21 V CC
H-DRIVE
20
VCC
21
H-DRIVE
Outputs inhibition
The application of a voltage lower than 1V (typ.) on
Pin 4 (duty cycle adjust) inhibits the horizontal and
vertical outputs. This is not memorised.
20
9105A-39.EPS
Output Section
The H-drive signal is transmitted to the output
through a shaping block ensuring a duty cycle
adjustable from 30% to 50%. In order to ensure a
reliable operation of the scanning power part, the
output is inhibited in the following circumstances :
- VCC too low,
- Xray protection activated,
- During the horizontal flyback,
- Output voluntarily inhibited through Pin 4.
The output stage is composed of a Darlington NPN
bipolartransistor. Both the collector and the emitter
are accessible (see Figure 16).
Theoutput Darlington is in off-statewhen the power
scanning transistor is also in off-state.
The maximum output current is 20mA, and the
correspondingvoltagedrop of theoutput darlington
is 1.1V typically.
It is evident that the power scanning transistor
cannot be directly driven by the integrated circuit.
An interface has to be designed between the circuit
and the power transistor which can be of bipolar or
MOS type.
Figure 20 : Safety Functions Block Diagram
VCC Checking
VCC
REF
XRAY Protection
XRAY
VCC off
S
R
Q
H OUTPUT
INHIBITION
Inhibition
H-Duty cycle
1V
V OUTPUT
INHIBITION
Flyback
0.7V
V sawtooth
retrace time
H-fly
18/31
LOGIC
BLOCK
to 2ND PLL
9105A-40.EPS
V-fly
Vsync
COMPOSITE
BLANKING
TDA9105A
OPERATING DESCRIPTION (continued)
Geometric Corrections
The principle is represented in Figure 20.
Figure 21 : Geometric Corrections Principle
Analog
Multiplier
X2
Vertical
Dynamic
Focus
Output
Vertical
Ramp
VDCIN
EW Amp
VDCIN
EW
Output
Keystone
X2
Corner
VDCIN
Side Pin
Balance
Output
Key Balance
Starting from the vertical ramp, a parabola shaped
is generatedfor E/W correction, dynamichorizontal
phase control correction, and vertical dynamic Focus correction.
The core of the parabola generator is an analog
multiplier. The output current of which is equal to :
∆I = k (VRAMP - VDCIN)2.
Where VRAMP is the vertical ramp, typically comprised between 2 and 5V, VDCIN is a vertical DC
input adjustable in the range 3.2V → 3.8V in order
to generate a dissymmetric parabola if required
(keystone adjustment).
In order to keep good screen geometry for any end
user preferences adjustment we implemented the
possibility to have “geometry tracking”. To enable
9105A-41.EPS
Sidepin Amp
the “tracking” function, the VDCOUT must be connected to VDCIN.
It is possible to inhibit VPOS tracking by applying a
fixed DC voltage on the VDCIN Pin.
This DC voltage in that case must be taken from
the vertical reference and adjusted to 3.5V with an
external bridge resistor.
Due to large output stages voltage range (E/W,
BALANCE, FOCUS), the combination of tracking
function with maximum vertical amplitude max. or
min. vertical position and maximumgain on the DC
control inputs may leads to the output stages saturation. This must be avoided by limiting the output
voltage by apropriate DC control voltages.
For E/W part and DynamicHorizontal phasecontrol
part, a sawtooth shaped differential current in the
followingform is generated: ∆I’ = k’(VRAMP -VDCIN).
Then ∆I and ∆I’ are added together and converted
into voltage.
For E/W part corner purpose, the following current
form is generated and added before voltage conversion ∆I” = k” (V RAMP - VDCIN)4.
These two parabola are respectively available on
Pin 37 and Pin 40 by the way of an emitter follower
which has to be biased by an external resistor
(10kΩ). They can be DC coupled with external
circuitry.
EW
VOUT = 2.5V + K1’ (VRAMP - VDCIN)
+ K1 (VRAMP - VDCIN)2
+ K1“ (VRAMP - VDCIN)4
K1 is adjustable by EW amp control (Pin 39)
K1’ is adjustable by KEYST control (Pin 38)
Dyn. Hor.
VOUT = 4V + K2’ (VRAMP - VDCIN)
Phase Control
+ K2 (VRAMP - VDCIN)2
K2 is adjustable by SPB amp control (Pin 42)
K2’ is adjustable by KEYBAL control (Pin 41)
For vertical dynamic focus part, only a constant
amplitude parabola is generated in the form :
VOUT = 6V - 0.75 x (VAMP - VDCIN)2.
The output connectionis the same as the two other
corrections (Pins 37-40).
It is important to note that the parasitic parabola
during the discharge of the vertical oscillator capacitor is suppressed.
19/31
TDA9105A
OPERATING DESCRIPTION (continued)
VERTICAL PART
Figure 22 : Vertical Part Block Diagram
CHARGE CURRENT
TRANSCONDUCTANCE
AMPLIFIER
REF
27
25
OSC
CAP
DISCH.
V_SYNC 34
SYNCHRO
SAMPLING
SAMP.
CAP
S CORRECTION
OSCILLATOR
28 VS_AMP
POLARITY
29 COR_C
C CORRECTION
Vlow
Sawth.
Disch.
30 VERT_OUT
31
VERT_AMP
PARABOLA
GENERATOR
37 EW_OUT
38
EW_CENT
39
23
EW_AMP
CORNER
40 SPB_OUT
42
SPB_AMP
9105A-42.EPS
41
SPB_CENT
1 V_FOCUS
The vertical part generates a fixed amplitude ramp
which can be affected by a S and C correction
shape. Then, the amplitudeof thisramp is adjusted
to drive an external power stage.
The internal reference voltage used for the vertical
part is available between Pin 26 and Pin 24. It can
be used as voltagereference for any DC adjusment
20/31
to keep a high accuracy to each adjustment. Its
typical value is :
V26 = VREF = 8V.
The charge of the external capacitor on Pin 27
(VCAP) generates a fixed amplitude ramp between
the internal voltages, VL (VL = VREF/4) and VH
(VH = 5/8 ⋅ VREF).
TDA9105A
OPERATING DESCRIPTION (continued)
VERTICAL PART (continued)
Function
When the synchronisation pulse is not present, an
internal current source sets the free running frequency. For an external capacitor, COSC = 150nF,
the typical free running frequency is 100Hz.
Typical free running frequency can be calculated
by :
f0 (Hz) = 1.5 ⋅ 10−5 ⋅
1
COSC (nF)
A negative or positive TTL level pulse applied on
Pin 34 (VSYNC) can synchronise the ramp in the
frequencyrange [fmin, fmax]. This frequencyrange
depends on the external capacitor connected on
Pin 27. A capacitor in the range [150nF, 220nF] is
recommanded for application in the following
range : 50Hz to 120Hz.
Typical maximum and minimum frequency, at 25°C
and without any correction (S correction or C correction), can be calculated by :
fmax = 2.5 ⋅ f0 and f min = 0.33 ⋅ f0
If S or C corrections are applied, these values are
slighty affected.
If an external synchronisation pulse is applied, the
internal oscillator is automaticaly caught but the
amplitude is no more constant. An internal correction is activated to adjust it in less than half a
second: the highest voltage of the ramp on Pin 27
is sampled on the samplingcapacitorconnected on
Pin 25 (VAGCCAP) at each clock pulse and a
transconductance amplifier generates the charge
current of the capacitor. The ramp amplitude becomes again constant.
It is recommandedto use a AGC capacitor with low
leakage current. A value lower than 100nA is mandatory.
Pin 36, Vfly is the vertical flyback input used to
generate the composite blanking signal. If Vfly is
not used, (VREF - 0.5), at minimum, must be connected to this input.
DC Control Adjustments
Then, S and C correction shapes can be added to
this ramp. This frequency independent S and C
corrections are generated internally; their ampli-
tude are DC adjustable on Pin 28 (VSAMP) and
Pin 29 (COR-C).
S correction is non effective for VSAMP lower than
VREF/4 and maximum for VSAMP = 3/4 ⋅ VREF.
C correction is non effective for COR-C grounded
and maximum for :
COR-C = VREF /4 or COR-C = 3/4 ⋅ VREF.
Endly, the amplitude of this S and C corrected ramp
can be adjusted by the voltage applied on Pin 31
(VAMP). The adjusted ramp is available on Pin 30
(VOUT) to drive an external power stage. The gain
of this stageis typically±30% when voltage applied
on Pin 31 is in the range VREF/4 to 3/4 ⋅ VREF. The
DC value of this ramp is kept constant in the
frequency range , for any correction applied on it.
Its typical value is : VDCOUT = VMID = 7/16 ⋅ VREF.
A DC voltage is available on Pin 32 (VDCOUT). It is
driven by the voltage applied on Pin 33 (VPOS)
For a voltage control range between VREF/4 and
3/4 ⋅ VREF, the voltage available on Pin 32 is :
VDCOUT = 7/16 ⋅ VREF ± 300mV.
So, the VDCOUT voltage is correlated with DC value
of VOUT. It increases the accuracy when temperature varies.
Basic Equations
In first approximation,the amplitude of the ramp on
Pin 30 (VOUT) is :
VOUT - VMID = (VCAP - VMID) [1 + 0.16 ⋅ (VAMP - VREF/2)]
with VMID = 7/16 ⋅ VREF ; typically 3.5V
VMID is the middle value of the ramp on Pin 27
VCAP = V27 , ramp with fixed amplitude.
On Pin 32 (VDCOUT), the voltage (in volts) is calculated by : VDCOUT =VMID + 0.16 ⋅ (VPOS - VREF/2).
VPOS is the voltage applied on Pin 33.
The current available on Pin 27
(when VSAMP = VREF/4) is :
IOSC = 3/8 ⋅ VREF ⋅ COSC ⋅ f
COSC : capacitor connected on Pin 27
f synchronisation frequency
The recommanded capacitor value on Pin 25
(VAGC) is 470nF. Its ensures a good stability of the
internal closed loop.
21/31
TDA9105A
INTERNAL SCHEMATICS
Figure 23
Figure 27
Href
9105A-47.EPS
5
Pins 1-37-40
1mA max
9105A-43.EPS
Figure 28
V CC
Figure 24
V CC
Pins
2-22
N MOS
7
9105A-48.EPS
9105A-44.EPS
10mA max.
Figure 29
Figure 25
Href
8
9105A-45.EPS
9105A-49.EPS
3
Figure 30
Figure 26
9
22/31
9105A-50.EPS
P MOS
9105A-46.EPS
4
TDA9105A
INTERNAL SCHEMATICS (continued)
Figure 31
Figure 35
P MOS
10
9105A-55.EPS
9105A-51.EPS
14
Figure 32
9105A-52.EPS
Figure 36
11
Figure 33
15
P MOS P MOS
9105A-56.EPS
N MOS
Figure 37
9105A-53.EPS
12
16
Figure 34
N MOS
9105A-57.EPS
9105A-54.EPS
13
23/31
TDA9105A
INTERNAL SCHEMATICS (continued)
Figure 40
Figure 38
P MOS
P MOS
N
25
P
17
9105A-60.EPS
N
9105A-58.EPS
P
Figure 41
Figure 39
V CC
21
20
26
9105A-61.EPS
9105A-59.EPS
20mA max.
Figure 42
V REF
V REF
V CC
V REF
N
P
N MOS
24/31
9105A-62.EPS
27
TDA9105A
INTERNAL SCHEMATICS (continued)
Figure 43
Figure 47
VCC
V REF
32
9105A-67.EPS
9105A-63.EPS
28
Figure 48
VREF
Figure 44
29
V REF
N MOS
9105A-64.EPS
33
9105A-68.EPS
Figure 45
VCC
Figure 49
VREF
30
9105A-69.EPS
9105A-65.EPS
34
Figure 50
Figure 46
VREF
31
9105A-66.EPS
9105A-70.EPS
35
25/31
TDA9105A
INTERNAL SCHEMATICS (continued)
Figure 51
Figure 52
VREF
VREF
P MOS
26/31
9105A-71.EPS
36
9105A-72.EPS
Pins
23
38-39
41-42
HOUT
VSYNC
BLK
J19
1
1
J3
HSYNC
R73 10kΩ
TP5
HFLY
XRAY IN
9105A-73.EPS
J5
TP6
J2
TP2
HFLY 1
J18
J25
DYN 1
FOCUS
CON1
R74 10kΩ
TP7
TP4
C8
100µF
+12V
TP3
10kΩ
R33
10kΩ
R71
SW1
on
5.6kΩ
R91
+
S1
off
+
C9
100nF
C36
1µF
+
HDF
R2 120kΩ
C52
C34
1µF
R84
47kΩ
R5 120kΩ
R3 10kΩ
R1 3.9kΩ
1N4148
D4
R90 1Ω
TP14
R88
10kΩ
R83 1kΩ
R6 10kΩ
C6
220nF
C3
10nF
R7 3.9kΩ
C48
47nF
C50
1nF
24
23
22
20
21
25
26
27
28
29
30
31
32
33
34
35
19
18
17
16
15
14
13
12
11
10
9
8
36
37
6
7
38
5
39
4
41
40
T
D
A
9
1
0
5
IC1
TP13
42
PINCSH
3
2
1
C39
1µF
R10 3.9kΩ
6.49kΩ 1%
R32
680pF 5%
HREF
C45
220pF
C1
22nF
TP12
R31 1.8kΩ
+
+
R87
10kΩ
4.7kΩ
R89
R80 2.7kΩ
C7
4.7µF +
R9 10kΩ
C35
1µF
R11 120kΩ
SBPAMP
C2
C30
47µF
47nF
C51
15nF
C54
+12V
330kΩ
15kΩ
+
R94
HREF
R8 120kΩ
R93
R4 3.9kΩ
C29
100nF
HSHIFT
R12 10kΩ
KEYBAL
R17 120kΩ
0/5V to 2/6V INTERFACE
R16 3.9kΩ
C4
C5
100nF
2 to 6V
470nF
C37 1µF
+
VSHIFT
R13 3.9kΩ
R15 10kΩ
R20 120kΩ
+
C28
47µF
V REF
C38 1µF
+
150nF C27
TP1
KEYST
R14 120kΩ
+12V
R18 10kΩ
J3b
R19 3.9kΩ
R21 10kΩ
R23 120kΩ
R22 3.9kΩ
C42 1µF
+
C43 1µF
+
VSIZE
VREF
1%
33.2kΩ
R82
1%
43.2kΩ
R81
CCOR
C40 1µF
+
R25 3.9kΩ
1 2 3 4 5 6 7
R27 10kΩ
R29 120kΩ
J2b
R24 10kΩ
R26 120kΩ
1 2 3 4
C41 1µF
+
V REF
SCOR
R28 3.9kΩ
J1b
R30 10kΩ
1 2 3 4
C53
1 µF
R35
C11
470pF
1
7
2
IC2
TDA8172
5
3
C14
470µ F
4
6
D1
1N4004
Q1
BC557
Q10
BC547
R44 10Ω
R38 5.6kΩ
-12V
+12V
C10
100nF
R85 15kΩ
1kΩ
+
R54
470Ω
BC557
Q3
R53
1kΩ
E/W POWER STAGE
R51
6.2kΩ
1kΩ
R92
R52
27kΩ
+12V
R86 4.7kΩ
L1
10µH
+12V
VERTICAL
DEFLECTION
STAGE
R36 12kΩ
5.6kΩ
R37
R70 12kΩ
D5
1N4148
27kΩ
R75
HSIZE
+
+
39kΩ
22kΩ
R45
Q2
STD5N20
+
C19
1nF
-12V
HDRIVE
R47b
33Ω 3W
V YOKE
3
1
2
J22
3
1
2
J23
1
J21
E/W
1
J24
HORIZONTAL
DRIVER
STAGE
G 5576-00
T1
1/2W
1Ω
R40
220Ω
1/2W
R39
TP15
TP11
R46
560Ω
R59
2.2Ω 1W
C44
220pF
Q9
TIP122
C32
100nF
R47a
47Ω 3W
C31
100nF
C15
220nF
1.5Ω
R41
C20
100µ F
63V
R57
270kΩ
R56
+ C12 35V
100µF
C13
470µF
BC557
Q4
R55
270kΩ
TDA9105A
APPLICATION DIAGRAMS
Figure 53 : Demonstration Board of TDA9105, modified for TDA9105A
27/31
+12V
9105A-74.EPS
Pc1 47kΩ
28/31
Q
HOUT
Cc1
47pF
+12V
Q
Q
Pc6 47kΩ
Pc7 47kΩ
KEYST
Pc12 47kΩ
SCOR
CCOR
Jc3
Pc5 47kΩ
1 2 3 4 5 6 7
PINCSH
Pc8 47kΩ
Jc2
KEYBAL
SBPAMP
Pc9 47kΩ
1 2 3 4
HDF
Pc4 47kΩ
HSHIFT
VSHIFT
VSIZE
Pc10 47kΩ
Jc1
Cc4
10µF
RC
CX
T
T
Icc1B
14528
Pc11 47kΩ
1 2 3 4
HFLY
Icc1A
14528
Cc5
100nF
R
R C
C X T T
Q
Pc2 47kΩ
Cc2
47pF
Pc3 47kΩ
+12V
1
Jc4
CON1
1
Jc26
Cc4
10µF
HSIZE
+5V
TDA9105A
APPLICATION DIAGRAMS
Figure 54 : Control Board
Pc13 4.7kΩ
TDA9105A
APPLICATION DIAGRAMS
9105A-75.TIF
Figure 55 : PCB Layout
29/31
TDA9105A
APPLICATION DIAGRAMS
9105A-76.EPS
Figure 56 : Components Layout
30/31
TDA9105A
PACKAGE MECHANICAL DATA
42 PINS - PLASTIC SHRINK DIP
E
A2
A
L
A1
E1
B
B1
e
e1
e2
D
c
E
42
22
.015
0,38
1
PMSDIP42.EPS
Gage Plane
e3
21
e2
SDIP42
A
A1
A2
B
B1
c
D
E
E1
e
e1
e2
e3
L
Min.
0.51
3.05
0.38
0.89
0.23
36.58
15.24
12.70
2.54
Millimeters
Typ.
3.81
0.46
1.02
0.25
36.83
13.72
1.778
15.24
3.30
Max.
5.08
4.57
0.56
1.14
0.38
37.08
16.00
14.48
18.54
1.52
3.56
Min.
0.020
0.120
0.0149
0.035
0.0090
1.440
0.60
0.50
0.10
Inches
Typ.
0.150
0.0181
0.040
0.0098
1.450
0.540
0.070
0.60
0.130
Max.
0.200
0.180
0.0220
0.045
0.0150
1.460
0.629
0.570
0.730
0.060
0.140
SDIP42.TBL
Dimensions
Information furni shed is believed to be accurate and reliable. However, SGS-THOMSON Micr oelectronics assumes no responsibility
for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result
from its use. No licence is granted by implication or otherwise und erany patent or patent rights of SGS-THOMSON Microelectronics.
Specifications mentioned in this publication are subject to change without notice. This pu blication supersedes and replaces all
information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life
support devices or systems without express written approval of SGS-THOMSON Microelectronics.
 1997 SGS-THOMSON Microelectronics - All Rights Reserved
Purchase of I 2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips
2
2
I C Patent. Rights to use these components in a I C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.
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