PHILIPS TDA4855

INTEGRATED CIRCUITS
DATA SHEET
TDA4855
Autosync Deflection Controller
(ASDC)
Preliminary specification
File under Integrated Circuits, IC02
1996 Jul 18
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
FEATURES
Vertical section
Concept features
• Vertical amplitude independent of frequency
• Full Horizontal (H) plus Vertical (V) autosync capability
• Automatic correction of picture height for VGA350 and
VGA400 modes
• Completely DC controllable for analog and digital
concepts
• DC controllable picture height, picture position and
S-correction
• Excellent geometry control functions (e.g. automatic
correction of East-West (EW) parabola during
adjustment of vertical size and vertical shift)
• Differential current outputs for DC coupling to vertical
booster.
• Flexible Switched Mode Power Supply (SMPS) function
block for feedback and feed forward converters
EW section
• Horizontal focus parabola with amplitude control
• Output for DC adjustable EW parabola with smoothed
top
• X-ray protection
• DC controllable picture width and trapezium correction
• Start-up and switch-off sequence for safe operation of
all power components
• Optional tracking of EW parabola with line frequency
• Prepared for additional DC controls of vertical linearity,
EW-corner, EW pin balance, EW parallelogram, vertical
focus by extended application.
• Very good vertical linearity
• Internal supply voltage stabilization
• SDIP32 package.
Synchronization inputs
GENERAL DESCRIPTION
• Can handle all sync signals (Horizontal, Vertical,
Composite and Sync-on-video)
The TDA4855 is a high performance and efficient solution
for autosync monitors. The concept is fully DC controllable
and can be used in applications with a microcontroller and
stand-alone in rock bottom solutions.
• Combined output for video clamping, vertical blanking
and protection blanking.
The TDA4855 provides synchronization processing, H + V
synchronization with full autosync capability, and very
short settling times after mode changes. External power
components are given a great deal of protection. The IC
generates the drive waveforms for DC-coupled vertical
boosters such as TDA486X and TDA8351.
Horizontal section
• Extremely low jitter
• Frequency locked loop for smooth catching of line
frequency
• Simple frequency preset of fmin and fmax by external
resistors
The TDA4855 provides extended functions e.g. as a
flexible SMPS block and an extensive set of geometry
control facilities, providing excellent picture quality.
• DC controllable wide range linear picture position
• Soft start for horizontal driver.
1996 Jul 18
Together with the Philips TDA488X video processor family
a very advanced system solution is offered.
2
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VCC
supply voltage
9.2
−
16
V
ICC
supply current
−
49
−
mA
∆HPOS
horizontal shift adjustment range
−
±10.5
−
%
∆VAMP
vertical size adjustment range
60
−
100
%
∆VPOS
vertical shift adjustment range
−
±11.5
−
%
∆VSCOR
vertical S-correction adjustment range
2
−
46
%
∆VEWPAR
EW parabola adjustment range
0.15
−
3.0
V
∆VEWWID
horizontal size adjustment range
0.2
−
4.0
V
∆VEWTRP
trapezium correction adjustment range
−
±0.5
−
V
Tamb
operating ambient temperature
0
−
70
°C
ORDERING INFORMATION
TYPE
NUMBER
TDA4855
1996 Jul 18
PACKAGE
NAME
SDIP32
DESCRIPTION
plastic shrink dual in-line package; 32 leads (400 mil)
3
VERSION
SOT232-1
1996 Jul 18
4
(video)
H-focus
parabola
clamping
blanking
16
HSYNC
(TTL level) 15
FOCUS 10
CLBL
SGND 25
PGND 8
9
14
HORIZONTAL/
COMPOSITE
SYNC INPUT
FOCUS
(2)
HPLL1
(1)
RHBUF
30
HPOS
220
kΩ
39
kΩ
HBUF
27
PLL1
1.5
nF
26
AGC
12 nF
10 nF
2%
RHREF
(1)
HPLL2
HCAP
HREF
31
29
28
PLL2
1
HFLB
X-RAY
PROTECTION
VGA
PRESETS
VERTICAL POSITION
VERTICAL SIZE
HORIZONTAL
OSCILLATOR
FREQUENCY DETECTOR
COINCIDENCE DETECTOR
TDA4855
VERTICAL
OSCILLATOR
18
19
13
12
VOUT1 VOUT2
HDRV
7
HORIZONTAL
OUTPUT
STAGE
B+
CONTROL
EW
PARABOLA
VERTICAL
OUTPUT STAGE
S-CORRECTION
39 kΩ
39 kΩ
17
220 kΩ
VSCOR
220 kΩ
Fig.1 Block diagram and application circuit.
47 nF
27 kΩ
POLARITY
CORRECTION
VERTICAL SYNC
INTEGRATOR
POLARITY
CORRECTION
HFLB
VIDEO CLAMPING PULSE
VERTICAL BLANKING
SUPPLY
AND
REFERENCE
VERTICAL
SYNC
INPUT
24
23
VAMP
MBG550
5 BIN
3 BOP
4 BSENS
220 kΩ
220 kΩ
220 kΩ
(3)
B+ CONTROL
APPLICATION
EWDRV
XRAY
6 BDRV
2
11
20 EWTRP 39 kΩ
32 EWWID 39 kΩ
21 EWPAR 39 kΩ
EW
trapeziun
horizontal
size
EW
parabola
Autosync Deflection Controller (ASDC)
(1) See calculation of fH range.
(2) See note 3 of Chapter “Characteristics”.
(3) See Figs 12 and 13.
VCC
9.2 to 16 V
VSYNC
(TTL level)
VAGC
VCAP
VREF
22
100
220 kΩ
nF
CVAGC
39 kΩ
100
22
nF
kΩ
1% CVCAP 5%
handbook, full pagewidth
RVREF
VPOS
Philips Semiconductors
Preliminary specification
TDA4855
BLOCK DIAGRAM
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
PINNING
SYMBOL PIN
DESCRIPTION
HFLB
1
horizontal flyback input
XRAY
2
X-ray protection input
BOP
3
B+ control OTA output;
comparator input
BSENS
4
B+ control comparator input/output
BIN
5
B+ control OTA input
BDRV
6
B+ control driver output
HDRV
7
horizontal driver output
PGND
8
power ground
VCC
9
supply voltage
FOCUS
10
horizontal focus parabola input/output
EWDRV
11
VOUT2
handbook, halfpage
HFLB
1
32 EWWID
XRAY
2
31 HPLL2
BOP
3
30 HPOS
BSENS
4
29 HCAP
BIN
5
28 HREF
BDRV
6
27 HBUF
HDRV
7
26 HPLL1
PGND
8
25 SGND
TDA4855
VCC
9
24 VCAP
EW parabola output
FOCUS 10
23 VREF
12
vertical output 2 (ascending sawtooth)
EWDRV 11
22 VAGC
VOUT1
13
vertical output 1 (descending
sawtooth)
VSYNC
14
vertical synchronization input/output
(TTL level)
HSYNC
15
horizontal/composite synchronization
input (TTL level or sync-on-video)
CLBL
16
video clamping pulse/vertical blanking
and protection output
VPOS
17
vertical shift input
VAMP
18
vertical size input
VSCOR
19
vertical S-correction input
EWTRP
20
EW trapezium correction input
EWPAR
21
EW parabola amplitude input
VAGC
22
external capacitor for vertical
amplitude control
VREF
23
external resistor for vertical oscillator
VCAP
24
external capacitor for vertical oscillator
SGND
25
signal ground
HPLL1
26
external filter for PLL1
HBUF
27
buffered f/v voltage output
HREF
28
reference current for horizontal
oscillator
HCAP
29
external capacitor for horizontal
oscillator
HPOS
30
horizontal shift input
HPLL2
31
external filter for PLL2/soft start
EWWID
32
horizontal size input
1996 Jul 18
VOUT2 12
21 EWPAR
VOUT1 13
20 EWTRP
VSYNC 14
19 VSCOR
HSYNC 15
18 VAMP
CLBL 16
17 VPOS
MBG549
Fig.2 Pin configuration.
5
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
The lower level of the sandcastle pulse is the vertical
blanking pulse, which is derived directly from the internal
oscillator waveform. It is started by the vertical sync and
stopped with the start of the vertical scan. This results in
optimum vertical blanking.
FUNCTIONAL DESCRIPTION
Horizontal sync separator and polarity correction
HSYNC (pin 15) is the input for horizontal synchronization
signals, which can be DC-coupled TTL signals (horizontal
or composite sync) and AC-coupled negative-going video
sync signals. Video syncs are clamped to 1.28 V and
sliced at 1.4 V. This results in a fixed absolute slicing level
of 120 mV related to sync top.
Blanking will be activated continuously, if one of the
following conditions is true:
No horizontal flyback pulses at HFLB (pin 1)
X-ray protection is activated
For DC-coupled TTL signals the input clamping current is
limited. The slicing level for TTL signals is 1.4 V.
Soft start of horizontal drive (voltage at HPLL2 (pin 31)
is low)
The separated sync signal (either video or TTL) is
integrated on an internal capacitor to detect and normalize
the sync polarity.
Supply voltage at VCC (pin 9) is low (see Fig.14)
PLL1 is unlocked while frequency-locked loop is in
search mode.
Normalized horizontal sync pulses are used as input
signals for the vertical sync integrator, the PLL1 phase
detector and the frequency-locked loop.
Blanking will not be activated if the horizontal sync
frequency is below the valid range or there are no sync
pulses available.
Vertical sync integrator
VGA mode detector
Normalized composite sync signals from HSYNC are
integrated on an internal capacitor in order to extract
vertical sync pulses. The integration time is dependent on
the horizontal oscillator reference current at HREF
(pin 28). The integrator output directly triggers the vertical
oscillator. This signal is available at VSYNC (normally
vertical sync input; pin 14), which is used as an output in
this mode.
The polarities of horizontal and vertical sync are internally
detected in order to provide an automatic adjustment of
vertical size for VGA350 and VGA400 modes.
These automatic VGA presets are activated only if the
current ratio IHBUF/IHREF exceeds a fixed value
(see Chapter “Characteristics”). Thus it is possible to
disable this function for a part of the frequency range or
even completely.
Vertical sync slicer and polarity correction
Table 1
Vertical sync signals (TTL) applied to VSYNC (pin 14) are
sliced at 1.4 V. The output signal of the sync slicer is
integrated on an internal capacitor to detect and normalize
the sync polarity.
MODE
If a composite sync signal is detected at HSYNC, VSYNC
is used as output for the integrated vertical sync (e.g. for
power saving applications).
The video clamping/vertical blanking signal at CLBL
(pin 16) is a two-level sandcastle pulse which is especially
suitable for video ICs such as the TDA488X family, but
also for direct applications in video output stages.
The upper level is the video clamping pulse, which is
triggered by the trailing edge of the horizontal sync pulse.
The width of the video clamping pulse is determined by an
internal monoflop.
6
HORIZONTAL/VERTICAL SYNC
POLARITY
VGA350
+
−
VGA400
−
+
VGA480
−
−
+
+
−
Video clamping/vertical blanking generator
1996 Jul 18
VGA modes
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
The reference current at HREF also defines the integration
time constant of the vertical sync integration.
Frequency-locked loop
The frequency-locked loop can lock the horizontal
oscillator over a wide frequency range. This is achieved by
a combined search and PLL operation. The frequency
range is preset by two external resistors and the
f min
1
recommended maximum ratio is ---------- = -------3.5
f max
Calculation of line frequency range
First the oscillator frequencies fmin and fmax have to be
calculated. This is achieved by adding the spread of the
relevant components to the highest and lowest sync
frequencies fS(min) and fS(max). The oscillator is driven by
the difference of the currents in RHREF and RHBUF. At the
highest oscillator frequency RHBUF does not contribute to
the spread. The spread will increase towards lower
frequencies due to the contribution of RHBUF. It is also
Larger ranges are possible by extended applications.
Without a horizontal sync signal the oscillator will be
free-running at fmin. Any change of sync conditions is
detected by the internal coincidence detector. A deviation
of more than 4% between horizontal sync and oscillator
frequency switches the horizontal section into search
mode. This means that PLL1 control currents are switched
off immediately. Then the internal frequency detector
starts tuning the oscillator. Very small DC currents at
HPLL1 (pin 26) are used to perform this tuning with a well
defined change rate. When coincidence between
horizontal sync and oscillator frequency is detected, the
search mode is replaced by a normal PLL operation.
This operation ensures a smooth tuning and avoids fast
changes of horizontal frequency during catching.
f S ( max )
dependent on the ratio n S = -----------------f S ( min )
The following example is a 31.45 to 64 kHz application:
f S ( max )
64 kHz
n S = ------------------ = --------------------------- = 2.04
f S ( min )
31.45 kHz
Table 2
Calculation of total spread
for fmax
for fmin
IC
3%
3%
CHCAP
2%
2%
RHREF
1%
−
−
1% × (2.3 × nS − 1)
6%
8.69%
spread of:
In this concept it is not allowed to load HPLL1.
The frequency dependent voltage at this pin is fed
internally to HBUF (pin 27) via a sample-and-hold and
buffer stage. The sample-and-hold stage removes all
disturbances caused by horizontal sync or composite
vertical sync from the buffered voltage. An external
resistor from HBUF to HREF defines the frequency range.
RHREF, RHBUF
Total
Thus the typical frequency range of the oscillator in this
example is:
See also hints for locking procedure in note 3 of
Chapter “Characteristics”.
f max = f S ( max ) × 1.06 = 67.84 kHz
PLL1 phase detector
f S ( min )
f min = ----------------- = 28.93 kHz
1.087
The phase detector is a standard type using switched
current sources. It compares the middle of horizontal sync
with a fixed point on the oscillator sawtooth voltage.
The PLL1 loop filter is connected to HPLL1 (pin 26).
The resistors RHREF and RHBUF can be calculated with the
following formulae:
74 × kHz × k Ω
R HREF = -------------------------------------- = 1.091 kΩ
f max [ kHz ]
Horizontal oscillator
The horizontal oscillator is of the relaxation type and
requires a capacitor of 10 nF at HCAP (pin 29).
For optimum jitter performance the value of 10 nF must not
be changed.
R HREF × 1.19 × n
R HBUF = -------------------------------------------- = 2.26 kΩ
n–1
f max
Where: n = ---------- = 2.35
f min
The maximum oscillator frequency is determined by a
resistor from HREF to ground. A resistor from HREF to
HBUF defines the frequency range.
1996 Jul 18
TDA4855
7
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
therefore the phase between horizontal sync and
horizontal drive pulse is only determined by PLL2.
The spread of fmin increases with the frequency
f S ( max )
ratio ------------------- .
f S ( min )
Output stage for line drive pulses
For higher ratios this spread can be reduced by using
resistors with less tolerances.
An open collector output stage allows direct drive of an
inverting driver transistor because of a low saturation
voltage of 0.3 V at 20 mA. To protect the line deflection
transistor, the output stage is disabled (floating) for low
supply voltage at VCC (see Fig.14).
PLL2 phase detector
The PLL2 phase detector is similar to the PLL1 detector
and compares the line flyback pulse at HFLB (pin 1) with
the oscillator sawtooth voltage. The PLL2 detector thus
compensates for the delay in the external horizontal
deflection circuit by adjusting the phase of the HDRV
(pin 7) output pulse.
The duty factor of line drive pulses is slightly dependent on
the actual line frequency. This ensures optimum drive
conditions over the whole frequency range.
X-ray protection
The phase between horizontal flyback and horizontal sync
can be controlled at HPOS (pin 30).
The x-ray protection input XRAY (pin 2) provides a voltage
detector with a precise threshold. If the input voltage at
XRAY exceeds this threshold for a certain time, an internal
latch switches the IC into protection mode. In this mode
several pins are forced into defined states:
If HPLL2 is pulled to ground, horizontal output pulses,
vertical output currents and B+ control driver pulses are
inhibited. This means, HDRV (pin 7), BDRV (pin 6)
VOUT1 (pin 13) and VOUT2 (pin 12) are floating in this
state. PLL2 and the frequency-locked loop are disabled,
and CLBL (pin 16) provides a continuous blanking signal.
Horizontal output stage (HDRV) is floating
B+ control driver stage (BDRV) is floating
Vertical output stages (VOUT1 and VOUT2) are floating
This option can be used for soft start, protection and
power-down modes. When the HPLL2 voltage is released
again, an automatic soft start sequence will be performed
(see Fig.15).
CLBL provides a continuous blanking signal
The capacitor connected to HPLL2 (pin 31) is
discharged.
To reset the latch and return to normal operation, VCC has
to be temporarily switched off.
The soft start timing is determined by the filter capacitor at
HPLL2 (pin 31), which is charged with an constant current
during soft start. In the beginning the horizontal driver
stage generates very small output pulses. The width of
these pulses increases with the voltage at HPLL2 until the
final duty factor is reached. At this point BDRV (pin 6),
VOUT1 (pin 13) and VOUT2 (pin 12) are re-enabled.
The voltage at HPLL2 continues to rise until PLL2 enters
its normal operating range. The internal charge current is
now disabled. Finally PLL2 and the frequency-locked loop
are enabled, and the continuous blanking at CLBL is
removed.
Vertical oscillator and amplitude control
This stage is designed for fast stabilization of vertical
amplitude after changes in sync frequency conditions.
The free-running frequency fosc(V) is determined by the
resistor RVREF connected to pin 23 and the capacitor
CVCAP connected to pin 24. The value of RVREF is not only
optimized for noise and linearity performance in the whole
vertical and EW section, but also influences several
internal references. Therefore the value of RVREF must not
be changed. Capacitor CVCAP should be used to select the
free-running frequency of the vertical oscillator in
accordance with the following formula:
1
f osc ( V ) = ----------------------------------------------------------10.8 × R VREF × C VCAP
Horizontal phase adjustment
HPOS (pin 30) provides a linear adjustment of the relative
phase between the horizontal sync and oscillator
sawtooth. Once adjusted, the relative phase remains
constant over the whole frequency range.
Application hint: HPOS is a current input, which provides
an internal reference voltage while IHPOS is in the specified
adjustment current range. By grounding HPOS the
symmetrical control range is forced to its centre value,
1996 Jul 18
TDA4855
8
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
readjustment of these parameters is necessary after an
adjustment of vertical picture size or position.
To achieve a stabilized amplitude the free-running
frequency fosc(V), without adjustment, should be at least
10% lower than the minimum trigger frequency.
The contributions shown in Table 3 can be assumed.
Table 3
Application hint: VPOS is a current input, which provides
an internal reference voltage while IVPOS is in the specified
adjustment current range. By grounding VPOS (pin 17) the
symmetrical control range is forced to its centre value.
Calculation of fosc(V) total spread
Contributing elements:
Minimum frequency offset between fosc(V)
and lowest trigger frequency
Application hint: VSCOR is a current input at 5 V.
Superimposed on this level is a very small positive-going
vertical sawtooth, intended to modulate an external
long-tailed transistor pair. This enables further optional DC
controls of functions which are not directly accessible such
as vertical tilt or vertical linearity (see Fig.17).
±10%
Spread of IC
±3%
Spread of RVREF
±1%
Spread of CVCAP
±5%
Total
19%
TDA4855
EW parabola (including horizontal size and trapezium
correction)
EWDRV (pin 11) provides a complete EW drive waveform.
EW parabola amplitude, DC shift (horizontal size) and
trapezium correction can be controlled via separate DC
inputs.
Result for 50 to 110 Hz application:
50 Hz
f osc ( V ) = --------------- = 42 Hz
1.19
Application hint: VAGC (pin 22) has a high input
impedance during scan, thus the pin must not be loaded
externally. Otherwise non-linearities in the vertical output
currents may occur due to the changing charge current
during scan.
EWPAR (pin 21) is used to adjust the parabola amplitude.
This can be a combination of a DC adjustment and a
dynamic waveform modulation.
The EW parabola amplitude also tracks with vertical
picture size. The parabola waveform itself tracks with the
adjustment for vertical picture shift (VPOS).
Additional effort has been taken to generate a smooth
waveform at the top of the parabola. This is to avoid ringing
in the horizontal output stage.
Application hint: The full vertical sync range of 1 : 2.5 can
be made usable by incorporating an adjustment of the
free-running frequency. Also the complete sync range can
be shifted to higher frequencies (e.g. 70 to 160 Hz) by
reducing the value of CVCAP.
EWWID (pin 32) offers two modes of operation:
Adjustment of vertical size, vertical shift and
S-correction
1. Mode 1
Horizontal size is DC controlled via EWWID (pin 32)
and causes a DC shift at the EWDRV output. Also the
complete waveform is multiplied internally by a signal
proportional to the line frequency (which is detected
via the current at HREF (pin 28). This mode is to be
used for driving EW modulator stages which require a
voltage proportional to the line frequency.
VPOS (pin 17) is the input for the DC adjustable vertical
picture shift. This pin provides a phase shift at the
sawtooth output VOUT1 and VOUT2 (pins 13 and 12) and
the EW drive output EWDRV (pin 11) in such a way, that
the whole picture moves vertically while maintaining the
correct geometry.
2. Mode 2
The amplitude of the differential output currents at VOUT1
and VOUT2 can be adjusted via input VAMP (pin 18).
This can be a combination of a DC adjustment and a
dynamic waveform modulation.
EWWID (pin 32) is grounded. Then EWDRV is no
longer multiplied by the line frequency. The DC
adjustment for horizontal size must be added to the
input of the B+ control amplifier BIN (pin 5). This mode
is to be used for driving EW modulators which require
a voltage independent of the line frequency.
VSCOR (pin 19) is used to adjust the amount of vertical
S-correction in the output signal.
The adjustments for vertical size and vertical shift also
affect the waveforms of the EW parabola and the vertical
S-correction. The result of this interaction is that no
1996 Jul 18
EWTRP (pin 20) is used to adjust the amount of trapezium
correction in the EW drive waveform.
9
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
Application hint: EWTRP (pin 20) is a current input at
5 V. Superimposed on this level is a very small vertical
parabola with positive tips, intended to modulate an
external long-tailed transistor pair. This enables further
optional DC controls of functions which are not directly
accessible such as EW-corner, vertical focus or EW pin
balance (see Fig.17).
An internal discharge circuit allows a well defined
discharge of capacitors at BSENS. BDRV is active at a low
level output voltage (see Figs 12 and 13), thus it requires
an external inverting driver stage.
The B+ function block can be used for B+ deflection
modulators in either of two modes:
• Feedback mode (see Fig.12)
Application hint: By grounding EWTRP (pin 20) the
symmetrical control range is forced to its centre value.
In this application the OTA is used as an error amplifier
with a limited output voltage range. The flip-flop will be
set at the rising edge of the signal at HDRV. A reset will
be generated when the voltage at BSENS taken from
the current sense resistor exceeds the voltage at BOP.
Dynamic focus section
This section generates a horizontal parabola waveform for
dynamic focus applications. The amplitude of this parabola
is internally stabilized, thus it is independent from the line
frequency.
If no reset is generated within a line period, the rising
edge of the next HDRV pulse forces the flip-flop to reset.
The flip-flop is set immediately after the voltage at
BSENS has dropped below the threshold voltage
VRESTART(BSENS).
FOCUS (pin 10) is designed as a current sink.
The peak-to-peak amplitude of the output current can be
adjusted by forcing the voltage at pin 10 to a value
between 1 and 4 V.
• Feed forward mode (see Fig.13)
This application uses an external RC combination at
BSENS to provide a pulse width which is independent
from the horizontal frequency. The capacitor is charged
via an external resistor and discharged by the internal
discharge circuit. For normal operation the discharge
circuit is activated when the flip-flop is reset by the
internal voltage comparator. Now the capacitor will be
discharged with a constant current until the internally
controlled stop level VSTOP(BSENS) is reached. This level
will be maintained until the rising edge of the next HDRV
pulse sets the flip-flop again and disables the discharge
circuit.
B+ control function block
The B+ control function block of the ASDC consists of an
Operational Transconductance Amplifier (OTA), a voltage
comparator, a flip-flop and a discharge circuit.
This configuration allows easy applications for different
B+ control concepts.
GENERAL DESCRIPTION
The non-inverting input of the OTA is connected internally
to a high precision reference voltage. The inverting input is
connected to BIN (pin 5). An internal clamping circuit limits
the maximum positive output voltage of the OTA.
The output itself is connected to BOP (pin 3) and to the
inverting input of the voltage comparator.
The non-inverting input of the voltage comparator can be
accessed via BSENS (pin 4).
If no reset is generated within a line period, the rising
edge of the next HDRV pulse automatically starts the
discharge sequence and resets the flip-flop (Fig.13).
When the voltage at BSENS reaches the threshold
voltage VRESTART(BSENS), the discharge circuit will be
disabled automatically and the flip-flop will be set
immediately. This behaviour allows a definition of the
maximum duty cycle of the B+ control drive pulse by the
relationship of charge current to discharge current.
B+ drive pulses are generated by an internal flip-flop and
fed to BDRV (pin 6) via an open collector output stage.
This flip-flop will be set at the rising edge of the signal at
HDRV (pin 7). The falling edge of the output signal at
BDRV has a defined delay of td(BDRV) to the rising edge of
the HDRV pulse. When the voltage at BSENS exceeds the
voltage at BOP, the voltage comparator output resets the
flip-flop, and therefore the open collector stage at BDRV is
floating again.
1996 Jul 18
TDA4855
10
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
The return to normal operation is performed in accordance
with the start-up sequence in Fig.14a, if the reset was
caused by the supply voltage at pin 9. The first action with
increasing supply voltage is the activation of continuous
blanking at CLBL. When the threshold for activation of
HDRV is passed, an internal current begins to charge the
external capacitor at HPLL2 and a PLL2 soft start
sequence is performed (see Fig.15). In the beginning of
this phase the horizontal driver stage generates very small
output pulses. The width of these pulses increases with the
voltage at HPLL2 until the final duty cycle is reached.
Then the PLL2 voltage passes the threshold for activation
of BDRV, VOUT1 and VOUT2.
Supply voltage stabilizer, references and protection
The ASDC provides an internal supply voltage stabilizer
for excellent stabilization of all internal references.
An internal gap reference especially designed for
low-noise is the reference for the internal horizontal and
vertical supply voltages. All internal reference currents and
drive current for the vertical output stage are derived from
this voltage via external resistors.
A special protection mode has been implemented in order
to protect the deflection stages and the picture tube during
start-up, shut-down and fault conditions. This protection
mode can be activated as shown in Table 4.
Table 4
For activation of these pins not only the PLL2 voltage, but
also the supply voltage must have passed the appropriate
threshold. A last pair of thresholds has to be passed by
PLL2 voltage and supply voltage before the continuous
blanking is finally removed, and the operation of PLL2 and
frequency-locked loop is enabled.
Activation of protection mode
ACTIVATION
RESET
Low supply voltage at pin 9
increase supply voltage
X-ray protection XRAY (pin 2)
triggered
remove supply voltage
HPLL2 (pin 31) pulled to
ground
release pin 31
A return to the normal operation by releasing the voltage
at HPLL2 will lead to a slightly different sequence. Here the
activation of all functions is influenced only by the voltage
at HPLL2 (see Fig.15).
When protection mode is active, several pins of the ASDC
are forced into a defined state:
Application hint: Internal discharge of the capacitor at
HPLL2 will only be performed, if the protection mode was
activated via the supply voltage or X-ray protection.
HDRV (horizontal driver output) is floating
BDRV (B+ control driver output) is floating
VOUT1 and VOUT2 (vertical outputs) are floating
CLBL provides a continuous blanking signal
The capacitor at HPLL2 is discharged.
If the protection mode is activated via the supply voltage at
pin 9, all these actions will be performed in a well defined
sequence (see Fig.14). For activation via X-ray protection
or HPLL2 all actions will occur simultaneously.
1996 Jul 18
TDA4855
11
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); all voltages measured with respect to ground.
SYMBOL
PARAMETER
UNIT
+16
V
BIN
−0.5
+6.0
V
HSYNC, VPOS, VAMP, VSCOR, VREF, HREF and HPOS
−0.5
+6.5
V
XRAY
−0.5
+8.0
V
VOUT1 and VOUT2
−0.5
+6.5
V
BDRV and HDRV
−0.5
+16
V
BOP and BSENS
−0.5
+6.0
V
FOCUS and VSYNC
supply voltage
VI(n)
input voltages
VI/O(n)
MAX.
−0.5
VCC
VO(n)
MIN.
output voltages
input/output voltages
−0.5
+6.5
V
IHDRV
horizontal driver output current
−
100
mA
IHFLB
horizontal flyback input current
−10
+10
mA
ICLBL
video clamping pulse/vertical blanking output current
−
−10
mA
IBOP
B+ control OTA output current
−
1
mA
IBDRV
B+ control driver output current
−
50
mA
IEWDRV
EW driver output current
−
−5
mA
Tamb
operating ambient temperature
0
70
°C
Tj
junction temperature
−
150
°C
Tstg
storage temperature
−55
+150
°C
Vesd
electrostatic discharge for all pins (note 1)
machine model
−400
+400
V
human body model
−3000
+3000
V
Note
1. Machine model: 200 pF, 25 Ω, 2.5 µH; human body model: 100 pF, 1500 Ω, 7.5 µH.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
thermal resistance from junction to ambient in free air
VALUE
UNIT
55
K/W
QUALITY SPECIFICATION
In accordance with “URF-4-2-59/601”; EMC emission/immunity test in accordance with “DIS 1000 4.6” (IEC 801.6)
SYMBOL
VEMC
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
emission test
note 1
−
1.5
−
mV
immunity test
note 1
−
2.0
−
V
Note
1. Tests are performed with application reference board. Tests with other boards will have different results.
1996 Jul 18
12
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
CHARACTERISTICS
VCC = 12 V; Tamb = 25 °C; peripheral components in accordance with Fig.1; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Horizontal sync separator
INPUT CHARACTERISTICS FOR DC-COUPLED TTL SIGNALS [HSYNC (PIN 15)]
−
−
V
1.2
1.4
1.6
V
10
−
500
ns
10
−
500
ns
VDC(HSYNC)
sync input signal voltage
1.7
slicing voltage level
tr(HSYNC)
rise time of sync pulse
tf(HSYNC)
fall time of sync pulse
tW(HSYNC)
minimum width of sync pulse
IDC(HSYNC)
input current
0.7
−
−
µs
VHSYNC = 0.8 V
−
−
−200
µA
VHSYNC = 5.5 V
−
−
10
µA
INPUT CHARACTERISTICS FOR AC-COUPLED VIDEO SIGNALS (SYNC-ON-VIDEO, NEGATIVE SYNC POLARITY)
VAC(HSYNC)
sync amplitude of video input
signal voltage
slicing voltage level
(measured from top sync)
source resistance
RS = 50 Ω
−
300
−
mV
90
120
150
mV
1.1
1.28
1.5
V
1.7
2.4
3.4
µA
0.7
−
−
µs
Vclamp(HSYNC)
top sync clamping voltage level
IC(HSYNC)
charge current for coupling
capacitor
tHSYNC(min)
minimum width of sync pulse
RS(max)
maximum source resistance
duty factor = 7%
−
−
1500
Ω
rdiff(HSYNC)
differential input resistance
during sync
−
80
−
Ω
fH < 45 kHz
−
−
20
%
fH > 45 kHz
−
−
25
%
0.3
−
1.8
ms
fH = 31.45 kHz;
IHREF = 1.052 mA
7
10
13
µs
fH = 64 kHz;
IHREF = 2.141 mA
3.9
5.7
6.5
µs
fH = 100 kHz;
IHREF = 3.345 mA
2.5
3.8
4.5
µs
sync input signal voltage
1.7
−
−
V
slicing voltage level
1.2
1.4
1.6
V
−
−
±10
µA
VHSYNC > Vclamp(HSYNC)
Automatic polarity correction for horizontal sync
tP ( H)
------------tH
horizontal sync pulse width
related to tH
tP(H)
delay time for changing polarity
Vertical sync integrator
tint(V)
integration time for generation
of a vertical trigger pulse
Vertical sync slicer (DC-coupled, TTL compatible) [VSYNC (pin 14)]
VVSYNC
IVSYNC
1996 Jul 18
input current
0 V < VSYNC < 5.5 V
13
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
SYMBOL
PARAMETER
TDA4855
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VERTICAL SYNC OUTPUT AT VSYNC (PIN 14) DURING COMPOSITE SYNC AT HSYNC (PIN 15)
IVSYNC
output current
during internal vertical
sync
−0.7
−1.0
−1.35
mA
VVSYNC
internal clamping voltage level
during internal vertical
sync
4.4
4.8
5.2
V
−
300
−
ns/mA
steepness of slopes
Automatic polarity correction for vertical sync
tVSYNC(max)
maximum width of vertical sync
pulse
−
−
300
µs
td(VPOL)
delay for changing polarity
0.3
−
1.8
ms
0.6
0.7
0.8
µs
4.32
4.75
5.23
V
Video clamping/vertical blanking output [CLBL (pin 16)]
tclamp(CLBL)
width of video clamping pulse
measured at VCLBL = 3 V
Vclamp(CLBL)
top voltage level of video
clamping pulse
td(clamp)
delay between trailing edge of
horizontal sync and start of
video clamping pulse
clamping pulse triggered
on trailing edge of
horizontal sync
−
130
−
ns
tclamp(max)
maximum duration of video
clamping pulse referenced to
end of horizontal sync
measured at VCLBL = 3 V
−
−
1.0
µs
TCclamp
temperature coefficient of
Vclamp(CLBL)
−
+4
−
mV/K
steepness of slopes for
clamping pulse
RL = 1 MΩ; CL = 20 pF
−
50
−
ns/V
Vblank(CLBL)
top voltage level of vertical
blanking pulse
notes 1 and 2
1.7
1.9
2.1
V
tblank(CLBL)
width of vertical blanking pulse
VGA presets active
500
575
650
µs
VGA presets disabled
240
300
360
µs
−
+2
−
mV/K
0.59
0.63
0.67
V
TCblank
temperature coefficient of
Vblank(CLBL)
Vscan(CLBL)
output voltage during vertical
scan
TCscan
temperature coefficient of
Vscan(CLBL)
−
−2
−
mV/K
Isink(CLBL)
internal sink current
2.4
−
−
mA
Iload(CLBL)
external load current
−
−
−3.0
mA
1996 Jul 18
ICLBL = 0
14
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
SYMBOL
PARAMETER
TDA4855
CONDITIONS
MIN.
TYP.
MAX.
UNIT
PLL1 phase comparator and frequency-locked loop [HPLL1 (pin 26) and HBUF (pin 27)]
tHSYNC(max)
maximum width of horizontal
sync pulse (referenced to line
period)
fH < 45 kHz; note 3
−
−
20
%
fH > 45 kHz; note 3
−
−
25
%
−
40
80
ms
tlock(HPLL1)
total lock-in time of PLL1
VHPLL1
control voltage
notes 4 and 5
VHBUF
buffered f/v voltage at HBUF
(pin 27)
fH(min); note 6
−
5.6
−
V
fH(max); note 6
−
2.5
−
V
−
−
−4.0
mA
Iload(HBUF)
maximum load current
ADJUSTMENT OF HORIZONTAL PICTURE POSITION
∆HPOS
IHPOS
horizontal shift adjustment
range (referenced to horizontal
period)
IHSHIFT = 0
−
−10.5
−
%
IHSHIFT = −135 µA
−
+10.5
−
%
input current
∆HPOS = +10.5%
−110
−120
−135
µA
∆HPOS = −10.5%
−
0
−
µA
note 7
−
5.1
−
V
0
−
0.1
V
30.53
31.45
32.39
kHz
Vref(HPOS)
reference voltage at input
Voff(HPOS)
picture shift is centred if HPOS
(pin 30) is forced to ground
Horizontal oscillator [HCAP (pin 29) and HREF (pin 28)]
RHBUF = ∞;
RHREF = 2.4 kΩ;
CHCAP = 10 nF; note 5
fH(0)
free-running frequency without
PLL1 action (for testing only)
∆fH(0)
spread of free-running
frequency (excluding spread of
external components)
−
−
±3.0
%
TC
temperature coefficient of
free-running frequency
−100
0
+100
10−6/K
fH(max)
maximum oscillator frequency
−
−
130
kHz
VHREF
voltage at input for reference
current
2.43
2.55
2.68
V
PLL2 phase detector [HFLB (pin 1) and HPLL2 (pin 31)]
∆φPLL2
PLL2 control (advance of
horizontal drive with respect to
middle of horizontal flyback)
maximum advance
36
−
−
%
minimum advance
−
7
−
%
td(HFLB)
delay between middle of
horizontal sync and middle of
horizontal flyback
HPOS (pin 30) grounded
−
200
−
ns
VPROT(HPLL2)
maximum voltage for PLL2
protection mode/soft start
−
4.4
−
V
Icharge(HPLL2)
charge current for external
capacitor during soft start
−
15
−
µA
1996 Jul 18
VHPLL2 < 3.7 V
15
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
SYMBOL
PARAMETER
TDA4855
CONDITIONS
MIN.
TYP.
MAX.
UNIT
HORIZONTAL FLYBACK INPUT [HFLB (PIN 1)]
VHFLB
IHFLB
VHFLB
positive clamping level
IHFLB = 5 mA
−
5.5
−
V
negative clamping level
IHFLB = −1 mA
−
−0.75
−
V
positive clamping current
−
−
6
mA
negative clamping current
−
−
−2
mA
slicing level
−
2.8
−
V
−
−
0.3
V
Output stage for line driver pulses [HDRV (pin 7)]
OPEN COLLECTOR OUTPUT STAGE
VHDRV
saturation voltage
IHDRV = 20 mA
IHDRV = 60 mA
−
−
0.8
V
Ileakage(HDRV)
output leakage current
VHDRV = 16 V
−
−
10
µA
IHDRV = 20 mA;
fH = 31.45 kHz; see Fig.9
42
45
48
%
IHDRV = 20 mA;
fH = 57 kHz; see Fig.9
45
46.3
47.7
%
IHDRV = 20 mA;
fH = 90 kHz; see Fig.9
46.6
48
49.4
%
AUTOMATIC VARIATION OF DUTY FACTOR
tHDRV(OFF)/tH
relative tOFF time of HDRV
output; measured at
VHDRV = 3 V; HDRV duty factor
is determined by the relation
IHREF/IVREF
X-ray protection [XRAY (pin 2)]
VXRAY
slicing voltage level
6.14
6.38
6.64
V
tW(XRAY)
minimum width of trigger pulse
10
−
−
µs
RI(XRAY)
input resistance at XRAY
(pin 2)
VXRAY < 6.38 V + VBE
500
−
−
kΩ
VXRAY > 6.38 V + VBE
−
5
−
kΩ
−
5.6
−
V
VRESET(VCC)
supply voltage for reset of
X-ray latch
Vertical oscillator (oscillator frequency in application without adjustment of free-running frequency fv(o))
fV
free-running frequency
RVREF = 22 kΩ;
CVCAP = 100 nF
40
42
43.3
Hz
fv(o)
vertical frequency catching
range
constant amplitude;
notes 8, 9 and 10
50
−
110
Hz
VVREF
voltage at reference input for
vertical oscillator
−
3.0
−
V
td(scan)
delay between trigger pulse
and start of ramp at VCAP
(pin 24) (width of vertical
blanking pulse)
VGA presets active
500
575
650
µs
VGA presets disabled
240
300
360
µs
IVAGC
control currents of amplitude
control
±120
±200
±300
µA
CVAGC
external capacitor at VAGC
(pin 22)
−
−
150
nF
1996 Jul 18
16
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
SYMBOL
PARAMETER
TDA4855
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Differential vertical current outputs
ADJUSTMENT OF VERTICAL SIZE (see Figs 3 to 8) [VAMP (PIN 18)]
∆VAMP
IVAMP
Vref(VAMP)
IVAMP = 0; note 11
−
60
−
%
IVAMP = −135 µA; note 11
−
100
−
%
input current for maximum
amplitude (100%)
−110
−120
−135
µA
input current for minimum
amplitude (60%)
−
0
−
µA
reference voltage at input
−
5.0
−
V
2.25
2.5
2.75
vertical size adjustment range
(referenced to nominal vertical
size)
PRESETS FOR VGA MODE DEPENDENT VERTICAL SIZE
IHBUF/IHREF
minimum current ratio
IHBUF/IHREF for enable of VGA
presets
∆VAMP
variation of vertical size for
detected VGA modes
(reference for all amplitude
settings is VGA480 mode)
note 12
VGA350
−
116.8
−
%
VGA400
−
102.2
−
%
VGA480
−
100.0
−
%
IVPOS = −135 µA; note 11
−
−11.5
−
%
IVPOS = 0; note 11
−
+11.5
−
%
input current for maximum
shift-up
−110
−120
−135
µA
input current for maximum
shift-down
−
0
−
µA
Vref(VPOS)
reference voltage at input
−
5.0
−
V
Voff(VPOS)
vertical shift is centred if VPOS
(pin 17) is forced to ground
0
−
0.1
V
IVSCOR = 0; note 11
−
2
−
%
IVSCOR = −135 µA;
note 11
−
46
−
%
input current for maximum
S-correction
−110
−120
−135
µA
input current for minimum
S-correction
−
0
−
µA
−
−
±0.7
%
−
5.0
−
V
−
−
145
mV
ADJUSTMENT OF VERTICAL SHIFT (see Figs 3 to 8) [VPOS (PIN 17)]
∆VPOS
IVPOS
vertical shift adjustment range
(referenced to 100% vertical
size)
ADJUSTMENT OF VERTICAL S-CORRECTION (see Figs 3 to 8) [VSCOR (PIN 19)]
∆VSCOR
IVSCOR
vertical S-correction
adjustment range
δVSCOR
symmetry error of S-correction
Vref(VSCOR)
reference voltage at input
VSAWM(p-p)
voltage amplitude of
superimposed logarithmic
sawtooth (peak-to-peak value)
1996 Jul 18
maximum ∆VSCOR
note 13
17
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
SYMBOL
PARAMETER
TDA4855
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Vertical output stage [VOUT1 (pin 13) and VOUT2 (pin 12)]
∆IVOUT(nom)
nominal differential output
current (peak-to-peak value)
(∆IVOUT = IVOUT1 − IVOUT2)
∆IVOUT(max)
nominal settings; note 11
0.76
0.85
0.94
mA
maximum differential output
current (peak value)
(∆IVOUT = IVOUT1 − IVOUT2)
0.54
0.6
0.66
mA
VVOUT1, VVOUT2
allowed voltage at outputs
0
−
4.2
V
δV(offset)
maximum offset error of vertical nominal settings; note 11
output currents
−
−
±2.5
%
δV(lin)
maximum linearity error of
vertical output currents
nominal settings; note 11
−
−
±1.5
%
1.05
1.2
1.35
V
EW drive output
EW DRIVE OUTPUT STAGE [EWDRV (PIN 11)]
VEWDRV
bottom output voltage
(internally stabilized)
VPAR(EWDRV) = 0;
VDC(EWDRV) = 0;
EWTRP centred
maximum output voltage
note 14
7.0
−
−
V
IEWDRV
output load current
−
−
±2.0
mA
TCEWDRV
temperature coefficient of
output signal
−
−
600
10−6/K
IEWPAR = 0; note 11
−
0.05
−
V
IEWPAR = −135 µA;
note 11
−
3
−
V
input current for maximum
amplitude
−110
−120
−135
µA
input current for minimum
amplitude
−
0
−
µA
reference voltage at input
−
5.0
−
V
IEWWID = −135 µA;
note 11
−
0.1
−
V
IEWWID = 0; note 11
−
4.2
−
V
input current for maximum DC
shift
−
0
−
µA
input current for minimum DC
shift
−110
−120
−135
µA
reference voltage at input
−
5.0
−
V
ADJUSTMENT OF EW PARABOLA AMPLITUDE (see Figs 3 to 8) [EWPAR (PIN 21)]
VPAR(EWDRV)
IEWPAR
Vref(EWPAR)
parabola amplitude
ADJUSTMENT OF HORIZONTAL SIZE (see Figs 3 to 8) [EWWID (PIN 32)]
VDC(EWDRV)
IEWWID
Vref(EWWID)
1996 Jul 18
EW parabola DC voltage shift
18
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
SYMBOL
PARAMETER
TDA4855
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ADJUSTMENT OF TRAPEZIUM CORRECTION (see Figs 3 to 8) [EWTRP (PIN 20)]
IEWTRP = 0; note 11
−
−0.5
−
V
IEWTRP = −135 µA;
note 11
−
+0.5
−
V
input current for maximum
positive trapezium correction
−110
−120
−135
µA
input current for maximum
negative trapezium correction
−
0
−
µA
Vref(EWTRP)
reference voltage at input
−
5.0
−
V
Voff(EWTRP)
trapezium correction is centred
if EWTRP (pin 20) is forced to
ground
0
−
0.1
V
VPARM(p-p)
amplitude of superimposed
logarithmic parabola
(peak-to-peak value)
−
−
145
mV
24
−
80
kHz
IHREF = 1.052 mA;
fH = 31.45 kHz; note 16
1.3
1.45
1.6
V
IHREF = 2.341 mA;
fH = 70 kHz; note 16
2.7
3.0
3.3
V
function disabled; note 16 2.7
3.0
3.3
V
VTRP(EWDRV)
IEWTRP
trapezium correction voltage
note 15
TRACKING OF EWDRV OUTPUT SIGNAL WITH fH PROPORTIONAL VOLTAGE
fH(MULTI)
fH range for tracking
VPAR(EWDRV)
parabola amplitude at EWDRV
(pin 11)
δVEWDRV
linearity error of fH tracking
−
−
8
%
VEWWID
voltage range to inhibit tracking
0
−
0.1
V
VFOCUS = 1 V
−
0.03
−
mA
VFOCUS = 4 V
−
1
−
mA
Focus section [FOCUS (pin 10)]
IFOCUS(p-p)
amplitude of horizontal
parabola (peak-to-peak value)
VFOCUS(min)
input voltage for minimum
horizontal parabola amplitude
0.9
1.0
1.1
V
VFOCUS(max)
input voltage for maximum
horizontal parabola amplitude
3.65
4.0
4.4
V
1996 Jul 18
19
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
SYMBOL
PARAMETER
TDA4855
CONDITIONS
MIN.
TYP.
MAX.
UNIT
B+ control section (see Figs 12 and 13)
TRANSCONDUCTANCE AMPLIFIER [BIN (PIN 5) AND BOP (PIN 3)]
VBIN
input voltage
0
−
5.25
V
IBIN(max)
maximum input current
−
−
±1
µA
Vref(int)
reference voltage at internal
non-inverting input of OTA
2.37
2.5
2.58
V
VBOP(min)
minimum output voltage
−
0.4
−
V
VBOP(max)
maximum output voltage
5
5.3
5.6
V
IBOP < 1 mA
IBOP(max)
maximum output current
−
±500
−
µA
g
transconductance of OTA
note 17
30
50
70
mS
Gopen
open-loop gain
note 18
−
86
−
dB
CBOP
minimum value of capacitor at
BOP (pin 3)
4.7
−
−
nF
VOLTAGE COMPARATOR [BSENS (PIN 4)]
VBSENS
voltage range of positive
comparator input
0
−
5
V
VBOP
voltage range of negative
comparator input
0
−
5
V
IBSENS
maximum leakage current
−
−
−2
µA
20
−
−
mA
−
−
3
µA
discharge disabled
OPEN COLLECTOR OUTPUT STAGE [BDRV (PIN 6)]
IBDRV(max)
maximum output current
Ileakage(BDRV)
output leakage current
VBDRV = 16 V
IBDRV < 20 mA
Vsat(BDRV)
saturation voltage
toff(min)
minimum off-time
td(BDRV)
delay between BDRV pulse
and HDRV pulse
−
−
300
mV
−
250
−
ns
measured at
VHDRV, VBDRV = 3 V
−
500
−
ns
BSENS DISCHARGE CIRCUIT
VSTOP(BSENS)
discharge stop level
capacitive load;
IBSENS = 0.5 mA
0.85
1.0
1.15
V
IDISC(BSENS)
discharge current
VBSENS > 2.5 V
4.5
6
7.5
mA
fault condition
1.2
1.3
1.4
V
2
−
−
nF
VRESTART(BSENS) threshold voltage for restart
CBSENS
minimum value of capacitor at
BSENS (pin 4)
Internal reference, supply voltage and protection
VSTAB(VCC)
external supply voltage for
complete stabilization of all
internal references
9.2
−
16
V
IVCC
supply current
−
49
−
mA
PSRR
power supply rejection ratio of
internal supply voltage
50
−
−
dB
1996 Jul 18
f = 1 kHz
20
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
Notes to the characteristics
1. For duration of vertical blanking pulse see characteristics of “Vertical oscillator (oscillator frequency in application
without adjustment of free-running frequency fv(o))”.
2. Continuous blanking at CLBL (pin 16) will be activated, if one of the following conditions is true:
a) No horizontal flyback pulses at HFLB (pin 1) within a line
b) X-ray protection is triggered
c) Voltage at HPLL2 (pin 31) is low (for soft start of horizontal drive)
d) Supply voltage at VCC (pin 9) is low
e) PLL1 unlocked while frequency-locked loop is in search mode.
3. To ensure safe locking of the horizontal oscillator, one of the following procedures is required:
a) Search mode starts always from fmin. Then the PLL1 filter components are a 3.3 nF capacitor from pin 26 to
ground in parallel with an 8.2 kΩ resistor in series with a 47 nF capacitor.
b) Search mode starts either from fmin or fmax with HPOS in middle position (IHPOS = 60 µA). Then the PLL1 filter
components are a 1.5 nF capacitor from pin 26 to ground in parallel with a 27 kΩ resistor in series with a 47 nF
capacitor.
c) After locking is achieved, HPOS can be operated in the normal way.
4. Loading of HPLL1 (pin 26) is not allowed.
5. Oscillator frequency is fmin when no sync input signal is present (no continuous blanking at pin 16).
6. Voltage at HPLL1 (pin 26) is fed to HBUF (pin 27) via a buffer. Disturbances caused by horizontal sync are removed
by an internal sample-and-hold circuit.
kT
1
7. Input resistance at HPOS (pin 30): R HPOS = ------ × --------------q I HPOS
8. Full vertical sync range with constant amplitude (fV(min) : fV(max) = 1 : 2.5) can be made usable by choosing an
application with adjustment of free-running frequency.
9. If higher vertical frequencies are required, sync range can be shifted by using a smaller capacitor at VCAP (pin 24).
10. Value of resistor at VREF (pin 23) may not be changed.
11. All vertical and EW adjustments are specified at nominal vertical settings, which means:
a) ∆VAMP = 100% (IVAMP = 135 µA)
b) ∆VSCOR = 0 (pin 19 open-circuit)
c) ∆VPOS centred (pin 17 forced to ground)
d) VGA presets disabled (current ratio IHBUF : IHREF < 2.25)
e) fH = 70 kHz.
12. VGA presets are enabled below the horizontal frequency at which the current ratio IHBUF : IHREF exceeds the
specified value.
13. The superimposed logarithmic sawtooth at VSCOR (pin 19) tracks with internal VGA settings and with VPOS, but
1–d
kT
not with VAMP settings. The superimposed waveform is described by ------- × In ------------- with ‘d’ being the modulation
1+d
q
depth of a sawtooth from −5⁄6 to +5⁄6. A linear sawtooth with the same modulation depth can be recovered in an
external long-tailed pair (see Fig.17).
14. The output signal at EWDRV (pin 11) may consist of parabola + DC shift + trapezium correction. These adjustments
have to be carried out in a correct relationship to each other in order to avoid clipping due to the limited output voltage
range at EWDRV.
1996 Jul 18
21
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
15. The superimposed logarithmic parabola at EWTRP (pin 20) tracks with internal VGA settings and with VPOS, but
not with VAMP settings (see Fig.17).
16. If fH tracking is enabled, the amplitude of the complete EWDRV output signal (parabola + DC shift + trapezium) will
be changed proportional to IHREF. The EWDRV low level of 1.2 V remains fixed.
17. First pole of transconductance amplifier is 5 MHz without external capacitor (will become the second pole, if the OTA
operates as an integrator).
V BOP
18. Open-loop gain is -------------- at f = 0 with no resistive load and CBOP = 4.7 nF (from BOP (pin 3) to GND).
V BIN
Vertical and EW adjustments
MBG590
handbook, halfpage
MBG591
handbook, halfpage
VEWDRV
IVOUT1
IVOUT2
∆l2
VPAR(EWDRV)
∆l1(1)
t
t
(1) ∆I1 is the maximum amplitude setting at VAMP (pin 18);
VGA presets disabled, VPOS centred and VSCOR = 0%.
∆I 2
∆VAMP = -------- × 100%
∆I 1
∆EWPAR = 0 to VPAR(EWDRV).
Fig.4 VEWDRV as a function of time.
Fig.3 IVOUT1 and IVOUT2 as functions of time.
1996 Jul 18
22
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
MBG592
handbook, halfpage
TDA4855
handbook, halfpage
VEWDRV
IVOUT1
MBG593
IVOUT2
∆l1(1) ∆l2
VDC(EWDRV)
t
t
(1) ∆I1 is VPOS adjustment centred; maximum amplitude setting at
VAMP (pin 18) and VGA presets disabled.
∆I 2 – ∆I 1
∆VPOS = ---------------------- × 100%
2 × ∆I 1
∆EWWID = 0 to VDC(EWDRV).
Fig.6 VEWDRV as a function of time.
Fig.5 IVOUT1 and IVOUT2 as functions of time.
MBG594
handbook, halfpage
IVOUT1
MBG595
handbook, halfpage
VEWDRV
∆l2/∆t
IVOUT2
VTRP(EWDRV)
∆l1(1)/∆t
t
t
(1) ∆I1 is VSCOR = 0%; maximum amplitude setting at VAMP
(pin 18) and VGA presets disabled.
∆I 1 – ∆I 2
∆VSCOR = ---------------------- × 100%
∆I 1
∆EWTRP = ±VTRP(EWDRV).
Fig.8 VEWDRV as a function of time.
Fig.7 IVOUT1 and IVOUT2 as functions of time.
1996 Jul 18
23
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
Pulse diagrams
handbook, full pagewidth
horizontal oscillator sawtooth
at HCAP (pin 29)
horizontal sync pulse
PLL1 control current
at HPLL1 (pin 26)
+
-
video clamping pulse
at CLBL (pin 16)
triggered on
trailing edge of horizontal sync
vertical blanking level
line flyback pulse
at HFLB (pin 1)
PLL2 control current
at HPLL2 (pin 31)
+
–
PLL2
control range
line drive pulse at HDRV (pin 7)
45 to 48% of line period
horizontal focus parabola
at FOCUS (pin 10)
MBG598
Fig.9 Pulse diagram for horizontal part.
1996 Jul 18
24
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
handbook, full pagewidth
TDA4855
4.0 V automatic trigger level
3.8 V synchronized trigger level
vertical oscillator sawtooth
at VCAP (pin 24)
1.4 V
vertical sync pulse
inhibited
internal trigger
inhibit window
(typical 6.7 ms)
vertical blanking pulse
at CLBL (pin 16)
IVOUT1
differential output currents
VOUT1 (pin 13) and
VOUT2 (pin 12)
IVOUT2
7.0 V maximum
tip-parabola
EW parabola 3 V (p-p) maximum
EW drive waveform
at EWDRV (pin 11)
DC shift 4 V maximum
LOW level 1.2 V fixed
MBG597
Fig.10 Pulse diagram for vertical part.
1996 Jul 18
25
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
handbook, fullcomposite
pagewidth sync (TTL)
at HSYNC (pin 15)
internal integration of
composite sync
internal vertical
trigger pulse
PLL1 control voltage
at HPLL1 (pin 26)
clamping and blanking
pulses at CLBL (pin 16)
MGC947
a. Reduced influence of vertical sync on horizontal phase.
handbook, full pagewidth
composite sync (TTL)
at HSYNC (pin 15)
clamping and blanking
pulses at CLBL (pin 16)
MBG596
b. Generation of video clamping pulses during vertical sync with serration pulses.
Fig.11 Pulse diagrams for composite sync applications.
1996 Jul 18
26
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
APPLICATION INFORMATION
handbook, full pagewidth
2 VHDRV
VCC
Vi
R6
7
6
S
3 VBDRV
D2
Q
OTA
2.5 V
L
TR1
R
Q
HORIZONTAL
OUTPUT
STAGE
INVERTING
BUFFER
DISCHARGE
D1
1 horizontal
flyback pulse
5
3
VBIN
VBOP
4
R5
4 VBSENS
R1
C4
R4
C1
R2
C2
R3
MBG599
CBOP
>4.7 nF
EWDRV
For f < 50 kHz and C2 < 47 nF calculation formulas and behaviour of the OTA are the same as for an OP. An exception is the limited output current at
BOP (pin 3). See Chapter “Characteristics”, Row Head “B+ control section (see Figs 12 and 13)”.
a. Feedback mode application.
handbook, full pagewidth
1 horizontal
flyback pulse
2 VHDRV
ton
3 VBDRV
td(BDRV)
toff(min)
VBSENS = VBOP
VRESTART(BSENS)
4 VBSENS
VSTOP(BSENS)
MBG600
b. Waveforms for normal operation.
c. Waveforms for fault condition.
Fig.12 Application and timing for feedback mode.
1996 Jul 18
27
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
handbook, full pagewidth
TDA4855
horizontal
flyback pulse
1
VCC
2 VHDRV
R4
7
6
S
Q
R
Q
INVERTING
BUFFER
OTA
2.5 V
3 VBDRV
HORIZONTAL
OUTPUT
STAGE
EHT
transformer
D2
5 IMOSFET
DISCHARGE
5
EHT adjustment
R1
R2
TR1
3
4
VBOP
VBSENS
VBIN
R3
MBG601
D1
4
C1
CBSENS
>2 nF
TR2
power-down
CBOP > 4.7 nF
a. Forward mode application.
handbook,
pagewidth
1 full
horizontal
flyback pulse
2 VHDRV
ton
3 VBDRV
toff
td(BDRV)
VBOP
(discharge time of CBSENS)
VBOP
4 VBSENS
VRESTART(BSENS)
VSTOP(BSENS)
5 IMOSFET
MBG602
b. Waveforms for normal operation.
c. Waveforms for fault condition.
Fig.13 Application and timing for feed forward mode.
1996 Jul 18
28
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
Start-up and shut-down sequence
handbook, full pagewidth
MBG555
VCC
8.5 V continuous blanking off
PLL2 enabled
frequency detector enabled
8.2 V
5.8 V
4.0 V
video clamping pulse enabled
BDRV enabled
VOUT1 and VOUT2 enabled
VCC > 8.5 V
and
VHPLL2 > 4.4 V
VCC > 8.2 V
and
VHPLL2 > 3.7 V
PLL2 soft start sequence begins(1)
continuous blanking CLBL (pin 16) activated
time
(1) See Fig.15 for PLL2 soft-start.
a. Start-up sequence.
MBG554
handbook, full pagewidth
VCC
8.5 V continuous blanking CLBL (pin 16) activated
PLL2 disabled
frequency detector disabled
8.0 V
video clamping pulse disabled
BDRV floating
VOUT1 and VOUT2 floating
5.6 V
HDRV floating
4.0 V
continuous blanking disappears
time
b. Shut-down sequence.
Fig.14 Start-up sequence and shut-down sequence.
1996 Jul 18
29
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
PLL2 soft start sequence
MBG553
handbook, full pagewidth
VHPLL2
ea
se
s
4.4 V continuous blanking off
PLL2 enabled
frequency detector enabled
HDRV duty factor has reached nominal value
BDRV enabled
VOUT1 and VOUT2 enabled
du
ty
fa
ct
or
in
cr
3.7 V
0.5 V
HDRV duty factor begins to increase
time
a. PLL2 start-up sequence.
MBG552
handbook, full pagewidth
VHPLL2
4.4 V continuous blanking CLBL (pin 16) activated
PLL2 disabled
frequency detector disabled
3.7 V
ty
du
HDRV duty factor begins to decrease
BDRV floating
VOUT1 and VOUT2 floating
es
as
re
ec
rd
o
ct
fa
0.5 V
HDRV floating
time
b. PLL2 shut-down sequence.
Fig.15 PLL2 soft start sequence.
1996 Jul 18
30
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
Vertical linearity error
handbook, halfpage
I
VOUT
(µA)
(1)
MBG551
+415
I1(2)
I2(3)
0
I3(4)
−415
VVCAP
(1) IVOUT = IVOUT1 − IVOUT2.
(2) I1 = IVOUT at VVCAP = 1.9 V.
(3) I2 = IVOUT at VVCAP = 2.6 V.
(4) I3 = IVOUT at VVCAP = 3.3 V.
I1 – I3
Which means: I 0 = -------------2
 I1 – I2
I2 – I3 
Vertical linearity error = 1 – max  -------------- or -------------- 
I0 
 I0
Fig.16 Definition of vertical linearity error.
1996 Jul 18
31
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
Usage of superimposed waveforms
handbook, halfpage
VSCOR
19
VPOS
VAMP
EWPAR
EWWID
handbook, halfpage
EWTRP
17, 18, 21, 32
20
VPOS
VAMP
EWPAR
EWWID
17, 18, 21, 32
5 V DC
5V
5V
120 mV (p-p)
120 mV (p-p)
MBG556
MBG557
a. VSCOR (pin 19).
b. EWTRP (pin 20).
Fig.17 Superimposed waveforms at pins 19 and 20 with pins 17, 18, 21 or 32.
1996 Jul 18
5 V DC
32
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
Printed printed-circuit board layout
further connections to other components
or ground paths are not allowed
27
26
25
24
23
22
21
20
19
18
7
8
9
10
11
12
13
14
15
external components of
vertical section
6
28
29
30
31
32
external components of
horizontal section
17
handbook, full pagewidth
16
5
4
3
2
1
TDA4855
external components of
driver stages
only this path may be connected
to ground on PCB
MBG558
For optimum performance of the TDA4855 the ground paths must be routed as shown. Only one connection to other grounds on the PCB is allowed.
Fig.18 Hints for printed-circuit board (PCB) layout.
1996 Jul 18
33
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
INTERNAL CIRCUITRY
Table 5 Internal circuitry of Fig.1
PIN
1
SYMBOL
INTERNAL CIRCUIT
HFLB
1.5 kΩ
1
7x
MBG561
2
XRAY
5 kΩ
2
6.25 V
MBG562
3
BOP
5.3 V
3
MBG563
1996 Jul 18
34
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
PIN
4
TDA4855
SYMBOL
INTERNAL CIRCUIT
BSENS
4
MBG564
5
BIN
5
MBG565
6
BDRV
6
MBG566
7
HDRV
7
MBG567
8
PGND
9
VCC
power ground, connected to substrate
9
MBG568
1996 Jul 18
35
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
PIN
10
SYMBOL
TDA4855
INTERNAL CIRCUIT
FOCUS
1 kΩ
10
MBG569
11
EWDRV
108 Ω
11
108 Ω
MBG570
12
13
1996 Jul 18
VOUT2
12
MBG571
13
MBG572
VOUT1
36
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
PIN
14
TDA4855
SYMBOL
INTERNAL CIRCUIT
VSYNC
100 Ω
1.4 V
14
2 kΩ
7.3 V
MBG573
15
HSYNC
1.28 V
85 Ω
1.4 V
15
MBG574
16
CLBL
16
MBG575
17
VPOS
2 VBE
7.2 kΩ
17
5V
1 kΩ
MBG576
1996 Jul 18
37
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
PIN
18
TDA4855
SYMBOL
INTERNAL CIRCUIT
VAMP
18
5V
MBG577
19
VSCOR
19
5V
MBG578
20
EWTRP
2 VBE
20
5V
MBG579
1996 Jul 18
38
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
PIN
21
TDA4855
SYMBOL
INTERNAL CIRCUIT
EWPAR
21
5V
1 kΩ
MBG580
22
VAGC
22
MBG581
23
VREF
23
3V
MBG582
24
VCAP
24
MBG583
25
1996 Jul 18
SGND
signal ground
39
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
PIN
26
TDA4855
SYMBOL
INTERNAL CIRCUIT
HPLL1
26
5.5 V
MBG589
27
HBUF
27
MBG584
28
HREF
29
HCAP
76 Ω
2.525 V
28
7.7 V
29
MBG585
30
HPOS
1.7 V
7.7 V
1 kΩ
30
4.3 V
MBG586
1996 Jul 18
40
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
PIN
31
SYMBOL
TDA4855
INTERNAL CIRCUIT
HPLL2
7.7 V
31
HFLB
MBG587
32
EWWID
2 VBE
7.2 kΩ
32
5V
1 kΩ
MBG588
Electrostatic discharge (ESD) protection
pin
pin
7.3 V
MBG559
7.3 V
MBG560
Fig.20 ESD protection for pins 2 to 4, 17 to 24 and
26 to 32.
Fig.19 ESD protection for pins 4, 10 to 13 and 16.
1996 Jul 18
41
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
PACKAGE OUTLINE
SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)
SOT232-1
ME
seating plane
D
A2 A
A1
L
c
e
Z
(e 1)
w M
b1
MH
b
17
32
pin 1 index
E
1
16
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.7
0.51
3.8
1.3
0.8
0.53
0.40
0.32
0.23
29.4
28.5
9.1
8.7
1.778
10.16
3.2
2.8
10.7
10.2
12.2
10.5
0.18
1.6
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-02-04
SOT232-1
1996 Jul 18
EUROPEAN
PROJECTION
42
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Soldering by dipping or by wave
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Jul 18
43
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101, Fax. +43 1 60 101 1210
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 708 296 8556
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 1949
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 615 800, Fax. +358 615 80920
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 52 60, Fax. +49 40 23 536 300
Greece: No. 15, 25th March Street, GR 17778 TAVROS,
Tel. +30 1 4894 339/911, Fax. +30 1 4814 240
Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722
Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,
Tel. +972 3 645 0444, Fax. +972 3 648 1007
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +1 800 234 7381, Fax. +1 708 296 8556
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 83749, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 926 5361, Fax. +7 095 564 8323
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 829 1849
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 632 2000, Fax. +46 8 632 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 481 7730
Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,
Chung Hsiao West Road, Sec. 1, P.O. Box 22978,
TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Ukraine: PHILIPS UKRAINE, 2A Akademika Koroleva str., Office 165,
252148 KIEV, Tel. +380 44 476 0297/1642, Fax. +380 44 476 6991
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 708 296 8556
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 825 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com/ps/
(1) TDA4855_1 June 26, 1996 11:51 am
© Philips Electronics N.V. 1996
SCA50
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/51/01/pp44
Date of release: 1996 Jul 18
Document order number:
9397 750 00973