SAMSUNG S1D2512X01-A0B0

JUL. 2000
Ver 0.3
DATA SHEET
S1D2512X01
Preliminary
S1D2512X01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
DEFLECTION PROCESSOR
32-SDIP-400
The S1D2512X01 is a monolithic integrated circuit assembled in 32 pins
shrunk dual in line plastic package. This IC controls all the functions
related to the horizontal and vertical deflection in multi modes or multifrequency computer display monitors.
The internal sync processor, combined with the very powerful geometry
correction block make the S1D2512X01 suitable for very high
performance monitors with very few external components. The horizontal
jitter level is very low. It is particularly well suited for high-end 17” and
19” monitors.
FUNCTIONS
•
Deflection processor
•
I2C bus control
•
B+ regulator
•
Vertical parabola generator
•
Vertical dynamic focus
ORDERING INFORMATION
Device
Package
Operating Temperature
S1D2512X01-A0B0
32-SDIP-400
0 °C — 70°C
•
FEATURES
Horizontal dynamic phase (side pin balance &
parallelogram)
•
Vertical dynamic focus (Vertical focus amplitude)
(HORIZONTAL)
(GENERAL)
•
Self-adaptive
•
Sync processor
•
Dual PLL concept
•
12V supply voltage
•
150kHz maximum frequency
•
Hor. & Vert. lock/unlock outputs
•
X-RAY protection input
•
Read/Write I2C interface
•
I2C controls: Horizontal duty-cycle, H-position, free
running frequency, frequency generator for burn-in
mode.
•
Horizontal and vertical moire
•
B+ Regulator
- Internal PWM generator for B+ current mode
step-up converter.
(VERTICAL)
•
Vertical ramp generator
•
50 to 185Hz AGC loop
•
Geometry tracking with V-POS & V-AMP
•
I2C Controls: V-AMP, V-POS, S-CORR, C-CORR
•
DC breathing compensation
- I2C adjustable B+ reference voltage
- Output pulses synchronized on horizontal
frequency
- Internal maximum current limitation.
- Soft start
•
(I2C GEOMETRY CORRECTIONS)
•
1
Vertical parabola generator
(pincushion-E/W, keystone, corner)
Compared with the S1D2511B, S1D2512X HAS:
- Corner correction
- Horizontal moire
- B+ soft start
- Increased max. Vertical frequency
- No horizontal focus
- No step down option for DC/DC converter.
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2512X01
HREF
13
VR
H POSITION
HLOCKOUT
R0
C0
HFLY
PLL2C
HOUT
7
8
3
6
5
12
4
26
PHASE/
FREQUENCY
COMPARATOR
H-PHASE(7 bits)
EF
HGND
PLL1F
BLOCK DIAGRAM
11
LOCK/UNLOCK
IDENTIFICATION
H/HVIN
VSYNCIN
PHASE
SHIFTER
Forced
Freq.
2 bits
SYNC INPUT
SELECT
(1bit)
H-DUTY
(5 bits)
HOUT
BUFFER
5V
Vcc
XRAY
SAFETY
PROCESSOR
Free running
5 bits
1
2
PHASE
COMPARATOR
VCO
B+ ADJUST
7 bits
B+
CONTROLLER
X2
SYNC
PROCESSOR
+
Spin Bal
6 bits
HSYNC
29
XRAY
25
VREF
21
VGND
19
SDA
31
SCL
30
Horizontal
Moire Cancel
5 bits + on/off
Key Bal
6 bits
GEOMETRY
TRACKING
6 bits
32
28
B+ OUT
15
REGIN
16
ISENSE
17
BGND
9
HMOIRE
10
FOCUS
MOIRE
CANCEL
5 BITS+ON/OFF
VR
EF
5V
COMP
X2
VSYNC
VCC
14
AMPVDF
6 bits
X4
8 bits
RESET
GENERATOR
EW
7 bits
X2
VAMP
7 bits
S AND C
CORRECTION
Corner
7 bits
VERTICAL
OSCILLATOR
RAMP GENERATOR
+
keyst
6 bits
I 2 C INTERFACE
X
+
27
22
20
18
23
24
VACCAP
BREATH
VOUT
EWOUT
VPOS
7bits
VCAP
GND
2
S1D2512X01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
PIN CONFIGURATIONS
H/HVIN
5V
32
2
VSYNCIN
SDA
31
3
HLOCKOUT
SCL
30
4
PLL2C
VCC
29
5
C0
BOUT
28
6
R0
GND
27
7
PLL1F
HOUT
26
8
HPOSITION
XRAY
25
9
HMOIRE
EWOUT
24
10
FOCUSOUT
VOUT
23
11
HGND
VCAP
22
12
HFLY
VREF
21
13
HREF
VAGCCAP
20
14
COMP
VGND
19
15
REGIN
BREATH
18
16
ISENSE
B+GND
17
KB2512
1
S1D2512X
3
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2512X01
PIN DESCRIPTION
Table 1. Pin Description
No
Pin Name
Description
1
H/HVIN
TTL compatible horizontal sync input (separate or composite)
2
VSYNCIN
TTL compatible vertical sync input (for separated H&V)
3
HLOCKOUT
First PLL lock/unlock output (0V unlocked - 5V locked)
4
PLL2C
Second PLL loop filter
5
C0
Horizontal oscillator capacitor
6
R0
Horizontal oscillator resistor
7
PLL1F
First PLL loop filter
8
HPOSITION
Horizontal position filter (capacitor to be connected to HGND)
9
HMOIRE
Horizontal moire output (to be connected to PLL2 C through a resistor divider)
10
FOCUSOUT
Vertical dynamic focus output
11
HGND
Horizontal section ground
12
HFLY
Horizontal Flyback input (positive polarity)
13
HREF
Horizontal section reference voltage (to be filtered)
14
COMP
B+ error amplifier output for frequency compensation and gain setting
15
REGIN
Regulation input of B+ control loop
16
ISENSE
Sensing of external B+ switching transistor current
17
B+GND
Ground (related to B+ reference adjustment)
18
BREATH
DC breathing input control (compensation of vertical amplitude against EHV
variation)
19
VGND
Vertical section ground
20
VAGCCAP
Memory capacitor for automatic gain control loop in vertical ramp generator
21
VREF
Vertical section reference voltage (to be filtered)
22
VCAP
Vertical sawtooth generator capacitor
23
VOUT
Vertical ramp output
(with frequency independent amplitude and S or C corrections if any).
It is mixed with vertical position voltage and vertical moire.
24
EWOUT
Pincushion-East/West correction parabola output
25
XRAY
X-RAY protection input (with internal latch function)
26
HOUT
Horizontal drive output (internal transistor, open collector)
27
GND
General ground (referenced to Vcc)
28
BOUT
B+ PWM regulator output
29
Vcc
Supply voltage (12V typ)
30
SCL
I2C clock input
31
SDA
I2C data input
32
5V
Supply voltage (5V typ)
4
S1D2512X01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
REFERENCE DATA
Table 2. Reference Data
Parameter
Value
Unit
Horizontal frequency
15 to 150
kHz
Autosynch frequency (for given R0 and C0)
1 to 4.5FO
FH
± Horizontal sync polarity input
Yes
Polarity detection (on both horizontal and vertical section)
Yes
TTL composite sync
Yes
Lock/unlock identification (on both horizontal 1st PLL and vertical section)
Yes
I2C control for H-position
±10
XRAY protection
Yes
I2C horizontal duty cycle adjust
I2C free running frequency adjustment
%
30 to 60
%
0.8 to 1.3FO
FH
Stand-by function
Yes
Dual polarity H-drive outputs
No
Supply voltage monitoring
Yes
PLL1 inhibition possibility
No
Blanking output
No
Vertical frequency
35 to 200
Hz
Vertical Autosync (for 150nf on pin22 and 470nf on pin20)
50 to 185
Hz
Vertical S correction
Yes
Vertical C correction
Yes
Vertical amplitude adjustment
Yes
DC breathing control on vertical amplitude
Yes
Corner correction
Yes
East/West parabola output (also known as pin cushion output)
Yes
East/West correction amplitude adjustment
Yes
Keystone adjustment
Yes
Vertical position adjustment
Yes
Internal dynamic horizontal phase control
Yes
Side pin balance amplitude adjustment
Yes
Parallelogram adjustment
Yes
Tracking of geometric corrections with vertical amplitude and position
Yes
Reference voltage (both on horizontal and vertical)
Yes
5
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2512X01
Table 2. Reference Data (Continued)
Parameter
Value
Vertical dynamic focus
Yes
I2C horizontal dynamic focus amplitude adjustment
No
I2C horizontal dynamic focus symmetry adjustment
No
I2C vertical dynamic focus amplitude adjustment
Yes
Deflection of input sync type
Yes
Vertical moire output
Yes
Horizontal moire output
Yes
I2C controlled moire amplitude
Yes
Frequency generator for burn-in
Yes
Fast I2C read/write
400
B+ regulation adjustable by I2C
Yes
B+ soft start
Yes
Unit
kHz
6
S1D2512X01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
ABSOLUTE MAXIMUM RATINGS
Table 3. Absolute Maximum Ratings
No
Item
Symbol
Value
Unit
1
Supply voltage (Pin 29)
VCC
13.5
V
2
Supply voltage (Pin 32)
VDD
5.7
V
3
Maximum voltage on Pin 4
Pin 5
Pin 6, 7, 8, 14, 15, 16, 20, 22
Pin 9, 10, 18, 23, 24, 25, 26, 28
Pin 1, 2, 3, 30, 31
VIN
4.0
6.4
8.0
VCC
VDD
V
V
V
V
V
4
ESD susceptibility
Human body model, 100pF discharge through 1.5KΩ
EIAJ norm, 200pF discharge through 0Ω
VESD
2
kV
300
V
5
Storage temperature
Tstg
- 40, +150
°C
6
Operating temperature
Topr
0, +70
°C
THERMAL CHARACTERISTICS
Table 4. Thermal Characteristics
No
Item
Symbol
Value
Unit
1
Junction temperature
Tj
+150
°C
2
Junction-ambient thermal resistance
θja
65
°C/W
SYNC PROCESSOR
OPERATING CODNITIONS(VDD = 5V, Tamb = 25 °C)
Table 5. Sync Processor Operating Conditions
Parameter
Symbol
Conditions
Min
Horizontal sync input voltage
HsVR
Pin 1
0
Minimum horizontal input pulse duration
MinD
Pin 1
0.7
Maximum horizontal input signal duty cycle
Mduty
Pin 1
Vertical sync input voltage
VsVR
Pin 2
0
Minimum vertical sync pulse width
VSW
Pin 2
5
Maximum vertical sync input duty cycle
VSmD
Pin 2
15
%
Maximum vertical sync width on TTL H/V composite
VextM
Pin 1
750
µs
IHLOCKOUT
Pin 3
250
µA
Sink and source current
7
Typ
Max
Unit
5
V
µs
25
%
5
V
µs
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2512X01
ELECTRICAL CHARACTERISTICS
(VDD = 5V, Tamb = 25 °C)
Table 6. Sync Processor Electrical Characteristics
Parameter
Symbol
Conditions
Min
Horizontal and vertical input threshold
voltage (pin 1, 2)
VINTH
Low level
High level
Horizontal and vertical pull-up resister
RIN
Falling and rising output CMOS buffer
TfrOut
Pin 3, Cout = 20pF
Horizontal 1st PLL lock output status
(pin 3)
VHlock
Locked, ILOCKOUT = -250µA
Extracted Vsync integration time (% of
TH (see 9)) on H/V composite
VoutT
Typ
Max
Unit
0.8
V
V
2.2
Pins 1,2
200
Unlocked, I LOCKOUT = +250µA
4.4
0
5
C0 = 820pF
26
35
KΩ
200
ns
0.5
V
V
%
I2C READ/WRITE (See also I2C table control and I2C sub address control)
OPERATING CONDITIONS (VDD = 5V, Tamb = 25 °C)
Table 7. I2C Read/Write Operating Conditions
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Input high level voltage
VinH
3.0
-
5.0
V
Input low level voltage
VinL
0
-
1.5
V
Hold time before a new
transmission can start
tBUF
1.3
-
-
µs
Hold time for start conditions
tHDS
0.6
-
-
µs
Set-up time for stop conditions
tSUP
0.6
-
-
µs
tHDAT
0.3
-
-
µs
Set-up time data
tSUPDAT
0.25
-
-
µs
Rise time of SCL
tR
-
-
1.0
µs
Fall time of SCL
tF
-
-
3.0
µs
400
kHz
Hold time data
Maximum clock frequency
Fscl
Pin 30
Low period of the SCL clock
Tlow
Pin 30
1.3
µs
High period of the SCL clock
Thigh
Pin 30
0.6
µs
SDA and SCL input threshold
Vinth
Pin 30, 31
Acknowledge output voltage on
SDA input with 3mA
VACK
Pin 31
2.2
V
0.4
V
8
S1D2512X01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
I2C Bus Timing Requirement
tBUF
Start:Clock High
Stop:Clock High
tHDAT
SDA
tHDS
SCL
tSUPDAT
tSUP
tLOW
tHIGH
Data Change:Clock Low
HORIZONTAL SECTION
OPERATING CONDITIONS
Table 8. Horizontal Section Operating Conditions
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VCO
Minimum oscillator resistor
Ro(Min.)
Pin 6
6
KΩ
Minimum oscillator capacitor
Co(Min.)
Pin 5
390
pF
Maximum oscillator frequency
Fo(Max.)
150
kHz
OUTPUT SECTION
Maximum input peak current
I12m
Pin 12
5
mA
Horizontal drive output maximum
current
HOI
Pin 26, sunk current
30
mA
ELECTRICAL CHARACTERISTICS (VDD = 5V, Tamb = 25 °C)
Table 9. Horizontal Section Electrical Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SUPPLY AND REFERENCE VOLTAGE
Supply voltage
Vcc
Pin 29
10.8
12
13.2
V
Supply voltage
VDD
Pin 32
4.5
5
5.5
V
Supply current
ICC
Pin 29
50
mA
Supply current
IDD
Pin 32
5
mA
Horizontal reference voltage
VREF-H
Pin 13, I = -2mA
7.4
8
8.6
V
Vertical reference voltage
VREF-V
Pin 21, I = -2mA
7.4
8
8.6
V
9
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2512X01
Table 9. Horizontal Section Electrical Characteristics (Continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Max. sourced current on VREF-H
IREF-H
Pin 13
5
mA
Max. sourced current on VREF-V
IREF-V
Pin 21
5
mA
Polarity integration delay
HpoIT
Pin 1
VCO control voltage (pin 7)
VVCO
VREF-H = 8V
1st PLL SECTION
VCO gain (pin 7)
VCOG
Horizontal phase adjustment (see 11)
Hph
Horizontal phase setting value (Pin 8)
0.75
ms
fo
fH (Max.)
1.3
6.2
V
V
Ro = 6.49KΩ,
Co = 820pF,
dF/dV = 1/11RoCo
17
kHz/V
% of horizontal period
±10
%
2.8
3.4
4.0
V
V
V
Sub-address 01
(see 11)
Minimum current value
Typical value
Maximum value
Hphmin
Hphtyp
Hphmax
PLL1 filter current charge
Free running frequency
Free running frequency thermal drift (no
drift on external components)
Safe forced frequency
SF1 Byte 11 x x x x x x
SF2 Byte 10 x x x x x x
IPII1U
IPII1L
PLL1 is unlocked
PLL1 is locked
±140
±1
µA
mA
fo
Ro = 6.49KΩ,
Co = 820pF,
fo = 0.97/8RoCo
22.8
kHz
-150
ppm/c
0.8
1.3
Fo
Fo
dF0/dT
(see 7)
Free running frequency adjustment
Minimum value
Maximum value
PLL1 capture range
Byte x 1111111
Byte x 1000000
Byte x 0000000
fo(Min.)
fo(Max.)
CR
SFF
Sub-address 02
Byte x x x 11111
Byte x x x 00000
Ro = 6.49KΩ,
Co = 820pF,
from fo + 0.5kHz to
4.5Fo (fo:22.8kHz)
fH (min.)
fH (max.)
23.5
100
kHz
kHz
Sub-address 02
2F0
3F0
2ND PLL SECTION HORIZONTAL OUTPUT SECTION
Flyback input threshold
voltage (pin12)
Horizontal jitter
FBth
Hjit
0.65
At 31.4kHz
0.75
V
70
ppm
10
S1D2512X01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
Table 9. Horizontal Section Electrical Characteristics (Continued)
Parameter
Symbol
X-RAY protection input threshold
voltage
Internal clamping levels on 2nd PLL
loop filter (pin 4)
Min
Typ
Max
Unit
Sub-address 00
Horizontal drive output duty-cycle
(pin 26) (see 1)
Low level
High level
Conditions
Byte xxx00000 (see 2)
30
60
%
%
Pin 25 (see 12)
8
V
Low level
High level
1.6
4.0
V
V
HDmin
HDmax
Byte xxx11111
XRAYth
Vphi2
Threshold voltage to stop H-out, V-out,
B-out and reset XRAY when VCC <
VSCinh
VSCinh
Pin 29
7.5
V
Threshold voltage to stop H-out, V-out,
B-out and reset XRAY when VDD <
VSDinh
VSDinh
Pin 32
4.0
V
Horizontal drive output (low level)
HDvd
Pin 26 IOUT = 30mA
0.4
V
VERTICAL DYNAMIC FOCUS FUNCTION (POSITIVE PARABOLA)
Bottom DC output level
HDFDC
DC output voltage thermal drift (see 17)
TDHDF
Vertical dynamic focus parabola
amplitude with VAMP and VPOS typical
Min. Byte 000000
Typ. Byte 100000
Max. Byte 111111
AMPVDF
Parabola amplitude function of VAMP
(tracking between VAMP and VDF) with
VPOS typ. (Figure 1) (see 3)
VDFAMP
Parabola asymmetry function of VPOS
control (tracking between VPOS and
VDF) with VAMP Max.
VHDFKeyt
11
RLOAD = 10KΩ, Pin 10
2
V
200
ppm/C
0
0.5
1
Vpp
Vpp
Vpp
Sub-address 05
Byte 10000000
Byte 11000000
Byte 11111111
0.6
1
1.5
Vpp
Vpp
Vpp
Sub-address 06
Byte x0000000
Byte x1111111
0.52
0.52
Vpp
Vpp
Sub-address 0F
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2512X01
VERTICAL SECTION
OPERATING CONDITIONS
Table 10. Vertical Section Operating Conditions
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
6.5
V
OUTPUTS SECTION
Maximum EW output voltage
VEWM
Pin 24
Minimum EW output voltage
VEWm
Pin 24
1.8
V
Minimum load for less than 1% vertical amplitude
drift
RLOAD
Pin 20
65
MΩ
ELECTRICAL CHARACTERISTICS (VCC = 12V, TAMB = 25 °C)
Table 11. Vertical Section Electrical Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VERTICAL RAMP SECTION
Voltage at ramp bottom point
VRB
VREF-V = 8V,
2
V
5
V
VRT-0.1
V
70
µs
100
Hz
Pin 22
Voltage at ramp top point (with sync)
VRT
VREF-V = 8V,
Pin 22
Voltage at ramp top point (without sync)
VRTF
Pin 22
Vertical sawtooth discharge time duration
(pin 22)
VSTD
With 150nF cap
Vertical free running frequency see (see 4)
VFRF
COSC (pin22) =150nF
measured on
pin 22
AUTO -SYNC frequency (see 13)
ASFR
C22=150nF ± 5%
Ramp amplitude drift versus frequency at
Maximum vertical amplitude
RAFD
C22 = 150nF
Ramp linearity on pin 22 (∆I22/I22) (see 4)
RIin
Vertical position adjustment voltage
(pin 23 - VOUT centering)
Vpos
Vertical output voltage
(peak-to-peak on pin 23)
Vertical output maximum current (pin 23)
50
185
200
ppm/
Hz
2.5 < V22 < 4.5V
0.5
%
Sub address 06
Byte x0000000
Byte x1000000
Byte x1111111
3.3
3.65
3.2
3.5
3.8
V
V
V
2.5
3.5
2.25
3
3.75
V
V
V
50Hz < f < 185Hz
VOR
VOI
Hz
Sub address 05
Byte x0000000
Byte x1000000
Byte x1111111
±5
mA
12
S1D2512X01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
Table 11. Vertical Section Electrical Characteristics (Continued)
Parameter
Symbol
Max vertical S-correction amplitude (see 14)
XOXXXXXX inhibits S-CORR
X1111111 gives max S-CORR
dVS
Vertical C-Corr amplitude
XOXXXXXX inhibits C-corr
Ccorr
Conditions
Min
Typ
Max
Unit
Sub address 07
∆V/Vpp at TV/4
∆V/Vpp at 3TV/4
-4
+4
%
%
Sub address 08
∆V/Vpp at TV/2
Byte X1000000
Byte X1100000
Byte X1111111
-3
0
3
%
%
%
2.5
V
100
ppm/
C
Sub address 0A
Byte 1111111
Byte 1100000
Byte 1000000
1.7
0.85
0
Vpp
Vpp
Vpp
Sub address 05
Byte 1000000
Byte 1100000
Byte 1111111
0.30
0.55
0.85
Vpp
Vpp
Vpp
Sub address 09
Byte 1x000000
Byte 1x111111
0.65
0.65
Vpp
Vpp
EAST/WEST FUNCTION
DC output voltage with typ. Vpos, keystone
and corner inhibited
EWDC
pin 24,
see figure 2
DC output voltage thermal drift
TDEWDC see note 7
Parabola amplitude with max. Vamp,
typ. V-Pos, keystone and corner inhibited
EWpara
Parabola amplitude function of V-AMP control
(tracking between V-AMP and E/W) with typ.
Vpos, typ. EW amplitude, keystone and corner
inhibited (see 8)
EWtrack
Keystone adjustment capability with typ.Vpos,
corner and E/W inhibited and max. vertical
amplitude. (see 8)
KeyAdj
Intrinsic keystone function of V-POS control
(tracking between V-pos and EW) max. E/W
and max. vertical amplitude and corner
inhibited. (see 7)
A/B ratio
B/A ratio
KeyTrack
Corner amplitude with max. VAMP, typ.
VPOS,
keystone and E/W inhibit
Corner
Sub address 06
Byte x0000000
Byte x1111111
0.52
0.52
Sub address 0B
Byte 11111111
Byte 11000000
Byte 10000000
1.7
0
-1.7
Vpp
Vpp
Vpp
+1.4
-1.4
%T H
%T H
INTERNAL HORIZONTAL DYNAMIC PHASE CONTROL FUNCTION
Side pin balance parabola amplitude (Figure3)
with max. Vamp, typ. V-POS and
parallelogram inhibited (see 8, 9)
13
SPBpara Sub address 0D
Byte x1111111
Byte x1000000
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2512X01
Table 11. Vertical Section Electrical Characteristics (Continued)
Parameter
Side pin balance parabola amplitude function
of Vamp control (tracking between Vamp and
SPB) with max. SPB, typ. V-POS and
parallelogram inhibited (see 8, 9)
Symbol
Conditions
Min
SPBtrack Sub address 05
Byte 10000000
Byte 11000000
Byte 11111111
Parallelogram adjustment capability with max.
Vamp, typ. V-POS and max. SPB (see8, 9)
ParAdj
Intrinsic parallelogram function of Vpos control
(tracking between V-pos and DHPC) with max.
Vamp, max. SPB and parallelogram inhibited
Partrack
(see 8, 9)
Sub address 0E
Byte x1111111
Byte x1000000
Max
Unit
0.5
0.9
1.4
%T H
%T H
%T H
+1.4
-1.4
%T H
%T H
Sub address 06
Byte x0000000
Byte x1111111
A/B ratio
B/A ratio
Typ
0.52
0.52
VERTICAL MOIRE
Vertical moire (measured on VOUT) pin 23
VMOIRE
Sub address 0C
Byte 01x11111
6
mV
BREATHING COMPENSATION
DC breathing control range (see 15)
Vertical output variation versus DC breathing
control (Pin 23)
BRRANG
BRADj
V18
V18 ≥ VREF-V
V18 = 4V
1
12
0
-10
V
%
%
14
S1D2512X01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
B+ SECTION
OPERATING CONDITIONS
Table 12. B+ Section Operating Conditions
Parameter
Symbol
Minimum feedback resistor
Conditions
Min
FeedRes Resistor between pins 15 and 14
Typ
Max
5
Unit
KΩ
ELECTRICAL CHARACTERISTICS
(VCC = 12V, Tamb = 25 °C)
Table 13. B+ Section Electrical Characteristics
Parameter
Symbol
Conditions
Error amplifier open loop gain
OLG
At low frequency
Sunk current on error amplifier output
when BOUT is in safety condition
Icomp
Pin 14 (see 12)
Unity gain band width
UGBW
(see 7)
Regulation input bias current
(see 10)
Min
Typ
Max
Unit
85
dB
0.5
mA
6
MHz
0.2
µA
IRI
Current sourced by pin 15
(PNP base)
Maximum guaranteed error amplifier
output current
EAOI
Current sourced by pin 14
Current sunk by pin 14
Current sense input voltage gain
CSG
Pin 16
3
MCEth
Pin 16
1.2
V
1
µA
100
%
V28 with I28 = 10mA
0.25
V
On error amp positive input
for subaddress 0B
Byte 1000000
4.8
V
Byte 111111
Byte 000000
+20
-20
%
%
Pin 28
100
ns
Max current sense input threshold
voltage
Current sense input bias current
ISI
Maximum external power transistor on
time
Tonmax
B+ output saturation voltage
B+OSV
Internal reference voltage
Internal reference voltage adjustment
range
Falling time
15
Current sourced by pin 16
(PNP base)
% of H-period
@ fo = 27kHz
IVREF
VREFADJ
tFB+
0.5
2
mA
mA
(see 6)
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2512X01
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
Duty cycle is the ratio of power transistor off time period. Power transistor is off when output transistor is off.
Initial condition for safe operation start up.
S and C correction are inhibited so the output sawtooth has a linear shape.
With register 07 at byte x0xxxxxx (s-correction is inhibited) then the S correction is inhibited, and with register 08 at byte
x0xxxxxx (C-Correction is inhibited) consequently the sawtooth has a linear shape.
These parameters are not tested on each unit. They are measured during our internal qualification.
The external power transistor is OFF during 400ns.
These parameters are not tested on each unit. They are measured during out internal qualification.
Refers to notes 4.
TH is the Horizontal period.
These parameters are not tested on each unit. They are measured during our internal qualification procedure which
includes characterization on batches coming from corners of our processes and also temperature characterization.
See Figure 7 for explanation of reference phase.
See Figure 11.
This is the frequency range for which the vertical oscillator will automatically synchronize, using a single capacitor value on
Pin 22 and with a constant ramp amplitude.
TV is the vertical period.
When not used the DC breathing control pin must be connected to 12V.
CAUTIONS:
The ICS near CDT can be latched up by EHT. Therefore, in order to minimize the impact of the EHT, it is necessary to place
ICs far from CDT.
If you have not applied below recommendation, a parasitic effect of ionizing field induced by CDT EHT (Extremely
High Tension) make stock charges between resin and chip surface. In this case, abnormal leakage is increased.
And may cause no operation failure. For protecting CDT’s EHT interference, it is necessary to add metal-sheet for
isolating or locate ICs far from CDT.
Photo#1: Isolation used by metal sheet
Photo#2: Not locate near-by CDT
16
S1D2512X01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
VDFAMP
B
A
HDFDC
Figure 1. Vertical Dynamic Focus Function
EWPARA
B
A
EWDC
Figure 2. E/W Output
B
A
SPBPARA
DHPCPC
Figure 3. Dynamic Horizontal Phase Control Output
17
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2512X01
Table 14. Typical Vertical Output Wave forms
Function
Sub
Address
Pin
Vertical Size
05
23
Byte
10000000
Specification
Picture Image
VOUTDC
2.25V
VOUTDC
3.75V
11111111
Vertical
Position
DC
Control
06
Vertical
S
Linearity
07
23
x0000000
x1000000
x1111111
23
x0xxxxxx
Inhibited
x1111111
Vertical
C
Linearity
3.2V
3.5V
3.8V
08
∆V
Vpp
∆V =4%
Vpp
23
∆V
x1000000
Vpp
∆V =3%
Vpp
∆V
Vpp
x1111111
∆V =3%
Vpp
18
S1D2512X01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
Table 15. Geometry Output Wave forms
Function
Sub
address
Pin
Byte
Key stone
(trapezoid)
control
09
24
E/W + corner
inhibited
Specification
Picture Image
0.65V
2.5V
0.65V
2.5V
2.5V
0V
1x000000
1x111111
E/W
(pin cushion)
control
0A
24
Keystone +
corner Inhibited
10000000
1.7V
1111111
Corner control
0B
24
Keystone + E/W
inhibited
1.7V
2.5V
11111111
1.7V
10000000
Parallelogram
control
0E
Internal
SPB
Inhibited
3.7V
1.4% TH
1x000000
3.7V
1.4% T H
3.7V
1.4% TH
3.7V
1.4% TH
1x111111
Side pin
balance
control
0D
Internal
Parallelogram
Inhibited
1x000000
1x111111
Vertical
dynamic
focus
OF
10
2V
TV
19
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2512X01
I2C BUS ADDRESS TABLE
Slave address (8C): Write mode
Sub address definition
Table 16. I2C Bus Address Table
D8
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
0
Horizontal drive selection/horizontal duty cycle
1
0
0
0
0
0
0
0
1
Horizontal position
2
0
0
0
0
0
0
1
0
Forced Frequency/free running frequency
3
0
0
0
0
0
0
1
1
Synchro priority/horizontal moire amplitude
4
0
0
0
0
0
1
0
0
Refresh/B+ reference adjustment
5
0
0
0
0
0
1
0
1
Vertical ramp amplitude
6
0
0
0
0
0
1
1
0
Vertical position adjustment
7
0
0
0
0
0
1
1
1
S correction
8
0
0
0
0
1
0
0
0
C correction
9
0
0
0
0
1
0
0
1
E/W keystone
A
0
0
0
0
1
0
1
0
E/W amplitude
B
0
0
0
0
1
0
1
1
E/W corner adjustment
C
0
0
0
0
1
1
0
0
Vertical moire amplitude
D
0
0
0
0
1
1
0
1
Side pin balance
E
0
0
0
0
1
1
1
0
Parallelogram
F
0
0
0
0
1
1
1
1
Vertical dynamic focus amplitude
Slave address (8D): Read mode
No sub address needed
20
S1D2512X01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
Table 17. I 2C Bus Address Table (continued)
D8
D7
D6
D5
D4
D3
D2
D1
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
WRITE MODE
00
HDrive
0: off
[1]: on
01
Xray
1: reset
[0]
02
Horizontal duty cycle
[0]
[0]
Horizontal phase adjustment
[1]
[0]
[0]
[0]
Forced frequency
03
04
05
Free running frequency
1: on
[0]: off
1: F0x2
[0]: F0x3
Sync
0: comp
[1]: sep
HMoire
1: on
[0]
Detect
refresh
[0]: off
[1]
Vramp
0: off
[1]: on
[0]
[0]
[0]
[0]
[0]
[0]
Horizontal moire amplitude
[0]
B+ reference adjustment
[0]
[0]
Vertical ramp amplitude adjustment
[1]
[0]
[0]
[1]
[0]
[0]
06
[0]
Vertical position adjustment
07
[1]
[0]
[0]
[1]
[0]
[0]
[1]
[0]
[1]
[0]
[0]
E/W cor
0: off
[1]
[1]
[0]
[0]
Test V
1: on
[0]: off
Vmoire
1: on
[0]
C correction
C Select
1: on
[0]
09
[0]
S correction
S Select
1: on
[0]
08
East/west keystone
EW key
0: off
[1]
[0]
0A
East/west amplitude
0B
0C
0D
0E
[0]
East/west corner adjustment
SPB sel
0: off
[1]
[0]
Vertical moire
[0]
[0]
[0]
[0]
Side pin balance
[1]
Parallelogram
0: off
[1]
[1]
[0]
Test H
1: on
[0]: off
[1]
[0]
0F
[0]
Parallelogram
[0]
Vertical dynamic focus amplitude
[0]
[0]
V pol
[1], negative
Vext det
[0], no det
READ MODE
00
Hlock
0: on
[1]: no
Vlock
0: on
[1]: no
Xray
1: on
[0]: off
Polarity detection
H/V pol
[1], negative
Synchro detection
[ ] initial value
Set the unspecified bit to [0] in order to assure the compatibility with future devices.
21
H/V det
[0], no det
V det
[0], no det
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2512X01
OPERATING DESCRIPTION
GENERAL CONSIDERATIONS
Power Supply
The typical values of the power supply voltages Vcc and VDD are respectively 12V and 5V. Optimum operation is
obtained if Vcc and VDD are maintained in the limits: 10.8 to 13.2V and 4.5 to 5.5V.
In order to avoid erratic operation of the circuit during the transient phase of Vcc and VDD switching on, or switching
off, the value of Vcc and VDD are monitored and the outputs of the circuit are inhibited if Vcc is less than 7.5V
typically.
In the same manner, VDD is monitored and internal set-up is made until V DD reaches 4V (see I2C control table for
power on reset).
In order to have a very good power supply rejection, the circuit is internally supplied by several internal voltage
references (the typical value is 8V). Two of these voltage references are externally accessible, one for the vertical
part and one for the horizontal part. If needed, these voltage references can be used (until Iload is less than 5mA).
Furthermore it is necessary to filter the voltage references by the use of external capacitor connected to ground, in
order to minimize the noise and consequently the “jitter” on vertical and horizontal output signals.
I2C Control
S1D2512X01 belongs to the I2C controlled device family, instead of being controlled by DC voltage on dedicated
control pins, each adjustment can be realized through the I2C interface. The I2C bus is a serial bus with a clock and
a data input. The general function and the bus protocol are specified in the Phillips-bus data sheets.
The interface (data and clock) is TTL-level compatible. The internal threshold levels of the input comparator are
2.2V on rising edge and 0.8V on falling edge (when VDD is 5V). Spikes of up to 50ns are filtered by an integrator
and maximum clock speed is limited to 400kHz.
The data line (SDA) can be used in a bidirectional way that means in read-mode the IC clocks out a reply
information (1byte) to the micro-processor.
The bus protocol prescribes always a full-byte transmission. The first byte after the start condition is used to
transmit the IC-address (hexa 8C for write, 8D for read).
Write Mode
In write mode the second byte sent contains the sub address of the selected function to adjust (or controls to affect)
and the third byte the corresponding data byte. It is possible to send more than one data byte to the IC. If after the
third byte no stop or start condition is detected, the circuit increments automatically the momentary sub address in
the sub address counter by one (auto-increment mode). So it is possible to transmit immediately the next data
bytes without sending the IC address or sub address. It can be useful so as to reinitialize the whole controls very
quickly (flash manner). This procedure can be finished by a stop condition.
The circuit has 16 adjustment capabilities: 3 for horizontal part, 4 for vertical one, 2 for E/W correction, 2 for the
dynamic horizontal phase control, 1 for moire option, 3 for horizontal and vertical dynamic focus and 1 for B+
reference adjustment.
17 bits are also dedicated to several controls (on/off, horizontal forced frequency, sync priority, detection refresh
and XRAY reset).
22
S1D2512X01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
Read Mode
During read mode the second byte transmits the reply information.
The reply byte contains horizontal and vertical lock/unlock status, the XRAY activated or not, the horizontal and
vertical polarity detection. It also contains the Synchro detection status which is used by the MCU to assign sync
priority.
A stop condition always stops all the activities of the bus decoder and switches to high impedance both the data
and the clock line (SDA and SCL) .
See I2C sub address and control tables.
Sync processor
The internal sync processor allows the S1D2512X01 to accept any kind of input Synchro signals:
•
Separated horizontal & vertical TTL-compatible sync signals,
•
Composite horizontal & vertical TTL-compatible sync signals.
Sync identification Status
The MCU can read (address read mode: 8D) the status register via the I2C bus, and then select the sync priority
depending on this status.
Among other data this register indicates the presence of sync pulses on H/HVIN, VSYNCIN and (when 12V is
supplied) whether a Vext has been extracted from H/HVIN. Both horizontal and vertical sync are detected even if
only 5V is supplied.
In order to choose the right sync priority the MCU may proceed as follows (see I2C address Table):
•
Refresh the status register,
•
Wait at least for 20ms(max. vertical period),
•
Read this status register,
Sync priority choice should be:
Vext Det
H/V Det
V Det
Sync Priority Subaddress 03 (D8)
Comment Sync Type
No
Yes
Yes
1
Separated H & V
Yes
Yes
No
0
Composite TTL H & V
Of course, when choice is made, one can refresh the sync detections and verify that extracted Vsync is present
and that no sync change occurred.
The Sync processor is also giving sync polarity information.
IC status
The IC can inform the MCU about the 1st horizontal PLL and vertical section status(locked or not), and about the
XARY protection (activated or not). Resetting the XRAY internal latch can be done either by decreasing the Vcc or
VDD supply or directly resetting it via the I2C interface.
23
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2512X01
Sync Inputs
Both H/HVin and Vsyncin inputs are TTL compatible trigger with Hysteresis to avoid erratic detection.
Both inputs include a pull up register connected to VDD.
Sync Processor Output
The sync processor indicates on the HLOCKOUT Pin whether 1st PLL is locked to an incoming horizontal sync.
HLOCKOUT is a TTL compatible CMOS output. Its level goes to high when locked. In the same time the D8 bit of
the status register is set to 0. This information is mainly used to trigger safety procedures (like reducing B+ value)
as soon as a change is detected on the incoming sync. Further to this, it may be used in an automatic procedure
for free running frequency(fo) adjustment.
Sending the desired fo on the sync input and progressively decreasing the free running frequent I2C register value
(address 02), the HLOCKOUT Pin will go high as soon as the proper setting is reached. Setting the free running
frequency this way allows to fully exploit the S1D2512X01 horizontal frequency range.
HORIZONTAL PART
Internal input conditions
Horizontal part is internally fed by Synchro processor with a digital signal corresponding to horizontal Synchro
pulses or to TTL composite input.
concerning the duty cycle of the input signal, the following signals (positive or negative) may be applied to the
circuit.
Using internal integration, both signals are recognized on condition that Z/T < 25%, Synchronization occurs on the
leading edge of the internal sync signal. The minimum value of Z is 0.7µs.
Z
T
Z
An other integration is able to extract vertical pulse of composite Synchro if duty cycle is more than 25% (typically
d = 35%) (see 7)
c
TRAMEXT
d
d
The last feature performed is the equalizing pulses removing to avoid parasitic pulse on phase comparator input
which is intolerant to wrong or missing pulse.
24
S1D2512X01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
PLL1
The PLL1 is composed of a phase comparator, an external filter and a voltage control oscillator (VCO).
The phase comparator is a phase frequency type designed in CMOS technology. This kind of phase detector
avoids locking on wrong frequencies. It is followed by a charge pump, composed of two current sources sunk and
sourced (I = 1mA typ. when locked, I = 140µA when unlocked). This difference between lock/unlock permits a
smooth catching of horizontal frequency by PLL1. This effect is reinforced by an internal original slow down system
when PLL1 is locked avoiding horizontal too fast frequency change.
The dynamic behavior of the PLL is fixed by an external filter which integrates the current of the charge pump.
A CRC filter is generally used (see Figure 4)
PLL1F
7
1.8KΩ
4.7uF
1uF
Figure 4. PLL1
PLL1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing pulses or wrong
pulse on phase comparator. The inhibition results from the opening of a switch located between the charge pump
and the filter (see Figure 5).
The VCO uses an external RC network. It delivers a linear sawtooth obtained by charge and discharge of the
capacitor, by a current proportional to the current in the resistor. Typical thresholds of sawtooth are 1.6V and 6.4V.
Lock/Unlock
Status
H-LOCKOUT
3
Lockdet
HSYNC 1
Input
Interface
High
Charge
PUMP
Comp1
E2
Low
Tramext
Phase
Adjust
Figure 5. Block Diagram
25
PLL1F R0
7
I2C
Forced
Frequency
Tramext
PLL
Inhibition
6
C0
5
VCO
I2C
Hpos
Adj.
OSC
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
I2C Free running
Adjustment
Loop
Filter 7
a
+
-
(1.3V < V7 < 6V)
IO
2
6.4V
ID
(0.80<a<1.30)
S1D2512X01
1.6V
+
-
RS
Flip
Flop
+
-
4 IO
6
6.4V
5
R0
Co
1.6V
0
TH
0.875TH
Figure 6. Details of VCO
The control voltage of the VCO is typically comprised between 1.33V and 6V (see figure 6). The theoretical
frequency range of this VCO is in the ratio 1 to 4.5, the effective frequency range has to be smaller 1 to 4.2 due to
clamp intervention on filter lowest value. To avoid spread of external components and the circuit itself, it is possible
to adjust free running frequency through I2C. This adjustment can be made automatically on the manufacturing line
without manual operation by using lock/unlock information. The adjustment range is 0.8 to 1.3 F0 (where 1.3 F0 is
the free running frequency at power on reset).
The sync frequency has to be always higher than the free running frequency. As an example for a Synchro range
from 24kHz to 100kHz, the suggested free running frequency is 23kHz.
Another feature is the capability for MCU to force horizontal frequency through I2C to 2xF0 or 3xF0 (for burn in
mode or safety requirement). In this case, inhibition switch is opened leaving PLL1 free but voltage on PLL1 filter is
forced to 2.66V for 2xF0 or 4.0V for 3xF0.
The PLL1 ensures the coincidence between the leading edge of the Synchro signal and a phase reference
obtained by comparison between the sawtooth of the VCO and an internal DC voltage I2C adjustable between
2.8V and 4.0V (corresponding to ±10%) (see Figure 7)
H osc
Sawtooth
7/8TH
1/8TH
6.4V
2.8V < Vb < 4.0V
Vb
1.6V
Phase REF1
Phase REF1 is obtained by comparison between the sawtooth and a DC
voltage adjustable between 2.8V and
4.0V. The PLL1 ensures the exact
coincidence between the signals
phase REF and Hsyns. A ±TH/10
phase adjustment is possible
H Synchro
Figure 7. PLL1 Timing Diagram
26
S1D2512X01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
The S1D2512X01 also includes a lock/unlock identification block which senses in real time whether PLL1 is locked
or not on the incoming horizontal sync signal. The resulting information is available on Hlockout (see sync
processor). The block function is described in figure 5.
When PLL1 is unlocked, It forces Hlockout to leave high.
The lock/unlock information is also available through I2C read.
PLL2
The PLL2 ensures a constant position of the shaped Flyback signal in comparison with the sawtooth of the VCO
(Figure 8). The phase comparator of PLL2 (phase type comparator) is followed by a charge pump (typical output
current:0.5mA). The Flyback input is composed of an NPN transistor. This input must be current driven. The
maximum recommended input current is 5mA (see Figure 9).
The duty cycle is adjustable through I2C from 30% to 60%. For start up safe operation, initial duty cycle (after
power on reset) is 60% in order to avoid having a too long conduction period of the horizontal scanning transistor.
The maximum storage time (Ts max.) is (0.44TH-TFLY/2). Typically, TFLY/TH is around 20% which means that Ts
max is around 34% of TH.
H osc
Sawtooth
1/8TH
7/8TH
6.4V
4.0V
1.6V
Flyback
Internally
Shaped Flyback
H drive
Ts
Duty Cycle
Figure 8. PLL2 Timing Diagram
400Ω
HFLY 12
Q1
20KΩ
GND 0V
Figure 9. Flyback Input Electrical Diagram
27
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2512X01
Output Section
The H-drive signal is sent to the output through a shaping stage which also controls the H-drive duty cycle (I2C
adjustable). In order to secure scanning power part operation, the output is inhibited in the following circumstances:
•
Vcc and VDD too low
•
XRAY protection activated
•
During horizontal Flyback
•
H Drive I2C bit control is off.
The output stage is composed of a NPN bipolar transistor. Only the collector is accessible (see Figure 10).
26 H-DRIVE
Figure 10. Output Section
The output stage is intended for reverse base control, where setting the output NPN in off-state will control the
power scanning transistor in off-state.
The maximum output current is 30mA, and the corresponding voltage drop of the output VCEsat is 0.4V Max.
It is evident that the power scanning transistor cannot be directly driven by the integrated circuit. An interface has
to be designed between the circuit and the power transistor which can be of bipolar or MOS type.
X-RAY Protection
The activation of the X-ray protection is obtained by application of a high level on the X-ray input (8V on pin 25). It
inhibits the H-drive and B+ outputs.
This protection is latched; It may be reset either by Vcc or VDD switch off or by I2C (see Figure 11).
Vertical Dynamic Focus
The S1D2512X01 delivers a vertical parabola wave from on pin 10. Vertical dynamic focus is tracked with VPOS
and VAMP. Its amplitude can be adjusted. It is also affected by S and C corrections. This positive signal once
amplified has to be connected to the CRT focusing grids.
28
S1D2512X01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
I2C Drive on/off
VCC Checking
VCC
+
VSCinh
Horizontal
Output
Inhibition
VDD Checking
VDD
+
VSDinh
XRAY Protection
XRAY
S
Q
2
VCC or VDD off or I C Reset
R
I2C Ramp on/off
Vertical
Output
Inhibition
+
Horizontal Flyback
0.7V
Bout
Figure 11. Safety Functions Block Diagram
VERTICAL PART
Geometric Corrections
The principle is represented in Figure 12.
V.Focus amp
2
VDCMID (3.5V)
I
10
Dynamic Focus
23
Vertical Ramp VOUT
EW + amp
2
Parabola
Generator
+
VDCMID
(3.5V)
+
Corner
24
EW Output
Keystone
VDCMID
(3.5V)
Side pin amp
+
To Horizontal
Phase
Parallelogram
Figure 12. Geometric Corrections Principle
29
Side pin Balance
Output Current
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2512X01
Starting from the vertical ramp, a parabola shaped current is generated for E/W correction, dynamic horizontal
phase control correction, and vertical dynamic focus correction.
The base of the parabola generator is an analog multiplier, the output current of which is equal to:
∆I = k × (VOUT - VDCMID)2
Where Vout is the vertical output ramp (typically between 2 and 5V) and VDCMID is 3.5V (for V REF-V = 8V). One
more multiplier provides a current proportional to (Vout - VDCMID)4 for corner correction The VOUT sawtooth is
typically centered on 3.5V. By changing the vertical position, the sawtooth shifts by ±0.3V.
In order to keep a good screen geometry for any end user preference adjustment we implemented the geometry
tracking.
Due to large output stages voltage range (E/W, keystone, corner), the combination of tracking function with
maximum vertical amplitude, max or min vertical position and maximum gain on the DAC control may lead to the
output stages saturation. This must be avoided by limiting the output voltage by appropriate I2C registers values.
For E/W part and dynamic horizontal phase control part, a sawtooth shaped differential current in the following
form is generated:
∆I’ = k’ × (V OUT - VDCMID)2
Then ∆I and ∆I’are added together and converted into voltage for the E/W part.
Each of the three E/W components, and the two dynamic horizontal phase control ones may be inhibited by their
own I2C select bit.
The E/W parabola is available on pin 24 via an emitter follower which has to be biased by an external resistor
(10KΩ). Since stable in temperature, the device can be DC coupled with an external circuitry.
The vertical dynamic focus is available on output pin 10. Dynamic horizontal phase control current drives internally
the H-position, moving the Hfly position on the horizontal sawtooth in the ± 1.4% TH both on side pin balance and
parallelogram.
EW
EWOUT = 2.5V + K1 (VOUT - VDCMID) + K2 (VOUT - VDCMID)2 + K3 (Vout - VDCMID)4
K1 is adjustable by the keystone I2C register
K2 is adjustable by the EW amplitude I2C register
K3 is adjustable by the corner I2C register
Dynamic Horizontal Phase Control
IOUT = K4 (VOUT - VDCMID) 2 + K5 (VOUT - VDCMID)
K4 is adjustable by side pin balance I2C register
K5 is adjustable by parallelogram I2C register.
Function
When the Synchronization pulse is not present, an internal current source sets the free running frequency. For an
external capacitor, COSC = 150nF, the typical free running frequency is 100Hz.
Typical free running frequency can be calculated by:
fo ( Hz ) = 1.5 ⋅ 10
–5
1
⋅ -------------C OSC
30
S1D2512X01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
A negative or positive TTL level pulse applied on pin 2 (VSYNC) as well as a TTL composite sync on pin 1 can
Synchronize the ramp in the range [fmin, fmax]. This frequency range depends on the external capacitor
connected on pin 22. A capacitor in the range [150nF, ± 5%] is recommended for application in the following range:
50Hz to 185Hz.
Typical maximum and minimum frequency, at 25°C and without any correction (S correction or C correction), can
be calculated by:
f(Max.) = 3.5 × fo and f(Min.) = 0.33 × fo
If S or C corrections are applied, these values are slightly affected.
If a Synchronization pulse is applied, the internal oscillator is synchronized immediately but the amplitude changes.
An internal correction is activated to adjust it in less than a half a second: the highest voltage of the ramp pin 22 is
sampled on the sampling capacitor connected on pin 20 at each clock pulse and a transconductance amplifier
generates the charge current of the capacitor. The ramp amplitude becomes again constant.
The read status register enables to have the vertical lock-unlock and the vertical sync polarity informations.
It is recommended to use a AGC capacitor with low leakage current. A value lower than 100nA is mandatory.
A good stability of the internal closed loop is reached by a 470nF ± 5% capacitor value on pin 20 (VAGC)
TRANSCONDUCTANCE
AMPLIFIER
CHARGE CURRENT
REF
22
DISCH.
2
V-SYNC
SYNCHRO
+
SAMPLING 20
VS_AMP
SUB07/6bits
COR-C
SUB08/6bits
OSCILLATOR
POLARITY
C CORRECTION
+
-
18 BREATH
Vlow
VMOIRE
SUB0C/5BITS
VOSITION
SUB06/7BITS
Figure 13. AGC Loop Block Diagram
31
S CORRECTION
SAMP
CAP
OSC
CAP
Switch
Disch
VERT_AMP
SUB05/7BITS
+
23 VOUT
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2512X01
I2C Control Adjustments
Then, S and C correction shapes can be added to this ramp. This frequency independent S and C corrections are
generated internally. Their amplitude are adjustable by their respective I2C register. They can also be inhibited by
their select bit. The amplitude of this S and C corrected ramp can be adjusted by the vertical ramp amplitude
control register. The adjusted ramp is available on pin 23 (VOUT) to drive an external power stage. The gain of this
stage is typically 25% depending on its register value. The mean value of this ramp is driven by its own I2C register
(vertical position). Its value is VPOS = 7/16 • VREF ± 300mV.
Usually VOUT is sent through a resistive divider to the inverting input of the booster. Since VPOS derives from
VREF-V, the bias voltage sent to the non-inverting input of booster should also derive from VREF-V to optimize the
accuracy (see application diagram).
Basic Equations
In first approximation, the amplitude of the ramp on pin 23 (Vout) is:
VOUT - VPOS = (VOSC - VDCMID) • (1 + 0.25 (VAMP) )
with:
• VDCMID = 7/16•VREF (typically 3.5V, the middle value of the ramp on pin 22)
•
VOSC = V22 (ramp with fixed amplitude)
•
VAMP = - 1 for minimum vertical amplitude register value and +1 for maximum
•
VPOS is calculated by: VPOS = VDCMID + 0.3Vp with Vp equals -1 for minimum vertical position register value
and +1 for maximum
The current available on pin 22 is:
IOSC =
3
8
• VREF • C OSC • f
with COSC: capacitor connected on pin 22
f: synchronization frequency.
Vertical Moire
By using the vertical moire, VPOS can be modulated from frame to frame. This function is intended to cancel the
fringes which appear when line to line interval is very close to the CRT vertical pitch. The amplitude of the
modulation is controlled by register VMOIRE on address OC and can be switched - off via the control bit D7.
32
S1D2512X01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
DC/DC CONVERTER PART
This unit controls the switch-mode DC/DC converter. It converts a DC constant voltage into the B+ voltage(roughly
proportional to the horizontal frequency) necessary for the horizontal scanning. This DC/DC converter must be
configured in step-up mode. It operates very similarly to the well known UC3842.
Step-up Mode
Operating description
•
The power MOS is switched-on at the middle of the horizontal Flyback.
•
The power MOS is switched-off when its current reaches predetermined value. For this purpose, a sense
resistor is inserted in its source. The voltage on this resistor is sent to pin16 (ISENSE).
•
The feedback (coming either from the EHV or from the Flyback) is divided to a voltage close to 4.8V and compared to the internal 4.8V reference (IVREF). The difference is amplified by an error amplifier, the output of
which controls the power MOS switch-off current.
Main Features
•
Switching synchronized on the horizontal frequency
•
B+ voltage always higher than the DC source
•
Current limited on a pulse-by-pulse basis
•
The DC/DC converter is disabled:
- When VCC or VDD are too low,
- When X-Ray protection is latched,
- Directly through I2C bus.
•
When disabled, BOUT is driven to GND by a 0.5mA current source. This feature allows to implement externally
a soft start circuit.
33
8V
±Iadjust
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
DAC
7bits
S1D2512X01
400ns
I2C
12V
4.8V ± 20%
+
95dB
A
-
+
s
1/3
-
Soft
start
1.2V
1.2V
Inhibit SMPS
REGIN
15
COMP
14
C2
+
BOUT
S
Q
28
R
C3
+
Inhibit SMPS
ISENSE
16
1MΩ
+
22KΩ
L
V
B+
Figure 14. DC/DC Converter Part
34
S1D2512X01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
APPLICATION BOARD CIRCUIT
VCC=12V
5V
HSYNC
1K
1
HSYNC_IN
32
5V
+
100uF
0.1uF
VSYNC
1K
2
3
22nF 100V 4
2
VSYNC_IN
SDA
H_LOCKOUT
SCL
PLL2C
31
30
6.8K
6
4.7uF 50V 1.8K
7
CO
B+OUT
RO
GND
100
SCL
29
VCC
+
100uF
1% P
820pF 50V 5
SDA
100
0.1uF
10K
28
27
1K
+
PLL1F
26
H_OUT
HOUT
10nF 100V MP
1uF
22K
8
H_LOCKCAP
H-POSITION
25
XRAY
50K
S1D2512X
KB2512
2K
10K
9
10
11
H MOIRE
EWOUT
FOCUS
VOUT
HGND
VSCAP
24
10K
23
10K
22
150nF 100V
1% P
AFC
12
HFLY
21
V_REF
AFC
4.7uF
13
+
H_REF
VAGCCAP
COMP
VGND
REGIN
HBLKOUT
BREATH
+47uF
50V 0.1uF
20 470nF 63V P
0.1uF
14
10K
19
1K
1M
22K
50K
15
50K
18
33K
1K
22K
16
50K
I_SENSE
17
B+GND
3.3K
12V
1
SCLK
74HCT125
2
SDAT
1
47pF
5V
14
3
ACK
2
100K
13
4
3
12
4
11
HOUT
1
16
2
15 47pF
3
14
4
5
5
6
7
13
MC14528
12
10
+
0.1uF 100uF
9
8
SCL
6
11
7
10
10K
8
9
33pF
SDA
Figure 15. Application Circuit
35
100K
AFC