SAMSUNG KAB01D100M

SEC Only
MCP MEMORY
KAB0xD100M - TxGP
Document Title
Multi-Chip Package MEMORY
64M Bit (8Mx8/4Mx16) Dual Bank NOR Flash / 128M Bit (8Mx16) NAND Flash / 32M Bit (2Mx16) UtRAM
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial Draft
March 20, 2002
Preliminary
0.1
Inserted No ECC condition in NAND Flash
• Endurance (1page)
: 1,000 Program/Erase Cycles Maximum without ECC
• Program Flow (39page)
: Excluded "Read Verify" step after programming in this condition
March 28, 2002
Preliminary
0.2
<Common>
Revised TBIAS(43page)
• from "-25 to 85" to "-40 to 125"
Revised VIL(43page)
• from max. 0.6V to max. 0.5V
Revised VOH(43page)
• from min. 2.4V to min. 2.3V
Revised IOL(43page)
• from 0.1mA to max. 2.1mA
Revised IOH(43page)
• from -0.1mA to max. -1.0mA
March 28, 2002
Preliminary
0.3
<NAND>
Revised the internal voltage that disables all functions(37page)
• from 2V to 1.3V
Revised power-up and power-down recovery time(37page)
• from min. 1µs to min. 10µs
Revised write cycle time(tWC)(59page)
• from 50ns to min. 45ns
Combined ALE to RE Delay in ID read and in Read cycle(59page)
• from min. 20ns and 50ns to min. 10ns
Revised RE Access Time(tREA)(59page)
• from max. 35ns to max. 30ns
Excluded min. value of RE High to Output Hi-Z(tREH)(59page)
Inserted RE or CEF High to Output Hold(tOH) with min. 15ns(59page)
Revised timing diagram
June 17, 2002
Final
1.0
Finalize
October 15, 2002
Final
1.1
Revised <NOR>
- Release the stand-by current from typ. 5uA(max. 18uA) to typ.
10uA(max. 30uA).
June 18, 2003
Final
1.11
Revised <NAND>
- Corrected Some typos in the timing diagram
August 14, 2003
Final
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s web site.
http://samsungelectronics.com/semiconductors/products/products_index.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
-1-
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
Multi-Chip Package MEMORY
64M Bit (8Mx8/4Mx16) Dual Bank NOR Flash / 128M Bit (8Mx16) NAND Flash / 32M Bit (2Mx16) UtRAM
FEATURES
• Power Supply Voltage : 2.7V~3.1V
• Organization
- NOR Flash : 8,388,608 x 8 bit / 4,194,304 x 16 bit
- NAND Flash : (8M + 256K)bit x 16bit
- UtRAM : 2Mbit x 16 bit
• Access Time
- NOR Flash : 70ns(Max.)
- NAND Flash : Random : 10us(Max.), Serial : 50ns(Min.)
- UtRAM : 85ns
• Power Consumption (typical value)
- NOR Flash Read Current : 14mA (@5MHz)
Program/Erase Current : 15mA
Read while Program or Read while Erase : 35mA
Standby Mode/Autosleep Mode : 10µA
- NAND Flash Read Current : 10mA(@20MHz)
Program/Erase Current : 10mA
Standby Current : 10µA
- UtRAM Operating Current : 30mA
Standby Current : 80µA
• NOR Flash Secode(Security Code) Block : Extra 64KB Block
• NOR Flash Block Group Protection / Unprotection
• NOR Flash Bank Size : 16Mb / 48Mb , 32Mb / 32Mb
• NAND Flash Automatic Program and Erase
Page Program: (256 + 8)Word, Block Erase: (8K + 256)Word
• NAND Flash Fast Write Cycle Time
Program time : 200µs(Typ.)
Block Erase Time : 2ms(Typ.)
• Endurance
NOR : 100,000 Program/Erase Cycles Minimum
NAND : 100,000 Program/Erase Cycles Minimum with ECC
: 1,000 Program/Erase Cycles Maximum without ECC
• Data Retention : 10 years
• Operating Temperature : -25°C ~ 85°C
• Package : 80 - Ball TBGA Type - 8 x 12mm, 0.8 mm pitch
GENERAL DESCRIPTION
The KAB0xD100M featuring single 3.0V power supply is a Multi
Chip Package Memory which combines 64Mbit NOR Flash,
128Mbit NAND Flash and 32Mbit Unit Transistor CMOS RAM.
64Mbit NOR Flash memory is organized as 8M x8 or 4M x16 bit,
128Mbit NAND Flash memory is organized as 8M x16 bit and
32Mbit UtRAM is organized as 2M x16 bit. The memory architecture of NOR Flash memory is designed to divide its memory arrays
into 135 blocks and this provides highly flexible erase and program
capability. This device is capable of reading data from one bank
while programming or erasing in the other bank with dual bank
organization. NOR Flash memory performs a program operation in
units of 8 bits (Byte) or 16 bits (Word) and erases in units of a
block. Single or multiple blocks can be erased. The block erase
operation is completed for typically 0.7sec.
In 128Mbit NAND Flash a 256-word page program can be typically
achieved within 200µs and an 8K-word block erase can be typically achieved within 2ms. In serial read operation, a byte can be
read by 50ns. DQ pins serve as the ports for address and data
input/output as well as command inputs. The KAB0xD100M is
suitable for the memory of mobile communication system to
reduce not only mount area but also power consumption. This
device is available in 80-ball TBGA package.
BALL DESCRIPTION
Ball Name
A0 to A20
A-1, A21
BALL CONFIGURATION
1
2
3
4
5
6
7
Address Input Balls (NOR)
DQ0 to DQ7
Data Input/Output Balls (Common)
DQ8 to DQ15
Data Input/Output Balls (Common)
VccR
Power Supply (NOR)
VccF
Power Supply (NAND)
VccU
Power Supply (UtRAM)
VccQU
8
Description
Address Input Balls (NOR, UtRAM)
Data Output Buffer Power (UtRAM)
Vss
Ground (Common)
A
DNU
DNU
WE
Write Enable (Common)
B
DNU
DNU
OE
Output Enable (NOR,UtRAM)
CER
Chip Enable (NOR)
CEF
Chip Enable (NAND)
CSU
Chip Enable (UtRAM)
C
A6
R/BR
CLE
N.C
R/BF
A12
D
A5
A18
ALE
WE
A9
A13
E
A4
A17
Vss
A20
A10
A14
F
A3
LB
UB
A19
A11
A15
G
A1
CEF
ZZ
A21
A8
N.C
VccF
RESET
N.C
VccU
WP/
ACC
N.C
RE
A7
A2
WP
H
A0
CSU
J
OE
DQ2 DQ11 VccQU
CER
N.C
N.C
N.C
Vss
DQ12
BYTE
A16
DQ5 DQ14
DQ8
DQ9
N.C
VccU
N.C
DQ13
DQ7
L
DQ0
DQ1 DQ10 VccR
VccF
DQ4
DQ6
DQ15
/A-1
M
N
DNU
DNU
WP/ACC
BYTE
K
DQ3
RESET
DNU
DNU
80 Ball TBGA , 0.8mm Pitch
Top View (Ball Down)
Hardware Reset (NOR)
Hardware Write Protection/Program
Acceleration (NOR)
Byte Control (NOR)
R/BR
Read/Busy (NOR)
WP
Write Protection (NAND)
CLE
Command Latch Enable(NAND)
ALE
Address Latch Enable(NAND)
R/BF
Read/Busy (NAND)
RE
Output Enable (NAND)
ZZ
Deep Power Down (UtRAM)
UB
Upper Byte Enable (UtRAM)
LB
Lower Byte Enable (UtRAM)
N.C
No Connection
DNU
Do Not Use
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
-2-
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
ORDERING INFORMATION
K A B 0x D 1 0 0 M - T LGP
Samsung MCP Memory
(3Chip MCP)
Access Time
LGP : NOR(70ns) NAND(50ns), UtRAM(85ns)
NGP : NOR(80ns) NAND(50ns), UtRAM(85ns)
Device Type
B : Dual Bank NOR + NAND + UtRAM
Package
NOR Flash Density, Vcc, & Org.
: 64M, Vcc=3.0V, & Org.=x8/x16
: Bank Size(Boot Block)
T = 80 TBGA
Version
01 : 16M/48M(Bottom), 02 : 16M/48M(Top)
03 : 32M/32M(Bottom), 04 : 32M/32M(Top)
M = 1st Generation
NAND Flash Density (Vcc, Org.)
DRAM I/F, Density (Vcc, Org.)
D : 128M (3.0V, x16)
0 : NONE
UtRAM Density (Vcc, Org.)
SRAM Density (Vcc, Org.)
1 : 32M (3.0V, x16)
0 : NONE
Figure 1. FUNCTIONAL BLOCK DIAGRAM
VccR
Vss
Bank1
Address
RESET
X
Dec
A-1, A21
BYTE
Bank1 Data-In/Out
I/O
Interface
&
Bank
Control
Latch &
Control
Y Dec
X
Dec
Bank2
Address
Bank2
Cell Array
Erase
Control
OE
High
Voltage
Gen.
Program
Control
WE
Y-Gating
2nd half page Register & S/A
X-Buffers
Latches
& Decoders
RE
DQ0 to DQ15
Bank2 Data-In/Out
CER
ALE
Latch &
Control
Y Dec
R/BR
A0 to A20
Bank1
Cell Array
128M+4M Bit
NAND Flash
ARRAY
Y-Buffers
Latches
& Decoders
CLE
(256 + 8)Word x 32768
WP
1st half page Register & S/A
Y-Gating
CEF
VccF
Command
Register
Vss
Control Logic
& High Voltage
Generator
R/BF
DQ0 to DQ15
DQ0 to DQ15
I/O Buffers & Latches
Clk gen.
Precharge circuit.
ZZ
UtRAM
Main Cell Array
Row
select
UB
Output
Driver
Global Buffers
DQ0 to DQ15
(2Mb x16)
LB
CSU
VccU
VccQU
Vss
Control
logic
Data
control
I/O Circuit
Column select
Bottom Boot Block
-3-
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
Figure 2. NAND Flash ARRAY ORGANIZATION
1 Block =32 Pages
= (8K + 256) Words
32K Pages
(=1024 Blocks)
1 Page = 264 Words
1 Block = 264 Words x 32 Pages
= (8K + 256) Words
1 Device = 264 Words x 32Pages x 1024Blocks
= 132 Mbits
Page Register
(=256 Bytes)
16 bit
256 Words
8 Words
DQ 0 ~ DQ 15
Page Register
256 Words
DQ 0
DQ 1
DQ 2
DQ 3
8 Words
DQ 4
DQ 5
DQ 6
DQ 7
DQ8 to 15
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
*L
Column Address
2nd Cycle
A9
A10
A11
A12
A13
A14
A15
A16
*L
Row Address
3rd Cycle
A17
A18
A19
A20
A21
A22
A23
*L
*L
(Page Address)
NOTE: Column Address : Starting Address of the Register.
* L must be set to "Low"
-4-
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
Table 1. NOR Flash Memory Top Boot Block Address (KAB02D100/KAB04D100)
KAB
02D1
00
Bank1
KAB
04D1
00
Block Address
Address Range
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Block Size
(KB/KW)
BA134
1
1
1
1
1
1
1
1
1
1
8/4
7FE000H-7FFFFFH
3FF000H-3FFFFFH
BA133
1
1
1
1
1
1
1
1
1
0
8/4
7FC000H-7FDFFFH
3FE000H-3FEFFFH
BA132
1
1
1
1
1
1
1
1
0
1
8/4
7FA000H-7FBFFFH
3FD000H-3FDFFFH
BA131
1
1
1
1
1
1
1
1
0
0
8/4
7F8000H-7F9FFFH
3FC000H-3FCFFFH
Block
Byte Mode
Word Mode
BA130
1
1
1
1
1
1
1
0
1
1
8/4
7F6000H-7F7FFFH
3FB000H-3FBFFFH
BA129
1
1
1
1
1
1
1
0
1
0
8/4
7F4000H-7F5FFFH
3FA000H-3FAFFFH
BA128
1
1
1
1
1
1
1
0
0
1
8/4
7F2000H-7F3FFFH
3F9000H-3F9FFFH
BA127
1
1
1
1
1
1
1
0
0
0
8/4
7F0000H-7F1FFFH
3F8000H-3F8FFFH
BA126
1
1
1
1
1
1
0
X
X
X
64/32
7E0000H-7EFFFFH
3F0000H-3F7FFFH
BA125
1
1
1
1
1
0
1
X
X
X
64/32
7D0000H-7DFFFFH
3E8000H-3EFFFFH
BA124
1
1
1
1
1
0
0
X
X
X
64/32
7C0000H-7CFFFFH
3E0000H-3E7FFFH
BA123
1
1
1
1
0
1
1
X
X
X
64/32
7B0000H-7BFFFFH
3D8000H-3DFFFFH
BA122
1
1
1
1
0
1
0
X
X
X
64/32
7A0000H-7AFFFFH
3D0000H-3D7FFFH
BA121
1
1
1
1
0
0
1
X
X
X
64/32
790000H-79FFFFH
3C8000H-3CFFFFH
BA120
1
1
1
1
0
0
0
X
X
X
64/32
780000H-78FFFFH
3C0000H-3C7FFFH
BA119
1
1
1
0
1
1
1
X
X
X
64/32
770000H-77FFFFH
3B8000H-3BFFFFH
BA118
1
1
1
0
1
1
0
X
X
X
64/32
760000H-76FFFFH
3B0000H-3B7FFFH
BA117
1
1
1
0
1
0
1
X
X
X
64/32
750000H-75FFFFH
3A8000H-3AFFFFH
BA116
1
1
1
0
1
0
0
X
X
X
64/32
740000H-74FFFFH
3A0000H-3A7FFFH
BA115
1
1
1
0
0
1
1
X
X
X
64/32
730000H-73FFFFH
398000H-39FFFFH
Bank1
BA114
1
1
1
0
0
1
0
X
X
X
64/32
720000H-72FFFFH
390000H-397FFFH
BA113
1
1
1
0
0
0
1
X
X
X
64/32
710000H-71FFFFH
388000H-38FFFFH
BA112
1
1
1
0
0
0
0
X
X
X
64/32
700000H-70FFFFH
380000H-387FFFH
BA111
1
1
0
1
1
1
1
X
X
X
64/32
6F0000H-6FFFFFH
378000H-37FFFFH
BA110
1
1
0
1
1
1
0
X
X
X
64/32
6E0000H-6EFFFFH
370000H-377FFFH
BA109
1
1
0
1
1
0
1
X
X
X
64/32
6D0000H-6DFFFFH
368000H-36FFFFH
BA108
1
1
0
1
1
0
0
X
X
X
64/32
6C0000H-6CFFFFH
360000H-367FFFH
BA107
1
1
0
1
0
1
1
X
X
X
64/32
6B0000H-6BFFFFH
358000H-35FFFFH
BA106
1
1
0
1
0
1
0
X
X
X
64/32
6A0000H-6AFFFFH
350000H-357FFFH
BA105
1
1
0
1
0
0
1
X
X
X
64/32
690000H-69FFFFH
348000H-34FFFFH
BA104
1
1
0
1
0
0
0
X
X
X
64/32
680000H-68FFFFH
340000H-347FFFH
BA103
1
1
0
0
1
1
1
X
X
X
64/32
670000H-67FFFFH
338000H-33FFFFH
BA102
1
1
0
0
1
1
0
X
X
X
64/32
660000H-66FFFFH
330000H-337FFFH
BA101
1
1
0
0
1
0
1
X
X
X
64/32
650000H-65FFFFH
328000H-32FFFFH
BA100
1
1
0
0
1
0
0
X
X
X
64/32
640000H-64FFFFH
320000H-327FFFH
BA99
1
1
0
0
0
1
1
X
X
X
64/32
630000H-63FFFFH
318000H-31FFFFH
-5-
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
Table 1. NOR Flash Memory Top Boot Block Address (KAB02D100/KAB04D100)
KAB
02D1
00
KAB
04D1
00
Bank1
Block Address
Address Range
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Block Size
(KB/KW)
Byte Mode
Word Mode
BA98
1
1
0
0
0
1
0
X
X
X
64/32
620000H-62FFFFH
310000H-317FFFH
BA97
1
1
0
0
0
0
1
X
X
X
64/32
610000H-61FFFFH
308000H-30FFFFH
BA96
1
1
0
0
0
0
0
X
X
X
64/32
600000H-60FFFFH
300000H-307FFFH
BA95
1
0
1
1
1
1
1
X
X
X
64/32
5F0000H-5FFFFFH
2F8000H-2FFFFFH
BA94
1
0
1
1
1
1
0
X
X
X
64/32
5E0000H-5EFFFFH
2F0000H-2F7FFFH
2E8000H-2EFFFFH
Block
BA93
1
0
1
1
1
0
1
X
X
X
64/32
5D0000H-5DFFFFH
BA92
1
0
1
1
1
0
0
X
X
X
64/32
5C0000H-5CFFFFH
2E0000H-2E7FFFH
BA91
1
0
1
1
0
1
1
X
X
X
64/32
5B0000H-5BFFFFH
2D8000H-2DFFFFH
BA90
1
0
1
1
0
1
0
X
X
X
64/32
5A0000H-5AFFFFH
2D0000H-2D7FFFH
BA89
1
0
1
1
0
0
1
X
X
X
64/32
590000H-59FFFFH
2C8000H20CFFFFH
BA88
1
0
1
1
0
0
0
X
X
X
64/32
580000H-58FFFFH
2C0000H-2C7FFFH
BA87
1
0
1
0
1
1
1
X
X
X
64/32
570000H-57FFFFH
2B8000H-2BFFFFH
BA86
1
0
1
0
1
1
0
X
X
X
64/32
560000H-56FFFFH
2B0000H-2B7FFFH
BA85
1
0
1
0
1
0
1
X
X
X
64/32
550000H-55FFFFH
2A8000H-2AFFFFH
BA84
1
0
1
0
1
0
0
X
X
X
64/32
540000H-54FFFFH
2A0000H-2A7FFFH
BA83
1
0
1
0
0
1
1
X
X
X
64/32
530000H-53FFFFH
298000H-29FFFFH
BA82
1
0
1
0
0
1
0
X
X
X
64/32
520000H-52FFFFH
290000H-297FFFH
BA81
1
0
1
0
0
0
1
X
X
X
64/32
510000H-51FFFFH
288000H-28FFFFH
BA80
1
0
1
0
0
0
0
X
X
X
64/32
500000H-50FFFFH
280000H-287FFFH
BA79
1
0
0
1
1
1
1
X
X
X
64/32
4F0000H-4FFFFFH
278000H-27FFFFH
BA78
1
0
0
1
1
1
0
X
X
X
64/32
4E0000H-4EFFFFH
270000H-277FFFH
BA77
1
0
0
1
1
0
1
X
X
X
64/32
4D0000H-4DFFFFH
268000H-26FFFFH
BA76
1
0
0
1
1
0
0
X
X
X
64/32
4C0000H-4CFFFFH
260000H-267FFFH
BA75
1
0
0
1
0
1
1
X
X
X
64/32
4B0000H-4BFFFFH
258000H-25FFFFH
BA74
1
0
0
1
0
1
0
X
X
X
64/32
4A0000H-4AFFFFH
250000H-257FFFH
BA73
1
0
0
1
0
0
1
X
X
X
64/32
490000H-49FFFFH
248000H-24FFFFH
BA72
1
0
0
1
0
0
0
X
X
X
64/32
480000H-48FFFFH
240000H-247FFFH
BA71
1
0
0
0
1
1
1
X
X
X
64/32
470000H-47FFFFH
238000H-23FFFFH
Bank1
Bank2
-6-
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
Table 1. NOR Flash Memory Top Boot Block Address (KAB02D100/KAB04D100)
KAB
02D1
00
KAB
04D1
00
Bank1
Block Address
Address Range
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Block Size
(KB/KW)
Byte Mode
Word Mode
BA70
1
0
0
0
1
1
0
X
X
X
64/32
460000H-46FFFFH
230000H-237FFFH
BA69
1
0
0
0
1
0
1
X
X
X
64/32
450000H-45FFFFH
228000H-22FFFFH
BA68
1
0
0
0
1
0
0
X
X
X
64/32
440000H-44FFFFH
220000H-227FFFH
BA67
1
0
0
0
0
1
1
X
X
X
64/32
430000H-43FFFFH
218000H-21FFFFH
BA66
1
0
0
0
0
1
0
X
X
X
64/32
420000H-42FFFFH
210000H-217FFFH
BA65
1
0
0
0
0
0
1
X
X
X
64/32
410000H-41FFFFH
208000H-20FFFFH
BA64
1
0
0
0
0
0
0
X
X
X
64/32
400000H-3FFFFFH
200000H-207FFFH
BA63
0
1
1
1
1
1
1
X
X
X
64/32
3F0000H-3FFFFFH
1F8000H-1FFFFFH
BA62
0
1
1
1
1
1
0
X
X
X
64/32
3E0000H-3EFFFFH
1F0000H-1F7FFFH
BA61
0
1
1
1
1
0
1
X
X
X
64/32
3D0000H-3DFFFFH
1E8000H-1EFFFFH
BA60
0
1
1
1
1
0
0
X
X
X
64/32
3C0000H-3CFFFFH
1E0000H-1E7FFFH
BA59
0
1
1
1
0
1
1
X
X
X
64/32
3B0000H-3BFFFFH
1D8000H-1DFFFFH
BA58
0
1
1
1
0
1
0
X
X
X
64/32
3A0000H-3AFFFFH
1D0000H-1D7FFFH
BA57
0
1
1
1
0
0
1
X
X
X
64/32
390000H-39FFFFH
1C8000H-1CFFFFH
BA56
0
1
1
1
0
0
0
X
X
X
64/32
380000H-38FFFFH
1C0000H-1C7FFFH
BA55
0
1
1
0
1
1
1
X
X
X
64/32
370000H-37FFFFH
1B8000H-1BFFFFH
BA54
0
1
1
0
1
1
0
X
X
X
64/32
360000H-36FFFFH
1B0000H-1B7FFFH
BA53
0
1
1
0
1
0
1
X
X
X
64/32
350000H-35FFFFH
1A8000H-1AFFFFH
BA52
0
1
1
0
1
0
0
X
X
X
64/32
340000H-34FFFFH
1A0000H-1A7FFFH
BA51
0
1
1
0
0
1
1
X
X
X
64/32
330000H-33FFFFH
198000H-19FFFFH
BA50
0
1
1
0
0
1
0
X
X
X
64/32
320000H-32FFFFH
190000H-197FFFH
BA49
0
1
1
0
0
0
1
X
X
X
64/32
310000H-31FFFFH
188000H-18FFFFH
BA48
0
1
1
0
0
0
0
X
X
X
64/32
300000H-30FFFFH
180000H-187FFFH
BA47
0
1
0
1
1
1
1
X
X
X
64/32
2F0000H-2FFFFFH
178000H-17FFFFH
BA46
0
1
0
1
1
1
0
X
X
X
64/32
2E0000H-2EFFFFH
170000H-177FFFH
BA45
0
1
0
1
1
0
1
X
X
X
64/32
2D0000H-2DFFFFH
168000H-16FFFFH
BA44
0
1
0
1
1
0
0
X
X
X
64/32
2C0000H-2CFFFFH
160000H-167FFFH
BA43
0
1
0
1
0
1
1
X
X
X
64/32
2B0000H-2BFFFFH
158000H-15FFFFH
BA42
0
1
0
1
0
1
0
X
X
X
64/32
2A0000H-2AFFFFH
150000H-157FFFH
BA41
0
1
0
1
0
0
1
X
X
X
64/32
290000H-29FFFFH
148000H-14FFFFH
BA40
0
1
0
1
0
0
0
X
X
X
64/32
280000H-28FFFFH
140000H-147FFFH
BA39
0
1
0
0
1
1
1
X
X
X
64/32
270000H-27FFFFH
138000H-13FFFFH
BA38
0
1
0
0
1
1
0
X
X
X
64/32
260000H-26FFFFH
130000H-137FFFH
BA37
0
1
0
0
1
0
1
X
X
X
64/32
250000H-25FFFFH
128000H-12FFFFH
BA36
0
1
0
0
1
0
0
X
X
X
64/32
240000H-24FFFFH
120000H-127FFFH
BA35
0
1
0
0
0
1
1
X
X
X
64/32
230000H-23FFFFH
118000H-11FFFFH
Block
Bank2
Bank2
-7-
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
Table 1. NOR Flash Memory Top Boot Block Address (KAB02D100/KAB04D100)
KAB
02D1
00
Bank2
KAB
04D1
00
Bank2
Block Address
Address Range
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Block Size
(KB/KW)
Byte Mode
BA34
0
1
0
0
0
1
0
X
X
X
64/32
220000H-22FFFFH
110000H-117FFFH
BA33
0
1
0
0
0
0
1
X
X
X
64/32
210000H-21FFFFH
108000H-10FFFFH
BA32
0
1
0
0
0
0
0
X
X
X
64/32
200000H-20FFFFH
100000H-107FFFH
BA31
0
0
1
1
1
1
1
X
X
X
64/32
1F0000H-1FFFFFH
0F8000H-0FFFFFH
BA30
0
0
1
1
1
1
0
X
X
X
64/32
1E0000H-1EFFFFH
0F0000H-0F7FFFH
BA29
0
0
1
1
1
0
1
X
X
X
64/32
1D0000H-1DFFFFH
0E8000H-0EFFFFH
Block
Word Mode
BA28
0
0
1
1
1
0
0
X
X
X
64/32
1C0000H-1CFFFFH
0E0000H-0E7FFFH
BA27
0
0
1
1
0
1
1
X
X
X
64/32
1B0000H-1BFFFFH
0D8000H-0DFFFFH
BA26
0
0
1
1
0
1
0
X
X
X
64/32
1A0000H-1AFFFFH
0D0000H-0D7FFFH
BA25
0
0
1
1
0
0
1
X
X
X
64/32
190000H-19FFFFH
0C8000H-0CFFFFH
BA24
0
0
1
1
0
0
0
X
X
X
64/32
180000H-18FFFFH
0C0000H-0C7FFFH
BA23
0
0
1
0
1
1
1
X
X
X
64/32
170000H-17FFFFH
0B8000H-0BFFFFH
BA22
0
0
1
0
1
1
0
X
X
X
64/32
160000H-16FFFFH
0B0000H-0B7FFFH
BA21
0
0
1
0
1
0
1
X
X
X
64/32
150000H-15FFFFH
0A8000H-0AFFFFH
BA20
0
0
1
0
1
0
0
X
X
X
64/32
140000H-14FFFFH
0A0000H-0A7FFFH
BA19
0
0
1
0
0
1
1
X
X
X
64/32
130000H-13FFFFH
098000H-09FFFFH
BA18
0
0
1
0
0
1
0
X
X
X
64/32
120000H-12FFFFH
090000H-097FFFH
BA17
0
0
1
0
0
0
1
X
X
X
64/32
110000H-11FFFFH
088000H-08FFFFH
BA16
0
0
1
0
0
0
0
X
X
X
64/32
100000H-10FFFFH
080000H-087FFFH
BA15
0
0
0
1
1
1
1
X
X
X
64/32
0F0000H-0FFFFFH
078000H-07FFFFH
BA14
0
0
0
1
1
1
0
X
X
X
64/32
0E0000H-0EFFFFH
070000H-077FFFH
BA13
0
0
0
1
1
0
1
X
X
X
64/32
0D0000H-0DFFFFH
068000H-06FFFFH
BA12
0
0
0
1
1
0
0
X
X
X
64/32
0C0000H-0CFFFFH
060000H-067FFFH
BA11
0
0
0
1
0
1
1
X
X
X
64/32
0B0000H-0BFFFFH
058000H-05FFFFH
BA10
0
0
0
1
0
1
0
X
X
X
64/32
0A0000H-0AFFFFH
050000H-057FFFH
BA9
0
0
0
1
0
0
1
X
X
X
64/32
090000H-09FFFFH
048000H-04FFFFH
BA8
0
0
0
1
0
0
0
X
X
X
64/32
080000H-08FFFFH
040000H-047FFFH
BA7
0
0
0
0
1
1
1
X
X
X
64/32
070000H-07FFFFH
038000H-03FFFFH
BA6
0
0
0
0
1
1
0
X
X
X
64/32
060000H-06FFFFH
030000H-037FFFH
BA5
0
0
0
0
1
0
1
X
X
X
64/32
050000H-05FFFFH
028000H-02FFFFH
BA4
0
0
0
0
1
0
0
X
X
X
64/32
040000H-04FFFFH
020000H-027FFFH
BA3
0
0
0
0
0
1
1
X
X
X
64/32
030000H-03FFFFH
018000H-01FFFFH
BA2
0
0
0
0
0
1
0
X
X
X
64/32
020000H-02FFFFH
010000H-017FFFH
BA1
0
0
0
0
0
0
1
X
X
X
64/32
010000H-01FFFFH
008000H-00FFFFH
BA0
0
0
0
0
0
0
0
X
X
X
64/32
000000H-00FFFFH
000000H-007FFFH
NOTE: The bank address bits are A21 ∼ A20 for KAB02D100, A21 for KAB04D100.
Table 2. Secode Block Addresses for Top Boot Devices
Device
Block Address
A21-A12
Block
Size
(X8)
Address Range
(X16)
Address Range
KAB02D100/KAB04D100
1111111xxx
64/32
7F0000H-7FFFFFH
3F8000H-3FFFFFH
-8-
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
Table 3. NOR Flash Memory Bottom Boot Block Address (KAB01D100/KAB03D100)
KAB
01D1
00
KAB
03D1
00
Block Address
BA134
Bank2
Bank2
Address Range
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Block Size
(KB/KW)
Byte Mode
Word Mode
1
1
1
1
1
1
1
X
X
X
64/32
7F0000H-7FFFFFH
3F8000H-3FFFFFH
Block
BA133
1
1
1
1
1
1
0
X
X
X
64/32
7E0000H-7EFFFFH
3F0000H-3F7FFFH
BA132
1
1
1
1
1
0
1
X
X
X
64/32
7D0000H-7DFFFFH
3E8000H-3EFFFFH
BA131
1
1
1
1
1
0
0
X
X
X
64/32
7C0000H-7CFFFFH
3E0000H-3E7FFFH
BA130
1
1
1
1
0
1
1
X
X
X
64/32
7B0000H-7BFFFFH
3D8000H-3DFFFFH
BA129
1
1
1
1
0
1
0
X
X
X
64/32
7A0000H-7AFFFFH
3D0000H-3D7FFFH
BA128
1
1
1
1
0
0
1
X
X
X
64/32
790000H-79FFFFH
3C8000H-3CFFFFH
BA127
1
1
1
1
0
0
0
X
X
X
64/32
780000H-78FFFFH
3C0000H-3C7FFFH
BA126
1
1
1
0
1
1
1
X
X
X
64/32
770000H-77FFFFH
3B8000H-3BFFFFH
BA125
1
1
1
0
1
1
0
X
X
X
64/32
760000H-76FFFFH
3B0000H-3B7FFFH
BA124
1
1
1
0
1
0
1
X
X
X
64/32
750000H-75FFFFH
3A8000H-3AFFFFH
BA123
1
1
1
0
1
0
0
X
X
X
64/32
740000H-74FFFFH
3A0000H-3A7FFFH
BA122
1
1
1
0
0
1
1
X
X
X
64/32
730000H-73FFFFH
398000H-39FFFFH
BA121
1
1
1
0
0
1
0
X
X
X
64/32
720000H-72FFFFH
390000H-397FFFH
BA120
1
1
1
0
0
0
1
X
X
X
64/32
710000H-71FFFFH
388000H-38FFFFH
BA119
1
1
1
0
0
0
0
X
X
X
64/32
700000H-70FFFFH
380000H-387FFFH
BA118
1
1
0
1
1
1
1
X
X
X
64/32
6F0000H-6F1FFFH
378000H-37FFFFH
BA117
1
1
0
1
1
1
0
X
X
X
64/32
6E0000H-6EFFFFH
370000H-377FFFH
BA116
1
1
0
1
1
0
1
X
X
X
64/32
6D0000H-6DFFFFH
368000H-36FFFFH
BA115
1
1
0
1
1
0
0
X
X
X
64/32
6C0000H-6CFFFFH
360000H-367FFFH
BA114
1
1
0
1
0
1
1
X
X
X
64/32
6B0000H-6BFFFFH
358000H-35FFFFH
BA113
1
1
0
1
0
1
0
X
X
X
64/32
6A0000H-6AFFFFH
350000H-357FFFH
BA112
1
1
0
1
0
0
1
X
X
X
64/32
690000H-69FFFFH
348000H-34FFFFH
BA111
1
1
0
1
0
0
0
X
X
X
64/32
680000H-68FFFFH
340000H-347FFFH
BA110
1
1
0
0
1
1
1
X
X
X
64/32
670000H-67FFFFH
338000H-33FFFFH
BA109
1
1
0
0
1
1
0
X
X
X
64/32
660000H-66FFFFH
330000H-337FFFH
BA108
1
1
0
0
1
0
1
X
X
X
64/32
650000H-65FFFFH
328000H-32FFFFH
BA107
1
1
0
0
1
0
0
X
X
X
64/32
640000H-64FFFFH
320000H-327FFFH
X
64/32
630000H-63FFFFH
318000H-31FFFFH
X
64/32
620000H-62FFFFH
310000H-317FFFH
BA106
BA105
1
1
1
1
0
0
0
0
0
0
1
1
1
0
X
X
X
X
BA104
1
1
0
0
0
0
1
X
X
X
64/32
610000H-61FFFFH
308000H-30FFFFH
BA103
1
1
0
0
0
0
0
X
X
X
64/32
600000H-60FFFFH
300000H-307FFFH
BA102
1
0
1
1
1
1
1
X
X
X
64/32
5F0000H-5FFFFFH
2F8000H-2FFFFFH
BA101
1
0
1
1
1
1
0
X
X
X
64/32
5E0000H-5EFFFFH
2F0000H-2F7FFFH
BA100
1
0
1
1
1
0
1
X
X
X
64/32
5D0000H-5DFFFFH
2E8000H-2EFFFFH
BA99
1
0
1
1
1
0
0
X
X
X
64/32
5C0000H-5CFFFFH
2E0000H-2E7FFFH
-9-
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
Table 3. NOR Flash Memory Bottom Block Address (KAB01D100/KAB03D100)
KAB
01D1
00
Bank2
KAB
03D1
00
Bank2
Block Address
Address Range
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Block Size
(KB/KW)
Byte Mode
Word Mode
BA98
1
0
1
1
0
1
1
X
X
X
64/32
5B0000H-5BFFFFH
2D8000H-2DFFFFH
BA97
1
0
1
1
0
1
0
X
X
X
64/32
5A0000H-5AFFFFH
2D0000H-2D7FFFH
BA96
1
0
1
1
0
0
1
X
X
X
64/32
590000H-59FFFFH
2C8000H-2CFFFFH
BA95
1
0
1
1
0
0
0
X
X
X
64/32
580000H-58FFFFH
2C0000H-2C7FFFH
BA94
1
0
1
0
1
1
1
X
X
X
64/32
570000H-57FFFFH
2B8000H-2BFFFFH
BA93
1
0
1
0
1
1
0
X
X
X
64/32
560000H-56FFFFH
2B0000H-2B7FFFH
BA92
1
0
1
0
1
0
1
X
X
X
64/32
550000H-55FFFFH
2A8000H-2AFFFFH
BA91
1
0
1
0
1
0
0
X
X
X
64/32
540000H-54FFFFH
2A0000H-2A7FFFH
BA90
1
0
1
0
0
1
1
X
X
X
64/32
530000H-53FFFFH
298000H-29FFFFH
BA89
1
0
1
0
0
1
0
X
X
X
64/32
520000H-52FFFFH
290000H-297FFFH
BA88
1
0
1
0
0
0
1
X
X
X
64/32
510000H-51FFFFH
288000H-28FFFFH
BA87
1
0
1
0
0
0
0
X
X
X
64/32
500000H-50FFFFH
280000H-287FFFH
BA86
1
0
0
1
1
1
1
X
X
X
64/32
4F0000H-4FFFFFH
278000H-27FFFFH
BA85
1
0
0
1
1
1
0
X
X
X
64/32
4E0000H-4EFFFFH
270000H-277FFFH
BA84
1
0
0
1
1
0
1
X
X
X
64/32
4D0000H-4DFFFFH
268000H-26FFFFH
BA83
1
0
0
1
1
0
0
X
X
X
64/32
4C0000H-4CFFFFH
260000H-267FFFH
BA82
1
0
0
1
0
1
1
X
X
X
64/32
4B0000H-4BFFFFH
258000H-25FFFFH
BA81
1
0
0
1
0
1
0
X
X
X
64/32
4A0000H-4AFFFFH
250000H-257FFFH
BA80
1
0
0
1
0
0
1
X
X
X
64/32
490000H-49FFFFH
248000H-24FFFFH
BA79
1
0
0
1
0
0
0
X
X
X
64/32
480000H-48FFFFH
240000H-247FFFH
BA78
1
0
0
0
1
1
1
X
X
X
64/32
470000H-47FFFFH
238000H-23FFFFH
BA77
1
0
0
0
1
1
0
X
X
X
64/32
460000H-46FFFFH
230000H-237FFFH
BA76
1
0
0
0
1
0
1
X
X
X
64/32
450000H-45FFFFH
228000H-22FFFFH
BA75
1
0
0
0
1
0
0
X
X
X
64/32
440000H-44FFFFH
220000H-227FFFH
BA74
1
0
0
0
0
1
1
X
X
X
64/32
430000H-43FFFFH
218000H-21FFFFH
BA73
1
0
0
0
0
1
0
X
X
X
64/32
420000H-42FFFFH
210000H-217FFFH
BA72
1
0
0
0
0
0
1
X
X
X
64/32
410000H-41FFFFH
208000H-20FFFFH
BA71
1
0
0
0
0
0
0
X
X
X
64/32
400000H-40FFFFH
200000H-207FFFH
Block
- 10 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
Table 3. NOR Flash Memory Bottom Boot Block Address (KAB01D100/KAB03D100)
KAB
01D1
00
KAB
03D1
00
Block Address
BA70
Bank2
Bank1
Address Range
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Block Size
(KB/KW)
Byte Mode
Word Mode
0
1
1
1
1
1
1
X
X
X
64/32
3F0000H-3FFFFFH
1F8000H-1FFFFFH
Block
BA69
0
1
1
1
1
1
0
X
X
X
64/32
3E0000H-3EFFFFH
1F0000H-1F7FFFH
BA68
0
1
1
1
1
0
1
X
X
X
64/32
3D0000H-3DFFFFH
1E8000H-1EFFFFH
BA67
0
1
1
1
1
0
0
X
X
X
64/32
3C0000H-3CFFFFH
1E0000H-1E7FFFH
BA66
0
1
1
1
0
1
1
X
X
X
64/32
3B0000H-3BFFFFH
1D8000H-1DFFFFH
BA65
0
1
1
1
0
1
0
X
X
X
64/32
3A0000H-3AFFFFH
1D0000H-1D7FFFH
BA64
0
1
1
1
0
0
1
X
X
X
64/32
390000H-39FFFFH
1C8000H-1CFFFFH
BA63
0
1
1
1
0
0
0
X
X
X
64/32
380000H-38FFFFH
1C0000H-1C7FFFH
BA62
0
1
1
0
1
1
1
X
X
X
64/32
370000H-37FFFFH
1B8000H-1BFFFFH
BA61
0
1
1
0
1
1
0
X
X
X
64/32
360000H-36FFFFH
1B0000H-1B7FFFH
BA60
0
1
1
0
1
0
1
X
X
X
64/32
350000H-35FFFFH
1A8000H-1AFFFFH
BA59
0
1
1
0
1
0
0
X
X
X
64/32
340000H-34FFFFH
1A0000H-1A7FFFH
BA58
0
1
1
0
0
1
1
X
X
X
64/32
330000H-33FFFFH
198000H-19FFFFH
BA57
0
1
1
0
0
1
0
X
X
X
64/32
320000H-32FFFFH
190000H-197FFFH
BA56
0
1
1
0
0
0
1
X
X
X
64/32
310000H-31FFFFH
188000H-18FFFFH
BA55
0
1
1
0
0
0
0
X
X
X
64/32
300000H-30FFFFH
180000H-187FFFH
BA54
0
1
0
1
1
1
1
X
X
X
64/32
2F0000H-2F1FFFH
178000H-17FFFFH
BA53
0
1
0
1
1
1
0
X
X
X
64/32
2E0000H-2EFFFFH
170000H-177FFFH
BA52
0
1
0
1
1
0
1
X
X
X
64/32
2D0000H-2DFFFFH
168000H-16FFFFH
BA51
0
1
0
1
1
0
0
X
X
X
64/32
2C0000H-2CFFFFH
160000H-167FFFH
BA50
0
1
0
1
0
1
1
X
X
X
64/32
2B0000H-2BFFFFH
158000H-15FFFFH
BA49
0
1
0
1
0
1
0
X
X
X
64/32
2A0000H-2AFFFFH
150000H-157FFFH
BA48
0
1
0
1
0
0
1
X
X
X
64/32
290000H-29FFFFH
148000H-14FFFFH
BA47
0
1
0
1
0
0
0
X
X
X
64/32
280000H-28FFFFH
140000H-147FFFH
BA46
0
1
0
0
1
1
1
X
X
X
64/32
270000H-27FFFFH
138000H-13FFFFH
BA45
0
1
0
0
1
1
0
X
X
X
64/32
260000H-26FFFFH
130000H-137FFFH
BA44
0
1
0
0
1
0
1
X
X
X
64/32
250000H-25FFFFH
128000H-12FFFFH
BA43
0
1
0
0
1
0
0
X
X
X
64/32
240000H-24FFFFH
120000H-127FFFH
X
64/32
230000H-23FFFFH
118000H-11FFFFH
X
64/32
220000H-22FFFFH
110000H-117FFFH
BA42
BA41
0
0
1
1
0
0
0
0
0
0
1
1
1
0
X
X
X
X
BA40
0
1
0
0
0
0
1
X
X
X
64/32
210000H-21FFFFH
108000H-10FFFFH
BA39
0
1
0
0
0
0
0
X
X
X
64/32
200000H-20FFFFH
100000H-107FFFH
BA38
0
0
1
1
1
1
1
X
X
X
64/32
1F0000H-1FFFFFH
0F8000H-0FFFFFH
BA37
0
0
1
1
1
1
0
X
X
X
64/32
1E0000H-1EFFFFH
0F0000H-0F7FFFH
BA36
0
0
1
1
1
0
1
X
X
X
64/32
1D0000H-1DFFFFH
0E8000H-0EFFFFH
BA35
0
0
1
1
1
0
0
X
X
X
64/32
1C0000H-1CFFFFH
0E0000H-0E7FFFH
Bank1
- 11 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
Table 3. NOR Flash Memory Bottom Block Address (KAB01D100/KAB03D100)
KAB
01D1
00
KAB
03D1
00
Block Address
BA34
Bank1
Bank1
Address Range
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Block Size
(KB/KW)
Byte Mode
Word Mode
0
0
1
1
0
1
1
X
X
X
64/32
1B0000H-1BFFFFH
0D8000H-0DFFFFH
Block
BA33
0
0
1
1
0
1
0
X
X
X
64/32
1A0000H-1AFFFFH
0D0000H-0D7FFFH
BA32
0
0
1
1
0
0
1
X
X
X
64/32
190000H-19FFFFH
0C8000H-0CFFFFH
BA31
0
0
1
1
0
0
0
X
X
X
64/32
180000H-18FFFFH
0C0000H-0C7FFFH
BA30
0
0
1
0
1
1
1
X
X
X
64/32
170000H-17FFFFH
0B8000H-0BFFFFH
BA29
0
0
1
0
1
1
0
X
X
X
64/32
160000H-16FFFFH
0B0000H-0B7FFFH
BA28
0
0
1
0
1
0
1
X
X
X
64/32
150000H-15FFFFH
0A8000H-0AFFFFH
BA27
0
0
1
0
1
0
0
X
X
X
64/32
140000H-14FFFFH
0A0000H-0A7FFFH
BA26
0
0
1
0
0
1
1
X
X
X
64/32
130000H-13FFFFH
098000H-09FFFFH
BA25
0
0
1
0
0
1
0
X
X
X
64/32
120000H-12FFFFH
090000H-097FFFH
BA24
0
0
1
0
0
0
1
X
X
X
64/32
110000H-11FFFFH
088000H-08FFFFH
BA23
0
0
1
0
0
0
0
X
X
X
64/32
100000H-10FFFFH
080000H-087FFFH
BA22
0
0
0
1
1
1
1
X
X
X
64/32
0F0000H-0FFFFFH
078000H-07FFFFH
BA21
0
0
0
1
1
1
0
X
X
X
64/32
0E0000H-0EFFFFH
070000H-077FFFH
BA20
0
0
0
1
1
0
1
X
X
X
64/32
0D0000H-0DFFFFH
068000H-06FFFFH
BA19
0
0
0
1
1
0
0
X
X
X
64/32
0C0000H-0CFFFFH
060000H-067FFFH
BA18
0
0
0
1
0
1
1
X
X
X
64/32
0B0000H-0BFFFFH
058000H-05FFFFH
BA17
0
0
0
1
0
1
0
X
X
X
64/32
0A0000H-0AFFFFH
050000H-057FFFH
BA16
0
0
0
1
0
0
1
X
X
X
64/32
090000H-09FFFFH
048000H-04FFFFH
BA15
0
0
0
1
0
0
0
X
X
X
64/32
080000H-08FFFFH
040000H-047FFFH
BA14
0
0
0
0
1
1
1
X
X
X
64/32
070000H-07FFFFH
038000H-03FFFFH
BA13
0
0
0
0
1
1
0
X
X
X
64/32
060000H-06FFFFH
030000H-037FFFH
BA12
0
0
0
0
1
0
1
X
X
X
64/32
050000H-05FFFFH
028000H-02FFFFH
BA11
0
0
0
0
1
0
0
X
X
X
64/32
040000H-04FFFFH
020000H-027FFFH
BA10
0
0
0
0
0
1
1
X
X
X
64/32
030000H-03FFFFH
018000H-01FFFFH
BA9
0
0
0
0
0
1
0
X
X
X
64/32
020000H-02FFFFH
010000H-017FFFH
BA8
0
0
0
0
0
0
1
X
X
X
64/32
010000H-01FFFFH
008000H-00FFFFH
BA7
0
0
0
0
0
0
0
1
1
1
8/4
00E000H-00FFFFH
007000H-007FFFH
BA6
0
0
0
0
0
0
0
1
1
0
8/4
00C000H-00DFFFH
006000H-006FFFH
BA5
0
0
0
0
0
0
0
1
0
1
8/4
00A000H-00BFFFH
005000H-005FFFH
BA4
0
0
0
0
0
0
0
1
0
0
8/4
008000H-009FFFH
004000H-004FFFH
BA3
0
0
0
0
0
0
0
0
1
1
8/4
006000H-007FFFH
003000H-003FFFH
BA2
0
0
0
0
0
0
0
0
1
0
8/4
004000H-005FFFH
002000H-002FFFH
BA1
0
0
0
0
0
0
0
0
0
1
8/4
002000H-003FFFH
001000H-001FFFH
BA0
0
0
0
0
0
0
0
0
0
0
8/4
000000H-001FFFH
000000H-000FFFH
NOTE: The bank address bits are A21 ∼ A20 for KAB01D100, A21 for KAB04D100.
Table 4. Secode Block Addresses for Bottom Boot Devices
Device
Block Address
A21-A12
Block
Size
(X8)
Address Range
(X16)
Address Range
KAB01D100/KAB03D100
0000000xxx
64/32
000000H-00FFFFH
000000H-007FFFH
- 12 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NOR FLASH MEMORY COMMAND DEFINITIONS
The NOR Flash Memory operates by selecting and executing its operational modes. Each operational mode has its own command
set. In order to select a certain mode, a proper command with specific address and data sequences must be written into the command register. Writing incorrect information which include address and data or writing an improper command will reset the device to
the read mode. The defined valid register command sequences are stated in Table 5. Note that Erase Suspend (B0H) and Erase
Resume (30H) commands are valid only while the Block Erase Operation is in progress.
Table 5. Command Sequences
1st Cycle
Command Sequence
Word
Addr
Read
Autoselect
Block Group
Protect Verify
(2,3)
Auto Select
Secode Block
Factory Protect
Verify (2,3)
Enter Secode
Block Region
Exit Secode
Block Region
RD
Addr
XXXH
Word
Byte
Word
Byte
5th Cycle
6th Cycle
2AAH
555H
DA/
555H
DA/
AAAH
DA/
X00H
DA/
X00H
555H
DA/
555H
555H
DA/
555H
555H
DA/
555H
Word
Byte
Word
Byte
2AAH
555H
555H
AAAH
1
F0H
Addr
555H
AAAH
4
Data
AAH
Addr
555H
55H
AAAH
2AAH
90H
4
Data
AAH
Addr
555H
55H
AAAH
2AAH
Data
AAH
Addr
555H
55H
AAAH
2AAH
AAH
Addr
555H
55H
AAAH
2AAH
DA/
AAAH
90H
4
Data
DA/
AAAH
90H
4
DA/
AAAH
90H
555H
555H
ECH
DA/
X01H
DA/
X02H
(See Table 9)
BA /
X02H
BA/
X04H
(See Table 9)
DA /
X03H
DA/
X06H
(See Table 9)
AAAH
3
Data
AAH
Addr
555H
55H
AAAH
2AAH
88H
555H
555H
555H
555H
AAAH
XXXH
4
Data
Program
AAH
555H
55H
AAAH
2AAH
90H
00H
AAAH
PA
4
Data
AAH
Addr
Unlock Bypass
Unlock Bypass
Reset
4th Cycle
Byte
1
Addr
Unlock Bypass
Program
3rd Cycle
Word
RA
Data
Autoselect
Device Code
(2,3)
Byte
Data
Reset
Autoselect
Manufacturer
ID (2,3)
2nd Cycle
Cycle
555H
55H
AAAH
2AAH
A0H
555H
555H
PD
AAAH
3
Data
AAH
55H
Addr
XXXH
PA
20H
A0H
PD
XXXH
XXXH
2
Data
Addr
2
Data
90H
Addr
Chip Erase
555H
00H
AAAH
2AAH
555H
555H
555H
555H
AAAH
555H
AAAH
6
Data
AAH
Addr
Block Erase
555H
55H
AAAH
2AAH
80H
AAAH
AAH
555H
AAAH
55H
2AAH
10H
555H
BA
6
Data
AAH
55H
80H
AAH
55H
30H
XXXH
Block Erase
Suspend (4, 5)
Addr
Data
B0H
Block Erase
Resume
Addr
XXXH
1
1
Data
30H
Addr
CFI Query (6)
55H
AAH
1
Data
98H
- 13 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NOTES:
1. RA : Read Address, PA : Program Address, RD : Read Data, PD : Program Data
DA : Dual Bank Address (A20 - A21), BA : Block Address (A12 - A21), X = Don’t care .
2. To terminate the Autoselect Mode, it is necessary to write Reset command to the register.
3. The 4th cycle data of Autoselect mode is output data.
The 3rd and 4th cycle bank addresses of Autoselect mode must be same.
4. The Read / Program operations at non-erasing blocks and the autoselect mode are allowed in the Erase Suspend mode.
5. The Erase Suspend command is applicable only to the Block Erase operation.
6. Command is valid when the device is in read mode or Autoselect mode.
7. DQ8 - DQ15 are don’t care in command sequence, but RD and PD is excluded.
8. A11 - A21 are also don’t care, except for the case of special notice.
Table 6. NOR Flash Memory Autoselect Codes
DQ8 to DQ15
Description
DQ7 to DQ0
BYTE = VIH
BYTE = VIL
X
X
ECH
Device Code KAB02D100 (Top Boot Block)
22H
X
E0H
Device Code KAB01D100 (Bottom Boot Block)
22H
X
E2H
Device Code KAB04D100 (Top Boot Block)
22H
X
E1H
Device Code KAB03D100 (Bottom Boot Block)
22H
X
E3H
X
X
01H (Protected),
00H (Unprotected)
X
X
80H (Factory locked),
00H (Not factory locked)
Manufacturer ID
Block Protection Verification
Secode Block Indicator Bit (DQ7)
NOTES: 1. L=Logic Low=VIL, H=Logic High=VIH, DA=Dual Bank Address, BA=Block Address, X=Don’t care.
2. Secode Block : Security Code Block.
- 14 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NAND FLASH PRODUCT INTRODUCTION
The NAND Flash Memory is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 264 columns. Spare 8 columns are located in 256 to 263 column address. A 264-word data register is connected to memory cell arrays accommodating data
transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16
cells that are serially connected like NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages
formed by one NAND structures, totaling 8,448 NAND structures of 16 cells. The array organization is shown in Figure 2. Program
and read operations are executed on a page basis, while erase operation is executed on a block basis. The memory array consists
of 1024 blocks, and a block is separately erasable by 8K-word unit. It indicates that the bit by bit erase operation is prohibited on
the NAND Flash Memory.
The NAND Flash Memory has addresses multiplexed with lower 8 I/O′s. The NAND Flash Memory allows sixteen bit wide data transfer into and out of page registers. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by
maintaining consistency in system board design. Command, address and data are all written through I/O′s by bringing WE to low
while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to
multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except Page Program command
and Block Erase command which require two cycles: one cycle for setup and another for execution. The 8M word physical space
requires 24 addresses, thereby requiring three cycles for byte-level addressing: column address, low row address and high row
address, in that order. Page Read and Page Program need the same three address cycles following required command input. In
Block Erase operation, however, only two row address cycles are used. Device operations are selected by writing specific commands into command register. Table 7 defines the specific commands of the NAND Flash Memory.
Table 7. Command Sets
Function
1st. Cycle
2nd. Cycle
Read 1
00h
-
Read 2
50h
-
Read ID
90h
-
Reset
FFh
-
Page Program
80h
10h
Block Erase
60h
D0h
Read Status
70h
-
Acceptable Command during Busy
O
O
Table 8. NOR Flash Operations Table
Operation
CER
OE
WE
BYTE
WP/
ACC
A9
A6
A1
A0
DQ15/
A-1
DQ8/
DQ14
DQ0/
DQ7
RESET
A9
A6
A1
A0
A9
A6
A1
A0
DQ15
DOUT
DOUT
H
A-1
High-Z
DOUT
H
word
L
L
H
H
byte
L
L
H
L
VccR ±
0.3V
X
X
X
(2)
X
X
X
X
High-Z
High-Z
High-Z
(2)
Output Disable
L
H
H
X
L/H
X
X
X
X
High-Z
High-Z
High-Z
H
Reset
X
X
X
X
L/H
X
X
X
X
High-Z
High-Z
High-Z
L
word
L
H
L
H
A9
A6
A1
A0
DIN
DIN
DIN
H
byte
L
H
L
L
A9
A6
A1
A0
A-1
High-Z
DIN
H
Enable Block Group
Protect (3)
L
H
L
X
L/H
X
L
H
L
X
X
DIN
VID
Enable Block Group
Unprotect (3)
L
H
L
X
(4)
X
H
H
L
X
X
DIN
VID
Temporary Block
Group
X
X
X
X
(4)
X
X
X
X
X
X
X
VID
Read
L/H
Stand-by
Write
(4)
- 15 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NOTES:
1. L = VIL (Low), H = VIH (High), VID = 8.5V~12.5V, DIN = Data in, DOUT = Data out, X = Don't care.
2. WP/ACC and RESET pin are asserted at VccR±0.3 V or Vss±0.3 V in the Stand-by mode.
3. Addresses must be composed of the Block address (A12 - A21).
The Block Protect and Unprotect operations may be implemented via programming equipment too.
Refer to the "Block Group Protection and Unprotection".
4. If WP/ACC=VIL, the two outermost boot blocks is protected. If WP/ACC=VIH, the two outermost boot block protection depends on whether those
blocks were last protected or unprotected using the method described in "Block Group Protection and Unprotection". If WP/ACC=VHH, all blocks
will be temporarily unprotected.
Table 9. NAND Flash Operations Table
CLE
ALE
CER
WE
RE
WP
H
L
L
H
X
L
H
L
H
X
H
L
L
H
H
L
H
L
H
H
L
L
L
H
H
Mode
Command Input
Read Mode
Address Input(3clock)
Command Input
Write Mode
Address Input(3clock)
Data Input
L
L
L
H
X
Data Output
X
X
X
X
H
X
During Read(Busy)
X
X
X
X
X
H
During Program(Busy)
X
X
X
X
X
H
During Erase(Busy)
X
X(1)
X
X
X
L
X
X
H
X
X
0V/VccF(2)
Write Protect
Stand-by
NOTE: 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Table 10. UtRAM Operations Table
CSu
ZZ
H
H
OE
1)
X
WE
X
1)
1)
LB
UB
I/O0~7
I/O8~15
Mode
Power
1)
1)
High-Z
High-Z
Deselected
Standby
1)
X
X
L
X
X
X
X
High-Z
High-Z
Deselected
Deep Power
L
H
X1)
X1)
H
H
High-Z
High-Z
Deselected
Standby
L
H
H
H
L
X
High-Z
High-Z
Output Disabled
Active
L
H
H
H
X1)
L
High-Z
High-Z
Output Disabled
Active
L
H
L
H
L
H
Dout
High-Z
Lower Byte Read
Active
L
H
L
H
H
L
High-Z
Dout
Upper Byte Read
Active
L
H
L
H
L
L
Dout
Dout
Word Read
Active
L
H
X1)
L
L
H
Din
High-Z
Lower Byte Write
Active
L
H
1)
X
L
H
L
High-Z
Din
Upper Byte Write
Active
L
H
X1)
L
L
L
Din
Din
Word Write
Active
X
1)
1)
1)
1)
1. X = VIL or VIH
- 16 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NOR FLASH DEVICE OPERATION
Byte/Word Mode
If the BYTE pin is set at logical "1" , the device is in word mode, DQ0-DQ15 are active. Otherwise the BYTE pin is set at logical "0" ,
the device is in byte mode, DQ0-DQ7 are active. DQ8-DQ14 are in the High-Z state and DQ15 pin is used as an input for the LSB (A1) address pin.
Read Mode
The NOR Flash memory is controlled by Chip Enable (CER), Output Enable (OE) and Write Enable (WE). When CER and OE are
low and WE is high, the data stored at the specified address location,will be the output of the device. The outputs are in high impedance state whenever CER or OE is high.
Standby Mode
The NOR Flash memory features Stand-by Mode to reduce power consumption. This mode puts the device on hold when the device
is deselected by making CER high (CER = VIH). Refer to the DC characteristics for more details on stand-by modes.
Output Disable
The device outputs are disabled when OE is High (OE = VIH). The output pins are in high impedance state.
Automatic Sleep Mode
The NOR Flash Memory features Automatic Sleep Mode to minimize the device power consumption. Since the device typically draws
5µA of the current in Automatic Sleep Mode, this feature plays an extremely important role in battery-powered applications. When
addresses remain steady for tAA+50ns, the device automatically activates the Automatic Sleep Mode. In the sleep mode, output data
is latched and always available to the system. When addresses are changed, the device provides new data without wait time.
tAA + 50ns
Address
Outputs
Data
Data
Data
Data
Data
Data
Auto Sleep Mode
Figure 3. Auto Sleep Mode Operation
Autoselect Mode
The NOR Flash memory offers the Autoselect Mode to identify manufacturer and device type by reading a binary code. The Autoselect Mode allows programming equipment to automatically match the device to be programmed with its corresponding programming
algorithm. In addition, this mode allows the verification of the status of write protected blocks. The manufacturer and device code can
be read via the command register. The Command Sequence is shown in Table 5 and Figure 4. The autoselect operation of block protect verification is initiated by first writing two unlock cycle. The third cycle must contain the bank address and autoselect command
(90H). If Block address while (A6, A1, A0) = (0,1,0) is finally asserted on the address ball, it will produce a logical "1" at the device
output DQ0 to indicate a write protected block or a logical "0" at the device output DQ0 to indicate a write unprotected block. To terminate the autoselect operation, write Reset command (F0H) into the command register.
- 17 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
WE
A21∼A0(x16)/*
A21∼A-1(x8)
DQ15∼DQ0
2AAH/
555H
555H/
AAAH
01H/
02H
22E0H
or
22E2H
ECH
90H
55H
AAH
00H/
00H
555H/
AAAH
F0H
Manufacturer
Device Code
Return to
Code (KAB02C100 / KAB01C100) Read Mode
NOTE: The 3rd Cycle and 4th Cycle address must include the same bank address. Please refer to Table 6 for device code.
Figure 4. Autoselect Operation
Write (Program/Erase) Mode
The NOR Flash memory executes its program/erase operations by writing commands into the command register. In order to write the
commands to the register, CER and WE must be low and OE must be high. Addresses are latched on the falling edge of CER or WE
(whichever occurs last) and the data are latched on the rising edge of CER or WE (whichever occurs first). The device uses standard
microprocessor write timing.
Program
The NOR Flash memory can be programmed in units of a word or a byte. Programming is writing 0's into the memory array by executing the Internal Program Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address
of the memory location and the data to be programmed at that location are written. The device automatically generates adequate program pulses and verifies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is not required to provide further controls or timings.
During the Internal Program Routine, commands written to the device will be ignored. Note that a hardware reset during a program
operation will cause data corruption at the corresponding location.
WE
A21∼A0(x16)/
A21∼A-1(x8)
DQ15-DQ0
2AAH/
555H
555H/
AAAH
AAH
555H/
AAAH
55H
Program
Address
A0H
Program
Data
Program
Start
R/BR
Figure 5. Program Command Sequence
- 18 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
Unlock Bypass
The NOR Flash memory provides the unlock bypass mode to save its program time. The mode is invoked by the unlock bypass command sequence. Unlike the standard program command sequence that contains four bus cycles, the unlock bypass program command sequence comprises only two bus cycles.
The unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. Writing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H). Once the device is in the unlock
bypass mode, the unlock bypass program command sequence is necessary to program in this mode. The unlock bypass program
command sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the program address and data. This command sequence is the only valid one for programming the device in the unlock bypass mode.
The unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock
bypass reset command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains
only the data (00H). Then, the device returns to the read mode.
Chip Erase
To erase a chip is to write 1′s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus
cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two
more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the
entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE or CER
pulse in the command sequence and terminates when DQ7 is "1". After that the device returns to the read mode.
WE
A21∼A0(x16)/
A21∼A-1(x8)
DQ15-DQ0
555H/
AAAH
2AAH/
555H
AAH
555H/
AAAH
55H
555H
AAAH
80H
2AAH/
555H
AAH
555H/
AAAH
55H
10H
Chip Erase
Start
R/BR
Figure 6. Chip Erase Command Sequence
Block Erase
To erase a block is to write 1′s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six
bus cycles to write the command sequence shown in Table 5. After the first two "unlock" cycles, the erase setup command (80H) is
written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine
automatically pre-programs and verifies the entire memory prior to erasing it. The block address is latched on the falling edge of WE
or CER, while the Block Erase command is latched on the rising edge of WE or CER.
Multiple blocks can be erased sequentially by writing the six bus-cycle operation in Fig 7. Upon completion of the last cycle for the
Block Erase, additional block address and the Block Erase command (30H) can be written to perform the Multi-Block Erase. An 50us
(typical) "time window" is required between the Block Erase command writes. The Block Erase command must be written within the
50us "time window", otherwise the Block Erase command will be ignored. The 50us "time window" is reset when the falling edge of
the WE occurs within the 50us of "time window" to latch the Block Erase command. During the 50us of "time window", any command
other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After the 50 us
of "time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase
address and command following the exceeded "time window" may or may not be accepted. No other commands will be recognized
except the Erase Suspend command.
- 19 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
WE
A21∼A0(x16)/
A21∼A-1(x8)
555H/
AAAH
DQ15-DQ0
2AAH/
555H
AAH
555H/
AAAH
555H/
AAAH
80H
55H
2AAH/
555H
AAH
Block
Address
55H
30H
Block Erase
Start
R/BR
Figure 7. Block Erase Command Sequence
Erase Suspend / Resume
The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. The Erase Suspend command is only valid during the Block Erase operation including the time window of 50µs. The Erase Suspend command is
not valid while the Chip Erase or the Internal Program Routine sequence is running.
When the Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 20µs to suspend
the erase operation. But, when the Erase Suspend command is written during the block erase time window (50µs) , the device immediately terminates the block erase time window and suspends the erase operation.
After the erase operation has been suspended, the device is availble for reading or programming data in a block that is not being
erased. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode.
When the Erase Resume command is executed, the Block Erase operation will resume. When the Erase Suspend or Erase Resume
command is executed, the addresses are in Don't Care state.
WE
A21∼A0(x16)/
A21A21∼A-1(x8)
DQ15-DQ0
555H/
AAAH
Block
Address
AAH
Block Erase
Command Sequence
XXXH
30H
XXXH
B0H
Block Erase
Start
Erase
Suspend
30H
Erase
Resume
Figure 8. Erase Suspend/Resume Command Sequence
- 20 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
Read While Write
The NOR Flash memory provides dual bank memory architecture that divides the memory array into two banks. The device is capable of reading data from one bank and writing data to the other bank simultaneously. This is so called the Read While Write operation
with dual bank architecture; this feature provides the capability of executing the read operation during Program/Erase or Erase-Suspend-Program operation.
The Read While Write operation is prohibited during the chip erase operation. It is also allowed during erase operation when either
single block or multiple blocks from same bank are loaded to be erased. It means that the Read While Write operation is prohibited
when blocks from Bank1 and another blocks from Bank2 are loaded all together for the multi-block erase operation.
Block Group Protection & Unprotection
The NOR Flash memory feature hardware block group protection. This feature will disable both program and erase operations in any
combination of forty one block groups of memory. Please refer to Tables 12 and 13. The block group protection feature is enabled
using programming equipment at the user’s site. The device is shipped with all block groups unprotected.
This feature can be hardware protected or unprotected. If a block is protected, program or erase command in the protected block will
be ignored by the device. The protected block can only be read. This is useful method to preserve an important program data. The
block group unprotection allows the protected blocks to be erased or programed. All blocks must be protected before unprotect operation is executing. The block protection and unprotection can be implemented by the following method.
Table 11. Block Group Protection & Unprotection
CER
OE
WE
BYTE
A9
A6
A1
A0
DQ15/
A-1
DQ8/
DQ14
DQ0/
DQ7
RESET
Block Group Protect
L
H
L
X
X
L
H
L
X
X
DIN
VID
Block Group Unprotect
L
H
L
X
X
H
H
L
X
X
DIN
VID
Operation
Address must be inputted to the block group address (A12~A21) during block group protection operation. Please refer to Figure 10
(Algorithm) and Switching Waveforms of Block Group Protect & Unprotect Operations.
Temporary Block Group Unprotect
The protected blocks of the NOR Flash memory can be temporarily unprotected by applying high voltage (VID = 8.5V ~ 12.5V) to the
RESET ball. In this mode, previously protected blocks can be programmed or erased with the program or erase command routines.
When the RESET ball goes high (RESET = VIH), all the previously protected blocks will be protected again. If the WP/ACC ball is
asserted at VIL , the two outermost boot blocks remain protected.
VID
V = VIH or VIL
RESET
CER
WE
Program & Erase operation
at Protected Block
Figure 9. Temporary Block Group Unprotect Sequence
- 21 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
START
COUNT = 1
RESET=VID
Wait 1µs
First Write
Cycle=60h?
No
Temporary Block Group
Unprotect Mode
Yes
Yes
Block Group
Protection ?
No
Block Protect
Algorithm
No
Set up Block Group
address
All Block Groups
Protected ?
Block Unprotect
Algorithm
Yes
Block Group <i>, i= 0
Block Group Unprotect
Write 60H
with
A6=1,A1=1
A0=0
Block Group Protect:
Write 60H to Block
Group address with
A6=0,A1=1
A0=0
Wait 15ms
Wait 150µs
Reset
COUNT=1
Verify Block Group
Protect:Write 40H to
Block Group address
with A6=0,
A1=1,A0=0
Increment
COUNT
Increment
COUNT
Read from
Block Group address
with A6=1,
A1=1,A0=0
Read from
Block Group address
with A6=0,
A1=1,A0=0
No
COUNT
=1000?
Data=01h?
No
Data=00h?
Yes
Yes
Yes
Yes
Device failed
Protect another
Block Group?
Set up next Block
Group address
No
No
COUNT
=25?
Verify Block Group
Unprotect:Write 40H to
Block Group address
with A6=1,
A1=1,A0=0
Device failed
Last Block Group
verified ?
No
Yes
Yes
Remove VID
from RESET
No
Remove VID
from RESET
Write RESET
command
Write RESET
command
END
END
NOTE: All blocks must be protected before unprotect operation is executing.
Figure 10. Block Group Protection & Unprotection Algorithms
- 22 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
Table 12. NOR Flash Memory Block Group Address (Top Boot Block)
Block Address
Block Group
BGA0
BGA1
Block
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
0
0
0
0
0
0
0
X
X
X
BA0
0
1
1
0
X
X
X
BA1 to BA3
1
1
0
0
0
0
0
BGA2
0
0
0
0
1
X
X
X
X
X
BA4 to BA7
BGA3
0
0
0
1
0
X
X
X
X
X
BA8 to BA11
BGA4
0
0
0
1
1
X
X
X
X
X
BA12 to BA15
BGA5
0
0
1
0
0
X
X
X
X
X
BA16 to BA19
BGA6
0
0
1
0
1
X
X
X
X
X
BA20 to BA23
BGA7
0
0
1
1
0
X
X
X
X
X
BA24 to BA27
BGA8
0
0
1
1
1
X
X
X
X
X
BA28 to BA31
BGA9
0
1
0
0
0
X
X
X
X
X
BA32 to BA35
BGA10
0
1
0
0
1
X
X
X
X
X
BA36 to BA39
BGA11
0
1
0
1
0
X
X
X
X
X
BA40 to BA43
BGA12
0
1
0
1
1
X
X
X
X
X
BA44 to BA47
BGA13
0
1
1
0
0
X
X
X
X
X
BA48 to BA51
BGA14
0
1
1
0
1
X
X
X
X
X
BA52 to BA55
BGA15
0
1
1
1
0
X
X
X
X
X
BA56 to BA59
BGA16
0
1
1
1
1
X
X
X
X
X
BA60 to BA63
BGA17
1
0
0
0
0
X
X
X
X
X
BA64 to BA67
BGA18
1
0
0
0
1
X
X
X
X
X
BA68 to BA71
BGA19
1
0
0
1
0
X
X
X
X
X
BA72 to BA75
BGA20
1
0
0
1
1
X
X
X
X
X
BA76 to BA79
BGA21
1
0
1
0
0
X
X
X
X
X
BA80 to BA83
BGA22
1
0
1
0
1
X
X
X
X
X
BA84 to BA87
BGA23
1
0
1
1
0
X
X
X
X
X
BA88 to BA91
BGA24
1
0
1
1
1
X
X
X
X
X
BA92 to BA95
BGA25
1
1
0
0
0
X
X
X
X
X
BA96 to BA99
BGA26
1
1
0
0
1
X
X
X
X
X
BA100 to BA103
BGA27
1
1
0
1
0
X
X
X
X
X
BA104 to BA107
BGA28
1
1
0
1
1
X
X
X
X
X
BA108 to BA111
BGA29
1
1
1
0
0
X
X
X
X
X
BA112 to BA115
BGA30
1
1
1
0
1
X
X
X
X
X
BA116 to BA119
BGA31
1
1
1
1
0
X
X
X
X
X
BA120 to BA123
0
0
0
1
X
X
X
BA124 to BA126
BGA32
1
1
1
1
1
1
0
BGA33
1
1
1
1
1
1
1
0
0
0
BA127
BGA34
1
1
1
1
1
1
1
0
0
1
BA128
BGA35
1
1
1
1
1
1
1
0
1
0
BA129
BGA36
1
1
1
1
1
1
1
0
1
1
BA130
BGA37
1
1
1
1
1
1
1
1
0
0
BA131
BGA38
1
1
1
1
1
1
1
1
0
1
BA132
BGA39
1
1
1
1
1
1
1
1
1
0
BA133
BGA40
1
1
1
1
1
1
1
1
1
1
BA134
- 23 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
Table 13. NOR Flash Memory Block Group Address (Bottom Boot Block)
Block Address
Block Group
Block
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
BGA0
0
0
0
0
0
0
0
0
0
0
BA0
BGA1
0
0
0
0
0
0
0
0
0
1
BA1
BGA2
0
0
0
0
0
0
0
0
1
0
BA2
BGA3
0
0
0
0
0
0
0
0
1
1
BA3
BGA4
0
0
0
0
0
0
0
1
0
0
BA4
BGA5
0
0
0
0
0
0
0
1
0
1
BA5
BGA6
0
0
0
0
0
0
0
1
1
0
BA6
BGA7
0
0
0
0
0
1
1
1
BA7
X
X
X
BA8 to BA10
BGA8
0
0
0
0
0
0
0
0
1
1
0
1
1
BGA9
0
0
0
0
1
X
X
X
X
X
BA11 to BA14
BGA10
0
0
0
1
0
X
X
X
X
X
BA15 to BA18
BGA11
0
0
0
1
1
X
X
X
X
X
BA19 to BA22
BGA12
0
0
1
0
0
X
X
X
X
X
BA23 to BA26
BGA13
0
0
1
0
1
X
X
X
X
X
BA27 to BA30
BGA14
0
0
1
1
0
X
X
X
X
X
BA31 to BA34
BGA15
0
0
1
1
1
X
X
X
X
X
BA35 to BA38
BGA16
0
1
0
0
0
X
X
X
X
X
BA39 to BA42
BGA17
0
1
0
0
1
X
X
X
X
X
BA43 to BA46
BGA18
0
1
0
1
0
X
X
X
X
X
BA47 to BA50
BGA19
0
1
0
1
1
X
X
X
X
X
BA51 to BA54
BGA20
0
1
1
0
0
X
X
X
X
X
BA55 to BA58
BGA21
0
1
1
0
1
X
X
X
X
X
BA59 to BA62
BGA22
0
1
1
1
0
X
X
X
X
X
BA63 to BA66
BGA23
0
1
1
1
1
X
X
X
X
X
BA67 to BA70
BGA24
1
0
0
0
0
X
X
X
X
X
BA71 to BA74
BGA25
1
0
0
0
1
X
X
X
X
X
BA75 to BA78
BGA26
1
0
0
1
0
X
X
X
X
X
BA79 to BA82
BGA27
1
0
0
1
1
X
X
X
X
X
BA83 to BA86
BGA28
1
0
1
0
0
X
X
X
X
X
BA87to BA90
BGA29
1
0
1
0
1
X
X
X
X
X
BA91 to BA94
BGA30
1
0
1
1
0
X
X
X
X
X
BA95 to BA98
BGA31
1
0
1
1
1
X
X
X
X
X
BA99 to BA102
BGA32
1
1
0
0
0
X
X
X
X
X
BA103 to BA106
BGA33
1
1
0
0
1
X
X
X
X
X
BA107 to BA110
BGA34
1
1
0
1
0
X
X
X
X
X
BA111 to BA114
BGA35
1
1
0
1
1
X
X
X
X
X
BA115 to BA118
BGA36
1
1
1
0
0
X
X
X
X
X
BA119 to BA122
BGA37
1
1
1
0
1
X
X
X
X
X
BA123 to BA126
BGA38
1
1
1
1
0
X
X
X
X
X
BA127 to BA130
0
0
BGA39
1
1
1
1
1
0
1
X
X
X
1
0
BGA40
1
1
1
1
1
1
1
X
X
X
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BA131 to BA133
BA134
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
Write Protect (WP)
The WP/ACC ball has two useful functions. The one is that certain boot block is protected by the hardware method not to use VID.
The other is that program operation is accelerated to reduce the program time (Refer to Accelerated program Operation Paragraph).
When the WP/ACC ball is asserted at VIL, the device can not perform program and erase operation in the two "outermost" 8K byte
boot blocks independently of whether those blocks were protected or unprotected using the method described in "Block Group protection/Unprotection".
The write protected blocks can only be read. This is useful method to preserve an important program data.
The two outermost 8K byte boot blocks are the two blocks containing the lowest addresses in a bottom-boot-configured device, or
the two blocks containing the highest addresses in a top-boot-congfigured device.
(KAB02D100/KAB04D100 : BA133 and BA134, KAB01D100/KAB03D100 : BA0 and BA1)
When the WP/ACC ball is asserted at VIH, the device reverts to whether the two outermost 8K byte boot blocks were last set to be
protected or unprotected. That is, block protection or unprotection for these two blocks depends on whether they were last protected
or unprotected using the method described in "Block Group protection/unprotection".
Recommend that the WP/ACC ball must not be in the state of floating or unconnected, otherwise the device may be led to malfunction.
Secode(Security Code) Block Region
The Secode Block feature provides a NOR Flash memory region to be stored unique and permanent identification code, that is, Electronic Serial Number (ESN), customer code and so on. This is primarily intended for customers who wish to use an Electronic Serial
Number (ESN) in the device with the ESN protected against modification. Once the Secode Block region is protected, any further
modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field.
The Secode Block is factory locked or customer lockable. Before the device is shipped, the factory locked Secode Block is written on
the special code and it is protected. The Secode Indicator bit (DQ7) is permanently fixed at "1" and it is not changed. The customer
lockable Secode Block is unprotected, therefore it is programmed and erased. The Secode Indicator bit (DQ7) of it is permanently
fixed at "0" and it is not changed. but once it is protected, there is no procedure to unprotect and modify the Secode Block.
The Secode Block region is 64K bytes in length and is accessed through a new command sequence (see Table 8). After the system
has written the Enter Secode Block command sequence, the system may read the Secode Block region by using the same
addresses of the boot blocks (8KBx8). The KAB02D100/KAB04D100 occupies the address of the byte mode 7F0000H to 7FFFFFH
(word mode 3F8000H to 3FFFFFH) and the KAB01D100/KAB03D100 type occupies the address of the byte mode 000000H to
00FFFFH (word mode 000000H to 007FFFH). This mode of operation continues until the system issues the Exit Secode Block command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to read
mode.
Accelerated Program Operation
Accelerated program operation reduces the program time through the ACC function. This is one of two functions provided by the WP/
ACC ball. When the WP/ACC ball is asserted as VHH, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotecting any protected blocks, and reduces the program operation time. The system would use a two-cycle program
command sequence as required by the Unlock Bypass mode. Removing VHH from the WP/ACC ball returns the device to normal
operation. Recommend that the WP/ACC ball must not be asserted at VHH except on accelerated program operation, or the
device may be damaged. In addition, the WP/ACC ball must not be in the state of floating or unconnected, otherwise the
device may be led to malfunction.
Software Reset
The reset command provides that the device is reseted to read mode or erase-suspend-read mode. The addresses are in Don't Care
state. The reset command is vaild between the sequence cycles in an erase command sequence before erasing begins, or in a program command sequence before programming begins. This resets the bank in which was operating to read mode. if the device is be
erasing or programming, the reset command is invalid until the operation is completed. Also, the reset command is valid between the
sequence cycles in an autoselect command sequence. In the autoselect mode, the reset command returns the bank to read mode. If
a bank entered the autoselect mode in the Erase Suspend mode, the reset command returns the bank to erase-suspend-read mode.
If DQ5 is high on erase or program operation, the reset command return the bank to read mode or erase-suspend-read mode if the
bank was in the Erase Suspend state.
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Revision 1.11
August 2003
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MCP MEMORY
KAB0xD100M - TxGP
Hardware Reset
The NOR Flash memory offers a reset feature by driving the RESET ball to VIL. The RESET ball must be kept low (VIL) for at least
500ns. When the RESET ball is driven low, any operation in progress will be terminated and the internal state machine will be reset
to the standby mode after 20us. If a hardware reset occurs during a program operation, the data at that particular location will be
lost. Once the RESET ball is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. Also, note
that all the data output balls are tri-stated for the duration of the RESET pulse.
The RESET ball may be tied to the system reset ball. If a system reset occurs during the Internal Program and Erase Routine, the
device will be automatically reset to the read mode ; this will enable the systems microprocessor to read the boot-up firmware from
the NOR Flash memory.
Power-up Protection
To avoid initiation of a write cycle during VccR Power-up, RESET low must be asserted during power-up. After RESET goes high, the
device is reset to the read mode.
Low VccR Write Inhibit
To avoid initiation of a write cycle during VccR power-up and power-down, a write cycle is locked out for VccR less than 1.8V. If VccR
< VLKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the device
will reset itself to the read mode. Subsequent writes will be ignored until the VccR level is greater than VLKO. It is the user′s responsibility to ensure that the control balls are logically correct to prevent unintentional writes when VccR is above 1.8V.
Write Pulse Glitch Protection
Noise pulses of less than 5ns(typical) on CER, OE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited under any one of the following conditions : OE = VIL, CER = VIH or WE = VIH. To initiate a write, CER and WE
must be "0", while OE is "1".
Commom NOR Flash Memory Interface
Common Flash Momory Interface is contrived to increase the compatibility of host system software. It provides the specific information of the device, such as memory size, byte/word configuration, and electrical features. Once this information has been obtained,
the system software will know which command sets to use to enable flash writes, block erases, and control the flash component.
When the system writes the CFI command(98H) to address 55H in word mode(or address AAH in byte mode), the device enters the
CFI mode. And then if the system writes the address shown in Table 14, the system can read the CFI data. Query data are always
presented on the lowest-order data outputs(DQ0-7) only. In word(x16) mode, the upper data outputs(DQ8-15) is 00h. To terminate
this operation, the system must write the reset command.
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MCP MEMORY
KAB0xD100M - TxGP
Table 14. Common NOR Flash Memory Interface Code
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
Query Unique ASCII string "QRY"
10H
11H
12H
20H
22H
24H
0051H
0052H
0059H
Primary OEM Command Set
13H
14H
26H
28H
0002H
0000H
Address for Primary Extended Table
15H
16H
2AH
2CH
0040H
0000H
Alternate OEM Command Set (00h = none exists)
17H
18H
2EH
30H
0000H
0000H
Address for Alternate OEM Extended Table (00h = none exists)
19H
1AH
32H
34H
0000H
0000H
VccR Min. (write/erase)
D7-D4: volt, D3-D0: 100 millivolt
1BH
36H
0027H
VccR Max. (write/erase)
D7-D4: volt, D3-D0: 100 millivolt
1CH
38H
0036H
Vpp Min. voltage(00H = no Vpp pin present)
1DH
3AH
0000H
Vpp Max. voltage(00H = no Vpp pin present)
1EH
3CH
0000H
Typical timeout per single byte/word write 2N us
1FH
3EH
0004H
Description
N
Typical timeout for Min. size buffer write 2 us(00H = not supported)
20H
40H
0000H
Typical timeout per individual block erase 2N ms
21H
42H
000AH
Typical timeout for full chip erase 2N ms(00H = not supported)
22H
44H
0000H
N
Max. timeout for byte/word write 2 times typical
23H
46H
0005H
Max. timeout for buffer write 2N times typical
24H
48H
0000H
Max. timeout per individual block erase 2N times typical
25H
4AH
0004H
Max. timeout for full chip erase 2N times typical(00H = not supported)
26H
4CH
0000H
Device Size = 2N byte
27H
4EH
0017H
Flash Device Interface description
28H
29H
50H
52H
0002H
0000H
Max. number of byte in multi-byte write = 2N
2AH
2BH
54H
56H
0000H
0000H
Number of Erase Block Regions within device
2CH
58H
0002H
Erase Block Region 1 Information
2DH
2EH
2FH
30H
5AH
5CH
5EH
60H
0007H
0000H
0020H
0000H
Erase Block Region 2 Information
31H
32H
33H
34H
62H
64H
66H
68H
007EH
0000H
0000H
0001H
Erase Block Region 3 Information
35H
36H
37H
38H
6AH
6CH
6EH
70H
0000H
0000H
0000H
0000H
Erase Block Region 4 Information
39H
3AH
3BH
3CH
72H
74H
76H
78H
0000H
0000H
0000H
0000H
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Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
Table 14. Common NOR Flash Memory Interface Code
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
Query-unique ASCII string "PRI"
40H
41H
42H
80H
82H
84H
0050H
0052H
0049H
Major version number, ASCII
43H
86H
0030H
Minor version number, ASCII
44H
88H
0030H
Address Sensitive Unlock(Bits 1-0)
0 = Required, 1= Not Required
Silcon Revision Number(Bits 7-2)
45H
8AH
0000H
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46H
8CH
0002H
Block Protect
0 = Not Supported, 1 = Supported
47H
8EH
0001H
Block Temporary Unprotect 00 = Not Supported, 01 = Supported
48H
90H
0001H
Block Protect/Unprotect scheme 04 = K8D1x16U mode
49H
92H
0004H
Simultaneous Operation (1)
00 = Not Supported, XX = Number of Blocks in Bank2
4AH
94H
00XXH
Burst Mode Type 00 = Not Supported, 01 = Supported
4BH
96H
0000H
Page Mode Type
00=Not supported, 01=4word page, 02=8word page
4CH
98H
0000H
ACC(Acceleration) Supply Minimum
00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV
4DH
9AH
0085H
ACC(Acceleration) Supply Maximum
00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV
4EH
9CH
00C5H
Top/Bottom Boot Block Flag
02H = Bottom Boot , 03H = Top Boot
4FH
9EH
000XH
Description
NOTE:
1. The number of blocks in Bank2 is device dependent.
KAB02D100/KAB04D100(16Mb/48Mb) = 60h (96blocks)
KAB01D100/KAB03D100(32Mb/32Mb ) = 40h (64blocks)
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MCP MEMORY
KAB0xD100M - TxGP
NOR FLASH DEVICE STATUS FLAGS
The NOR Flash memory has means to indicate its status of operation in the bank where a program or erase operation is in processes. Address must include bank address being excuted internal routine operation. The status is indicated by raising the device
status flag via corresponding DQ balls or the R/BR ball. The corresponding DQ balls are DQ7, DQ6, DQ5, DQ3 and DQ2. The status
is as follows :
Table 15. Hardware Sequence Flags
Status
Programming
Block Erase or Chip Erase
Exceeded
Time Limits
0
Toggle
0
1
DQ7
Toggle
0
0
Toggle
0
0
0
Non-Erase Suspended Block
Data
Data
Data
Data
Data
1
Non-Erase Suspended Block
DQ7
Toggle
0
0
1
0
DQ7
Toggle
1
0
No
Toggle
0
0
Toggle
1
1
(Note 2)
0
0
No
Toggle
0
Erase Suspend
Program
Erase Suspend Program
1
1
DQ3
1
Erase Suspend Read
Block Erase or Chip Erase
0
DQ5
1
Erase Suspend Read
Programming
R/BR
DQ6
Toggle
(Note 1)
Erase Suspended
Block
In Progress
DQ2
DQ7
DQ7
Toggle
1
NOTES:
1. DQ2 will toggle when the device performs successive read operations from the erase suspended block.
2. If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle.
DQ7 : Data Polling
When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as
an indication of the Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data
written to DQ7. When a user attempts to read the device during the Erase operation, DQ7 will be low. If the device is placed in the
Erase Suspend Mode, the status can be detected via the DQ7 ball. If the system tries to read an address which belongs to a block
that is being erased, DQ7 will be high. If a non-erased block address is read, the device will produce the true data to DQ7. If an
attempt is made to program a protected block, DQ7 outputs complements the data for approximately 1µs and the device then returns
to the Read Mode without changing data in the block. If an attempt is made to erase a protected block, DQ7 outputs complement
data in approximately 100us and the device then returns to the Read Mode without erasing the data in the block.
DQ6 : Toggle Bit
Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state,
DQ6 will toggle. Toggling DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase Suspend Mode,
an attempt to read an address that belongs to a block that is being erased will produce a high output of DQ6. If an address belongs
to a block that is not being erased, toggling is halted and valid data is produced at DQ6.
If an attempt is made to program a protected block, DQ6 toggles for approximately 1us and the device then returns to the Read Mode
without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for approximately 100µs and
the device then returns to the Read Mode without erasing the data in the block.
DQ5 : Exceed Timing Limits
If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure.
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Revision 1.11
August 2003
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MCP MEMORY
KAB0xD100M - TxGP
DQ3 : Block Erase Timer
The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50µs of the block erase time window expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write
commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block erase
time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been
accepted, the software may check the status of DQ3 following each block erase command.
DQ2 : Toggle Bit 2
The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase Suspend is in progress. When the device
executes the Internal Erase Routine, DQ2 toggles only if an erasing block is read. Although the Internal Erase Routine is in the
Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the Erase
Suspend mode, DQ2 toggles only if an address in the erasing block is read. If a non-erasing block address is read during the Erase
Suspend mode, then DQ2 will produce valid data. DQ2 will go High if the user tries to program a non-erase suspend block while the
device is in the Erase Suspend mode. Combination of the status in DQ6 and DQ2 can be used to distinguish the erase operation
from the program operation.
R/BR : Ready/Busy
The NOR Flash memory has a Ready / Busy output that indicates either the completion of an operation or the status of Internal Algorithms. If the output is Low, the device is busy with either a program or an erase operation. If the output is High, the device is ready to
accept any read/write or erase operation. When the R/BR pin is low, the device will not accept any additional program or erase commands with the exception of the Erase Suspend command. If the NOR Flash memory is placed in an Erase Suspend mode, the R/BR
output will be High. For programming, the RY/ BY is valid (R/BR = 0) after the rising edge of the fourth WE pulse in the four write
pulse sequence. For Chip Erase, R/BR is also valid after the rising edge of WE pulse in the six write pulse sequence. For Block
Erase, R/BR is also valid after the rising edge of the sixth WE pulse.
The pin is an open drain output, allowing two or more Ready/ Busy outputs to be OR-tied. An appropriate pull-up resistor is required
for proper operation.
Rp
Vcc
2.7 V
Vcc (Max.) - VOL (Max.)
Rp =
IOL + Σ IL
=
2.1mA + Σ IL
Ready / Busy
open drain output
where Σ IL is the sum of the input currents of all devices tied to the
Ready / Busy pin.
Vss
Device
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MCP MEMORY
KAB0xD100M - TxGP
Start
Start
Yes
No
DQ7 = Data ?
DQ6 = Toggle ?
No
Yes
No
No
DQ5 = 1 ?
DQ5 = 1 ?
Yes
Yes
DQ7 = Data ?
No
Yes
DQ6 = Toggle ?
Yes
No
Fail
Fail
Pass
Figure 11. Data Polling Algorithms
Pass
Figure 12. Toggle Bit Algorithms
Start
RESET=VID
(Note 1)
Perform Erase or
Program Operations
RESET=VIH
Temporary Block
Unprotect Completed
(Note 2)
NOTES:
1. All protected block groups are unprotected.
( If WP/ACC = VIL , the two outermost boot blocks remain protected )
2. All previously protected block groups are protected once again.
Figure 13. Temporary Block Group Unprotect Routine
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MCP MEMORY
KAB0xD100M - TxGP
NAND FLASH MEMORY OPERATION
PAGE READ
Upon initial device power up, the device status is initially Read1 command(00h) latched. This operation is also initiated by writing
00h to the command register along with three address cycles. Once the command is latched, it does not need to be written for the following page read operation. Two types of operation are available : random read, serial page read. The random read mode is enabled
when the page address is changed. The 264 words of data within the selected page are transferred to the data registers in less than
10µs(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data
in a page is loaded into the registers, they may be read out by sequential RE pulse of 50n period cycle. High to low transitions of the
RE clock take out the data from the selected column address up to the last column address.
Read1 and Read2 commands determine pointer which selects either main area or spare area. The spare area(256 to 263 words)
may be selectively accessed by writing the Read2 command. Addresses A0 to A2 set the starting address of spare area while
addresses A3 to A7 must be "L". To move the pointer back to the main area, Read1 command(00h) is needed. Figures 16 through
21 show typical sequence and timing for each read operation.
Figure 14,15 details the sequence.
Figure 14. Read1 Operation
CLE
CE
WE
ALE
tR
R/BF
RE
DQx
00h
Data Output(Sequential)
Start Add.(3Cycle)
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MCP MEMORY
KAB0xD100M - TxGP
Figure 15. Read2 Operation
CLE
CE
WE
ALE
tR
R/BF
RE
DQx
50h
(A3 ~ A7 :
"L")
Start Add.(3Cycle)
Data Output(Sequential)
A0 ~ A2 & A9 ~ A23
Spare Field
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it allows multiple partial page program of one word or consecutive words up
to 264, in a single page program cycle. The number of consecutive partial page program operation within the same page without
intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done in any random
order in a block. Page program cycle consists of a serial data loading(up to 264 words of data) into the page register, and program of
loaded data into the appropriate cell. Serial data loading can start in 2nd half array by moving pointer. About the pointer operation,
please refer to the attached technical notes. Serial data loading is executed by entering the Serial Data Input command(80h) and
three cycle address input and then serial data loading. The bytes except those to be programmed need not to be loaded. The Page
Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering 80h will not initiate
program process. The internal write controller automatically executes the algorithms and timings necessary for program and verification, thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Register command may be entered,
with RE and CE low, to read the status register. The CPU can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming
is in progress. When the Page Program is completed, the Write Status Bit(I/O 0) may be checked(Figure 16). The internal write verification detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status
command mode until another valid command is written to the command register.
Figure 16 details the sequence.
Figure 16. Program & Read Status Operation
tPROG
R/BF
DQx
80h
Address & Data Input
10h
70h
DQ0
Pass
Fail
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MCP MEMORY
KAB0xD100M - TxGP
BLOCK ERASE
The Erase operation is done on a block(16K Bytes) basis. Block Erase is executed by entering Erase Setup command(60h) and 2
cycle block addresses and Erase Confirm command(D0h). Only address A14 to A23 is valid while A9 to A13 is ignored. This twostep sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external
noise condition. At the rising edge of WE after erase confirm command input, internal write controller handles erase and erase-verification. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked.
Figure 6 details the sequence.
Figure 17. Block Erase Operation
tBERS
R/BF
DQx
60h
Address Input(2Cycle)
Pass
DQ0
70h
D0h
Block Add. : A9 ~ A23
Fail
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to command register, a read cycle takes out
the content of the Status Register to the I/O pins on the falling edge of CEF or RE. This two line control allows the system to poll the
progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CEF does not need to be
toggled for updated status. Refer to table 16 for specific Status Register definitions. The command register remains in Status Read
mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command(00h or 50h) should be given before sequential page read cycle.
Table 16. Read Status Register Definition
DQ #
Status
Definition
DQ0
Program / Erase
"0" : Successful Program / Erase
"1" : Error in Program / Erase
DQ1
DQ2
DQ3
"0"
Reserved for Future
Use
"0"
"0"
DQ4
"0"
DQ5
"0"
DQ6
Device Operation
DQ7
Write Protect
DQ8~15
Not use
"0" : Busy
"1" : Ready
"0" : Protected
"1" : Not Protected
Don’t care
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KAB0xD100M - TxGP
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECh), and the device code (53h) respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 18 shows the operation sequence.
Figure 18. Read ID Operation
CLE
tCEA
CEF
WE
tAR1
ALE
tWHR
RE
I/Ox
tREA
90h
00h
ECh
Address. 1cycle
Maker code
53h
Device code
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 17 for device status after reset operation. If the device is
already in reset state, new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 19 below.
Figure 19. RESET Operation
tRST
R/BF
DQx
FFh
Table 17. Device Status
Operation Mode
After Power-up
After Reset
Read 1
Waiting for next command
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MCP MEMORY
KAB0xD100M - TxGP
READY/BUSY
The device has a R/BF output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/BF pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/BF outputs to be Or-tied. Because pull-up resistor value is related to tr(R/BF)
and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 20). Its value can
be determined by the following guidance.
Rp
VccR
ibusy
Ready Vcc
R/BF
open drain output
2.0V
0.8V
Busy
tf
tr
GND
Device
Figure 20. Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25°C , CL = 100pF
tr,tf [s]
Ibusy
300n
200n
290
3m
1.65
189
1.1
2m
Ibusy [A]
381
3.3
tr
100n
96
4.2
0.825
tf
1K
4.2
4.2
4.2
2K
3K
Rp(ohm)
4K
1m
Rp value guidance
Rp =
2.7V
VCC(Max.) - VOL(Max.)
IOL + ΣIL
=
8mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
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MCP MEMORY
KAB0xD100M - TxGP
Data Protection & Powerup sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever VccF is below about 1.3V. WP pin provides hardware protection and is recommended to be kept at
VIL during power-up and power-down and recovery time of minimum 1µs is required before internal circuit gets ready for any command sequences as shown in Figure 21. The two step command sequence for program/erase provides additional software protection.
≈
Figure 21. AC Waveforms for Power Transition
~ 2.5V
~ 2.5V
High
≈
VccF
WE
10µs
≈
WP
- 37 -
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KAB0xD100M - TxGP
NAND Flash Technical Notes
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The information regarding invalid block(s) is so called as the invalid block information. Devices ,regardless of having invalid block(s), have the
same quality level because all valid blocks have same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it’s bit line and common source line is isolated by a select transistor. The system design must be
able to mask out invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guaranteed to be
a valid block, does not require Error Correction.
Identifying Invalid Block(s)
All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid
block(s) status is defined by the 1st and 6th word in the spare area. Samsung makes sure that either 1st and 2nd page of every
invalid block has non-FFFFh data at the column address of 256 and 261. Since invalid block information is also erasable in most
cases, it is impossible to recover the information once it was erased. Therefore, system must be able to recognize the invalid block(s)
based on the original invalid block information and create invalid block table via the following suggested flow chart(Figure 22). Any
intentional erasure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Create (or update)
Invalid Block(s) Table
No
*
Check "FFFFh" ?
Check "FFFFh" at the column address
256 and 261of the 1st and 2nd page
in the block
Yes
No
Last Block ?
Yes
End
Figure 22. Flow chart to create invalid block table
- 38 -
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MCP MEMORY
KAB0xD100M - TxGP
NAND Flash Technical Notes
Error in write operation
Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for actual
data. The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. The said additional block failure
rate does not include those reclaimed blocks.
Failure Mode
Write
Read
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Program Failure
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
Single Bit Failure (1)
Verify ECC -> ECC Correction (2)
NOTE: 1. If Program/Erase Cycles is under 1K, Single Bilt Failure do not occure. Therefore there is no need to provide ECC.
2. ECC -> Error Correction Code -> Hamming Code etc.
Example) 1bit error correction and 2 bit error detection
Figure 24. Flash Program Flow Chart
If ECC is used or program/erase cycles are under 1K,
this verification operation is not needed.
Start
Write 00h
Write 80h
Write Address
Write Address
Wait for tR Time
Write Data
Write 10h
Verify Data
Read Status Register
No
*
Program Error
Yes
Program Completed
I/O 6 = 1 ?
or R/B = 1 ?
*
Program Error
Yes
No
No
*
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
I/O 0 = 0 ?
Yes
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MCP MEMORY
KAB0xD100M - TxGP
NAND Flash Technical Notes
Figure 24. Flash Erase Flow Chart
Start
Write 60h
Write Block Address
Write D0h
Read Status Register
DQ 6 = 1 ?
or R/B = 1 ?
*
Erase Error
No
Yes
No
DQ 0 = 0 ?
Yes
Erase Completed
*
: If erase operation results in an error, map out
the failing block and replace it with another block.
Figure 25. Block Replacement
1st
∼
(n-1)th
nth
(page)
1st
∼
(n-1)th
nth
(page)
{
Block A
2
Buffer memory of the controller.
{
Block B
1
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, Copy the 1st ~ (n-1)th data to the same location of the Block ’B’.
* Step4
Do not further erase Block ’A’ by creating a ’invalid Block’ table or other appropriate scheme.
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KAB0xD100M - TxGP
NAND Flash Technical Notes
Pointer Operation of NAND Flash
Samsung NAND Flash(x16) has two address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255word), and ’50h’ command sets the pointer to ’B’ area(256~263word). With these commands, the starting column address can be set to any of a whole page(0~263word). ’00h’ or ’50h’ is sustained until another address
pointer command is inputted. To program data starting from ’A’ or ’B’ area, ’00h’ or ’50h’ command must be inputted before ’80h’
command is written. A complete read operation prior to ’80h’ command is not necessary.
Table 18. Destination of the pointer
Command
Pointer position
Area
00h
50h
0 ~ 255 word
256 ~ 263 word
main array(A)
spare array(B)
"A" area
(00h plane)
"B" area
(50h plane)
256 Word
8 Word
"A"
"B"
Internal
Page Register
Pointer select
commnad
(00h, 50h)
Pointer
Figure 26. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’ area(0~255), and sustained
Address / Data input
00h
80h
Address / Data input
10h
00h
’A’,’B’ area can be programmed.
It depends on how many data are inputted.
80h
10h
’00h’ command can be omitted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’ area(256~263), and sustained
Address / Data input
50h
80h
Address / Data input
10h
50h
Only ’B’ area can be programmed.
80h
10h
’50h’ command can be omitted.
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KAB0xD100M - TxGP
NAND Flash Technical Notes
System Interface Using CE don’t-care.
For an easier system interface, CEF may be inactive during data-loading or sequential data-reading as shown below. The internal
264word page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CEF during the data-loading and reading would provide significant saving in power consumption.
Figure 27. Program Operation with CEF don’t-care.
CLE
CEF don’t-care
WE
≈
≈
CEF
ALE
DQx
80h
Start Add.(3Cycle)
tCS
Data Input
tCH
Data Input
10h
tCEA
CEF
CEF
tREA
RE
tWP
WE
I/O0~7
out
Figure 28. Read Operation with CEF don’t-care.
CLE
CEF don’t-care
≈
CEF
RE
ALE
tR
R/BF
WE
DQx
00h
Data Output(sequential)
Start Add.(3Cycle)
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MCP MEMORY
KAB0xD100M - TxGP
ABSOLUTE MAXIMUM RATINGS
Parameter
Vcc
Voltage on any pin relative to VSS
Symbol
Rating
VccR,VccF,VccU,VccQU
-0.2 to Vcc+0.3
RESET
Unit
-0.2 to 12.5V
VIN
-0.2 to 12.5V
Temperature Under Bias
TBIAS
-40 to + 125
Storage Temperature
TSTG
-65 to + 150
TA
-25 to + 85
WP/ACC
Other Balls
V
-0.2 to 3.6V
Operating Temperature
°C
NOTE:
1. Minimum DC voltage is -0.2V on input/output balls. During transitions, this level may undershoot to -1.0V for periods <20ns.
Maximum DC voltage on input/output balls is VCC+0.3V which, during transitions, may overshoot to VCC+1.0V for periods <20ns.
2. Minimum DC voltage is -0.2V on Reset and WP/ACC balls. During transitions, this level may undershoot to -1.0V for periods <20ns.
Maximum DC voltage on on Reset and WP/ACC balls is 12.5V which, during transitions, may overshoot to 14.0V for periods <20ns.
3. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to Vss, TA=-25 to 85°C)
Symbol
Min
Typ.
Max
Unit
Supply Voltage
Parameter
VccR,VccF,VccU,VccQU
2.7
2.9
3.1
V
Supply Voltage
VSS
0
0
0
V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter
Symbol
Test Conditions
Input LeaKAge Current
ILI
VIN=Vss to Vcc, Vcc=Vccmax
Output LeaKAge Current
ILO
VOUT=Vss to Vcc, Vcc=Vccmax, OE=VIH
Input Low Voltage Level
VIL
Min
Max
Unit
-10
10
µA
µA
-10
10
-0.3
0.5
Input High Voltage Level
VIH
2.2
Vcc+0.3
Output Low Voltage Level
VOL
IOL= 2.1mA, Vcc = Vccmin
-
0.4
Output High Voltage Level
VOH
IOH= -1.0mA, Vcc = Vccmin
2.3
-
- 43 -
V
Revision 1.11
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MCP MEMORY
KAB0xD100M - TxGP
DC AND OPERATING CHARACTERISTICS
Parameter
RESET Input Leakage Current
WP/ACC Input Leakage Current
Symbol
Test Conditions
Min
Typ
Max
Unit
-
35
µA
µA
ILIT
VccR=VccRmax, RESET=12.5V
-
ILIW
VccR=VccRmax, WP/ACC=12.5V
-
-
35
5MHz
-
14
20
1MHz
-
3
6
Active Read Current (1)
ICC1
CER=VIL, OE=VIH
Active Write Current (2)
ICC2
CER=VIL, OE=VIH
-
15
30
mA
Read While Program Current (3)
ICC3
CER=VIL, OE=VIH
-
25
50
mA
Read While Erase Current (3)
ICC4
CER=VIL, OE=VIH
-
25
50
mA
Program While Erase Suspend
Current
ICC5
CER=VIL, OE=VIH
-
15
35
mA
ACC Accelerated Program
Current
IACC
CER=VIL, OE=VIH
Standby Current
ISB1
NOR
Flash
mA
ACC Ball
-
5
10
mA
VccR Ball
-
15
30
mA
-
10
30
µA
-
10
30
µA
-
10
30
µA
VccR=VccRmax, CER=VccR± 0.3V,
RESET=VccR± 0.3V,
WP/ACC=VccR± 0.3V or Vss± 0.3V
NAND
Flash
VccR=VccRmax, RESET=Vss±0.3V,
Standby Curren During Reset
ISB2
Automatic Sleep Mode
ISB3
VIH=VccR ± 0.3V, VIL=Vss ± 0.3V,
OE=VIL, IOL=IOH=0
Voltage for WP/ACC Block
Temporarily Unprotect and
Program Acceleration (4)
VHH
VccR= 2.9V ± 0.2V
8.5
-
12.5
V
Voltage for Autoselect and
Block Protect (4)
VID
VccR= 2.9V ± 0.2V
8.5
-
12.5
V
1.8
-
2.5
V
WP/ACC=VccR± 0.3V or Vss± 0.3V
Low VccR Lock-out Voltage (5)
VLKO
Active Sequential Read Currnt
ICC1f
tRC=50ns,CEF=VIL, IOUT=0mA,
VccF=VccFmax
-
10
20
mA
Active Program Current
ICC2f
VccF=VccFmax
-
10
20
mA
Active Erase Current
ICC3f
VccF=VccFmax
-
10
20
mA
ISB2f
CEF=VccF, WP=0V/VccF
-
10
50
µA
ICC1u
Cycle time=1µs, 100% duty,
IIO=0mA, CSU≤0.2V, ZZ≥VccQU-0.2V,
VIN≤0.2V or VIN≥VccQU-0.2V
-
4
7
mA
ICC2u
Cycle time=min, 100% duty, IIO=0mA,
CSU=VIL, ZZ=VIH , VIN=VIL or VIH
-
30
35
mA
Stand_by Current(CMOS)
ISB2u
CSu≥VccQU-0.2V, ZZ≥VccQU-0.2V,
Other inputs =0~VccQU
-
80
100
µA
Deep Power Down
ISBD
ZZ≤0.2V, Other input =0~VccQU
-
5
10
µA
Stand_by Current(CMOS)
Operating Current
UtRAM
NOTES:
1. The ICC current listed includes both the DC operating current and the frequency dependent component(at 5 MHz).
The read current is typically 14 mA (@ VccR=2.9V , OE at VIH.)
2. ICC active during Internal Routine(program or erase) is in progress.
3. ICC active during Read while Write is in progress.
4. The high voltage ( VHH or VID ) must be used in the range of VccR = 2.9V ± 0.2V
5. Not 100% tested.
6. Typical values are measured at Vcc = 2.9V, Ta=25°C, not 100% tested.
- 44 -
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MCP MEMORY
KAB0xD100M - TxGP
Standby Mode State Machines(UtRAM)
CSU=VIL, UB or/and LB=VIL
ZZ=VIH
CSU=VIH
Initial State
(Wait 200µs)
Power On
Standby
Mode
CSU=VIH
ZZ=VIH
Active
ZZ=VIL
Read Operation Twice
ZZ=VIL
Deep Power
Down Mode
CSU=VIH, ZZ=VIH
Standby Mode Characteristic(UtRAM)
Power Mode
Memory Cell Data
Standby Current(µ
µA)
Wait Time(µ
µs)
Standby
Valid
100
0
Deep Power Down
Invaild
10
200
CAPACITANCE (TA = 25 °C, VCC = 2.9V, f = 1.0MHz)
Symbol
Test Condition
Min
Max
Unit
Input Capacitance
Item
CIN
VIN=0V
-
28
pF
Input/Output Capacitance
CIO
VIO=0V
-
30
pF
NOTE: Capacitance is periodically sampled and not 100% tested.
VALID BLOCK OF NAND FLASH MEMORY
Parameter
Symbol
Min
Typ.
Max
Unit
NVB
1004
-
1024
Blocks
Valid Block Number
NOTE:
1. The NAND Flash memory may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of
valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits.
Do not try to access these invalid blocks for program and erase.
Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
AC TEST CONDITION
Parameter
Value
Input Pulse Levels
0V to Vcc
Input Rise and Fall Times
5ns
Vcc/2 or VccQU/2
Input and Output Timing Levels
Output Load
CL = 30pF
NOTE: AC test inputs are driven at VccR, VccF or VccU for a logic "1" and 0V for a logic "0". Input timing begins, and output timing ends,
at VccR/2, VccF/2 or VccQU/2. Input rise and fall times (10% - 90%)<5ns. Worst case speed condition are when VccR = VccRmin,
VccF= VccFmin or VccQU = VccQUmin.
Device
Vcc
Vcc/2
Input & Output
Test Point
Vcc/2 or VccQU/2
CL
0V
Input Pulse and Test Point
* CL= 30pF including Scope
and Jig Capacitance
Output Load
- 45 -
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August 2003
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MCP MEMORY
KAB0xD100M - TxGP
NOR Flash AC CHARACTERISTICS
Write(Erase/Program)Operations
Alternate WE Controlled Write
Parameter
Symbol
Write Cycle Time (1)
tWC
Address Setup Time
70ns
80ns
Unit
Min
Max
Min
Max
70
-
80
-
ns
tAS
0
-
0
-
ns
tASO
55
-
55
-
ns
tAH
45
-
45
-
ns
tAHT
0
-
0
-
ns
Data Setup Time
tDS
35
-
35
-
ns
Data Hold Time
tDH
0
-
0
-
ns
Address Hold Time
Output Enable Setup Time (1)
Output Enable
Hold Time
tOES
0
-
0
-
ns
Read (1)
tOEH1
0
-
0
-
ns
Toggle and Data Polling (1)
tOEH2
10
-
10
-
ns
CER Setup Time
tCS
0
-
0
-
ns
CER Hold Time
tCH
0
-
0
-
ns
Write Pulse Width
tWP
35
-
35
-
ns
Write Pulse Width High
tWPH
25
-
25
-
ns
Programming Operation
Accelerated Programming Operation
Word
14(typ.)
14(typ.)
µs
9(typ.)
9(typ.)
µs
9(typ.)
9(typ.)
µs
7(typ.)
7(typ.)
µs
0.7(typ.)
0.7(typ.)
sec
tPGM
Byte
Word
tACCPGM
Byte
Block Erase Operation (2)
tBERS
VccR Set Up Time
tVCS
-
µs
0
-
ns
50
-
ns
20
-
µs
90
-
ns
-
500
-
ns
500
-
500
-
ns
-
20
-
20
µs
50
-
tRB
0
-
tRH
50
-
tRPD
20
-
tBUSY
90
-
tVID
500
RESET Pulse Width
tRP
RESET Low to R/BR High
tRRB
Write Recovery Time from R/BR
RESET High Time Before Read
RESET to Power Down Time
Program/Erase Valid to R/BR Delay
VID Rising and Falling Time
50
RESET Setup Time for Temporary Unprotect
tRSP
1
-
1
-
µs
RESET Low Setup Time
tRSTS
500
-
500
-
ns
RESET High to Address Valid
tRSTW
200
-
200
-
ns
Read Recovery Time Before Write
tGHWL
0
-
0
-
ns
CE High during toggling bit polling
tCEPH
20
-
20
-
ns
OE High during toggling bit polling
tOEPH
20
-
20
-
ns
NOTES: 1. Not 100% tested.
2. The duration of the Program or Erase operation varies and is calculated in the internal algorithms.
- 46 -
Revision 1.11
August 2003
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MCP MEMORY
KAB0xD100M - TxGP
NOR Flash AC CHARACTERISTICS
Write(Erase/Program)Operations
Alternate CER Controlled Writes
Parameter
Symbol
70ns
Min
80ns
Max
Min
Max
Unit
Write Cycle Time (1)
tWC
70
-
80
-
ns
Address Setup Time
tAS
0
-
0
-
ns
Address Hold Time
tAH
45
-
45
-
ns
Data Setup Time
tDS
35
-
35
-
ns
Data Hold Time
tDH
0
-
0
-
ns
Output Enable Setup Time (1)
tOES
0
-
0
-
ns
Read (1)
tOEH1
0
-
0
-
ns
Toggle and Data Polling (1)
tOEH2
10
-
10
-
ns
WE Setup Time
tWS
0
-
0
-
ns
WE Hold Time
tWH
0
-
0
-
ns
CER Pulse Width
tCP
35
-
35
-
ns
tCPH
25
-
25
-
Output Enable
Hold Time
CER Pulse Width High
Word
Programming Operation
tPGM
Byte
Accelerated Programming Operation
Word
14(typ.)
µs
9(typ.)
9(typ.)
µs
9(typ.)
9(typ.)
µs
tACCPGM
Byte
Block Erase Operation (2)
tBERS
BYTE Switching Low to Output HIGH-Z
tFLQZ
ns
14(typ.)
7(typ.)
7(typ.)
µs
0.7(typ.)
0.7(typ.)
sec
25
-
25
-
ns
NOTES: 1. Not 100% tested.
2.This does not include the preprogramming time.
ERASE AND PROGRAM PERFORMANCE
Limits
Parameter
Unit
Comments
Min
Typ
Max
Block Erase Time
-
0.7
15
sec
Chip Erase Time
-
98
-
sec
Word Programming Time
-
14
330
µs
Excludes system-level overhead
-
9
210
µs
Excludes system-level overhead
Word Mode
-
9
210
µs
Excludes system-level overhead
Byte Mode
-
7
150
µs
Excludes system-level overhead
Word Mode
-
59
177
sec
Byte Mode
-
75
225
sec
100,000
-
-
cycles
Byte Programming Time
Accelerated Byte/Word
Program Time
Chip Programming Time
Erase/Program Endurance
Excludes 00H programming
prior to erasure
Excludes system-level overhead
Minimum 100,000 cycles guaranteed
NOTES: 1. 25 °C, VccR = 2.9V 100,000 cycles, typical pattern.
2. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each byte.
In the preprogramming step of the Internal Erase Routine, all bytes are programmed to 00H before erasure.
- 47 -
Revision 1.11
August 2003
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MCP MEMORY
KAB0xD100M - TxGP
NOR Flash SWITCHING WAVEFORMS
Read Operations
tRC
Address Stable
Address
tAA
CER
tOE
tDF
OE
tOEH1
WE
tCE
Outputs
R/BR
tOH
HIGH-Z
HIGH-Z
Output Valid
HIGH
Parameter
Symbol
70ns
Min
80ns
Max
Min
Max
Unit
Read Cycle Time
tRC
70
-
80
-
ns
Address Access Time
tAA
-
70
-
80
ns
Chip Enable Access Time
tCE
-
70
-
80
ns
Output Enable Time
tOE
-
25
-
25
ns
CER & OE Disable Time (1)
tDF
-
16
-
16
ns
Output Hold Time from Address, CER or OE
OE Hold Time
tOH
0
-
0
-
ns
tOEH1
0
-
0
-
ns
NOTE: 1. Not 100% tested.
- 48 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NOR Flash SWITCHING WAVEFORMS
Hardware Reset/Read Operations
tRC
Address Stable
Address
tAA
CER
tRH
tRP
tRH
tCE
RESET
tOH
Outputs
High-Z
Output Valid
Parameter
Symbol
70ns
Min
80ns
Max
Min
Max
Unit
Read Cycle Time
tRC
70
-
80
-
ns
Address Access Time
tAA
-
70
-
80
ns
Chip Enable Access Time
tCE
-
70
-
80
ns
Output Hold Time from Address, CER or OE
tOH
0
-
0
-
ns
RESET Pulse Width
tRP
500
-
500
-
ns
RESET High Time Before Read
tRH
50
-
50
-
ns
- 49 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NOR Flash SWITCHING WAVEFORMS
Alternate WE Controlled Program Operations
tAS
PA
555H
Address
Data Polling
PA
tRC
tAH
CER
tOES
OE
tWC
tCH
tPGM
tWP
WE
tWPH
tCS
DATA
tOE
tDF
tDH
A0H
PD
Status
DOUT
tBUSY
tDS
tCE
tRB
tOH
R/BR
NOTES: 1. DQ7 is the output of the complement of the data written to the device.
2. DOUT is the output of the data written to the device.
3. PA : Program Address, PD : Program Data
4. The illustration shows the last two cycles of the program command sequence.
Parameter
Symbol
Write Cycle Time
tWC
70ns
80ns
Unit
Min
Max
Min
Max
70
-
80
-
ns
Address Setup Time
tAS
0
-
0
-
ns
Address Hold Time
tAH
45
-
45
-
ns
Data Setup Time
tDS
35
-
35
-
ns
Data Hold Time
tDH
0
-
0
-
ns
CER Setup Time
tCS
0
-
0
-
ns
CER Hold Time
tCH
0
-
0
-
ns
OE Setup Time
tOES
0
-
0
-
ns
Write Pulse Width
tWP
35
-
35
-
ns
Write Pulse Width High
tWPH
25
-
25
-
ns
Programming Operation
Accelerated Programming Operation
Word
tPGM
Byte
Word
14(typ.)
14(typ.)
us
9(typ.)
9(typ.)
us
tACCPGM
Byte
9(typ.)
9(typ.)
µs
7(typ.)
7(typ.)
µs
Read Cycle Time
tRC
70
-
80
-
ns
Chip Enable Access Time
tCE
-
70
-
80
ns
Output Enable Time
tOE
-
25
-
25
ns
CER & OE Disable Time
tDF
-
16
-
16
ns
Output Hold Time from Address, CER or OE
Program/Erase Valide to R/BR Delay
Recovery Time from R/BR
- 50 -
tOH
0
-
0
-
ns
tBUSY
90
-
90
-
ns
tRB
0
-
0
-
ns
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NOR Flash SWITCHING WAVEFORMS
Alternate CER Controlled Program Operations
tAS
555H
Address
Data Polling
PA
PA
tAH
WE
tOES
OE
tWC
tPGM
tCP
CER
tCPH
tWS
tDH
PD
A0H
DATA
DOUT
Status
tDS
tBUSY
tRB
R/BR
NOTES:
1. DQ7 is the output of the complement of the data written to the device.
2. DOUT is the output of the data written to the device.
3. PA : Program Address, PD : Program Data
4. The illustration shows the last two cycles of the program command sequence.
Parameter
Symbol
Write Cycle Time
tWC
70ns
80ns
Unit
Min
Max
Min
Max
70
-
80
-
ns
Address Setup Time
tAS
0
-
0
-
ns
Address Hold Time
tAH
45
-
45
-
ns
Data Setup Time
tDS
35
-
35
-
ns
Data Hold Time
tDH
0
-
0
-
ns
OE Setup Time
tOES
0
-
0
-
ns
WE Setup Time
tWS
0
-
0
-
ns
WE Hold Time
tWH
0
-
0
-
ns
CER Pulse Width
tCP
35
-
35
-
ns
CER Pulse Width High
tCPH
25
-
25
-
ns
Programming Operation
Accelerated Programming Operation
Word
tPGM
Byte
Word
14(typ.)
14(typ.)
µs
9(typ.)
9(typ.)
µs
9(typ.)
9(typ.)
µs
7(typ.)
7(typ.)
µs
tACCPGM
Byte
Program/Erase Valide to R/BR Delay
Recovery Time from R/BR
- 51 -
tBUSY
90
-
90
-
ns
tRB
0
-
0
-
ns
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NOR Flash SWITCHING WAVEFORMS
Word to Byte Timing Diagram for Read Operation
tCE
CER
OE
BYTE
tELFL
Data Output
(DQ0-DQ7)
DQ0-DQ7
DQ8-DQ14
Data Output
(DQ8-DQ14)
DQ15/A-1
Data Output
(DQ15)
Address Input (A-1)
tFLQZ
Byte to Word Timing Diagram for Read Operation
tCE
CER
OE
BYTE
tELFH
Data Output
(DQ0-DQ7)
DQ0-DQ7
Data Output
(DQ8-DQ14)
DQ8-DQ14
Address Input
(A-1)
DQ15/A-1
Data Output
(DQ15)
tFHQV
BYTE Timing Diagram for Write Operation
CER
The falling edge of the last WE signal
WE
BYTE
tSET
(tAS)
Parameter
tHOLD(tAH)
Symbol
Chip Enable Access Time
70ns
80ns
Min
Max
Min
Max
Unit
tCE
-
70
-
80
ns
tELFL/tELFH
-
5
-
5
ns
BYTE Switching Low to Output HIGH-Z
tFLQZ
-
25
-
25
ns
BYTE Switching High to Output Active
tFHQV
-
25
-
25
ns
CER to BYTE Switching Low or High
- 52 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NOR Flash SWITCHING WAVEFORMS
Chip/Block Erase Operations
tAS
555H
Address
555H for Chip Erase
2AAH
555H
555H
2AAH
BA
tAH
tRC
CER
tOES
OE
tWC
tWP
WE
tWPH
tCS
tDH
AAH
DATA
10H for Chip Erase
55H
AAH
80H
55H
30H
tDS
R/BR
VccR
tVCS
NOTE: BA : Block Address
Parameter
Symbol
70ns
Min
80ns
Max
Min
Max
Unit
Write Cycle Time
tWC
70
-
80
-
ns
Address Setup Time
tAS
0
-
0
-
ns
Address Hold Time
tAH
45
-
45
-
ns
Data Setup Time
tDS
35
-
35
-
ns
Data Hold Time
tDH
0
-
0
-
ns
OE Setup Time
tOES
0
-
0
-
ns
CER Setup Time
tCS
0
-
0
-
ns
Write Pulse Width
tWP
35
-
35
-
ns
Write Pulse Width High
tWPH
25
-
25
-
ns
Read Cycle Time
tRC
70
-
80
-
ns
VccR Set Up Time
tVCS
50
-
50
-
µs
- 53 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NOR Flash SWITCHING WAVEFORMS
Read While Write Operations
Read
Command
Read
Command
Read
Read
tRC
tWC
tRC
tWC
tRC
tRC
DA1
DA2
(PA)
Address
DA2
(555H)
DA1
tAS
DA2
(PA)
DA1
tAH
tAS
tAA
tAHT
tCE
CER
tOE
tCEPH
OE
tDF
tOES
tOEH2
tWP
WE
tDF
tDH
tDS
Valid
Output
DQ
Valid
Input
Valid
Output
Valid
Input
(A0H)
Valid
Output
Status
(PD)
NOTE: This is an example in the program-case of the Read While Write function.
DA1 : Address of Bank1, DA2 : Address of Bank 2
PA = Program Address at one bank , RA = Read Address at the other bank, PD = Program Data In , RD = Read Data Out
Parameter
Symbol
70ns
80ns
Min
Max
Min
Max
Unit
Write Cycle Time
tWC
70
-
80
-
ns
Write Pulse Width
tWP
35
-
35
-
ns
Write Pulse Width High
tWPH
25
-
25
-
ns
Address Setup Time
tAS
0
-
0
-
ns
Address Hold Time
tAH
45
-
45
-
ns
Data Setup Time
tDS
35
-
35
-
ns
Data Hold Time
tDH
0
-
0
-
ns
Read Cycle Time
tRC
70
-
80
-
ns
Chip Enable Access Time
tCE
-
70
-
80
ns
Address Access Time
tAA
-
70
-
80
ns
Output Enable Access Time
tOE
-
25
-
25
ns
OE Setup Time
tOES
0
-
0
-
ns
OE Hold Time
tOEH2
10
-
10
-
ns
CER & OE Disable Time
tDF
-
16
-
16
ns
Address Hold Time
tAHT
0
-
0
-
ns
tCEPH
20
-
20
-
ns
CER High during toggle bit polling
- 54 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NOR Flash SWITCHING WAVEFORMS
Data Polling During Internal Routine Operation
CER
tDF
tOE
OE
tOEH2
WE
tCE
tOH
DQ7
Data In
HIGH-Z
*DQ7 = Valid Data
DQ7
tPGM or tBERS
DQ0-DQ6
Data In
HIGH-Z
Valid Data
Status Data
NOTE: *DQ7=Vaild Data (The device has completed the internal operation).
R/BR Timing Diagram During Program/Erase Operation
CER
The rising edge of the last WE signal
WE
Entire progrming
or erase operation
R/BR
tBUSY
Parameter
Symbol
Program/Erase Valid to R/BR Delay
70ns
Min
80ns
Max
Min
Max
Unit
tBUSY
90
-
90
-
ns
Chip Enable Access Time
tCE
-
70
-
80
ns
Output Enable Time
tOE
-
25
-
25
ns
CER & OE Disable Time
tDF
-
16
-
16
ns
Output Hold Time from Address, CER or OE
tOH
0
-
0
-
ns
tOEH2
10
-
10
-
ns
OE Hold Time
- 55 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NOR Flash SWITCHING WAVEFORMS
Toggle Bit During Internal Routine Operation
tAS
tAHT
Address*
tAHT
tASO
CER
tOEH2
tCEPH
WE
tOEPH
OE
tDH
tOE
Status
Data
Data In
DQ6/DQ2
Status
Data
Status
Data
Array Data Out
R/BR
NOTE: Address for the write operation must include a bank address (A20~A21) where the data is written.
Enter
Embedded
Erasing
Erase
Suspend
Erase
WE
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Toggle
DQ2 and DQ6
with OE or CER
NOTE: DQ2 is read from the erase-suspended block.
Parameter
Symbol
Output Enable Access Time
OE Hold Time
70ns
80ns
Min
Max
tOE
-
tOEH2
10
Unit
Min
Max
25
-
25
ns
-
10
-
ns
Address Hold Time
tAHT
0
-
0
-
ns
Address Setup
tASO
55
-
55
-
ns
Address Setup Time
tAS
0
-
0
-
ns
Data Hold Time
tDH
0
-
0
-
ns
CER High during toggle bit polling
tCEPH
20
-
20
-
ns
OE High during toggle bit polling
tOEPH
20
-
20
-
ns
- 56 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NOR Flash SWITCHING WAVEFORMS
RESET Timing Diagram
R/BR
High
CER or OE
tRH
RESET
tRP
tREADY
Reset Timings NOT during Internal Routine
tREADY
R/BR
tRB
CER or OE
tRP
RESET
Reset Timings during Internal Routine
Power-up and RESET Timing Diagram
tRSTS
RESET
Vcc
Address
DATA
tAA
Parameter
Symbol
RESET Pulse Width
70ns
80ns
Min
Max
Min
Max
Unit
tRP
500
-
500
-
ns
RESET Low to Valid Data
(During Internal Routine)
tREADY
-
20
-
20
µs
RESET Low to Valid Data
(Not during Internal Routine)
tREADY
-
500
-
500
ns
tRH
50
-
50
-
ns
RESET High Time Before Read
R/BR Recovery Time
tRB
0
-
0
-
ns
RESET High to Address Valid
tRSTW
200
-
200
-
ns
RESET Low Set-up Time
tRSTS
500
-
500
-
ns
- 57 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NOR Flash SWITCHING WAVEFORMS
Block Group Protect & Unprotect Operations
VID
RESET
Vss,VIL,
or VIH
Vss,VIL,
or VIH
BGA,A6
A1,A0
Valid
Valid
Block Group Protect / Unprotect
DATA
60H
Valid
Verify
40H
60H
Status*
Block Group Protect:150µs
Block Group UnProtect:15ms
1µs
CER
WE
tRB
OE
tBUSY
R/BR
NOTES: Block Group Protect (A6=VIL , A1=VIH , A0=VIL) , Status=01H
Block Group Unprotect (A6=VIH , A1=VIH, A0=VIL) , Status=00H
BGA = Block Group Address (A12 ~ A21)
Temporary Block Group Unprotect
VID
RESET
Vss,VIL,
or VIH
Vss,VIL,
or VIH
CER
WE
tVID
tRSP
Program or Erase Command Sequence
tRRB
tVID
R/BR
- 58 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NAND Flash Program/Erase Characteristics(VccF=2.7~3.1V, TA=-25 to 85°C)
Parameter
Program Time
Number of Partial Program Cycles
in the Same Page
Symbol
Min
Typ
Max
tPROG
-
200
500
µs
-
-
2
cycles
-
-
3
cycles
-
2
3
ms
Main Array
Nop
Spare Array
Block Erase Time
tBERS
Unit
NAND Flash AC Timing Characteristics for Command/Address/Data Input
(VccF=2.7~3.1V, TA=-25 to 85°C)
Parameter
Symbol
Min
Max
Unit
CLE Set-up Time
tCLS
0
-
ns
CLE Hold Time
tCLH
10
-
ns
CEF Setup Time
tCS
0
-
ns
CEF Hold Time
tCH
10
-
ns
WE Pulse Width
tWP
25
-
ns
ALE Setup Time
tALS
0
-
ns
ALE Hold Time
tALH
10
-
ns
Data Setup Time
tDS
20
-
ns
Data Hold Time
tDH
10
-
ns
Write Cycle Time
tWC
45
-
ns
WE High Hold Time
tWH
15
-
ns
NAND Flash AC Characteristics for Operation(VccF=2.7~3.1V, TA=-25 to 85°C)
Symbol
Min
Max
Unit
Data Transfer from Cell to Register
Parameter
tR
-
10
µs
10
-
ns
ALE to RE Delay
tAR
CEF Access Time
tCEA
-
45
ns
Ready to RE Low
tRR
20
-
ns
RE Pulse Width
tRP
25
-
ns
WE High to Busy
tWB
-
100
ns
Read Cycle Time
tRC
50
-
ns
RE Access Time
tREA
-
30
ns
RE High to Output Hi-Z
tRHZ
-
30
ns
CEF High to Output Hi-Z
tCHZ
-
20
ns
RE or CEF High to Output Hold
tOH
15
-
ns
RE High Hold Time
tREH
15
-
ns
Output Hi-Z to RE Low
tIR
0
-
ns
WE High to RE Low
tWHR
60
-
ns
Device Resetting Time(Read/Program/Erase)
tRST
-
5/10/500(1)
µs
NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us
- 59 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NAND Flash Command Latch Cycle
CLE
tCLS
tCLH
tCS
tCH
CEF
tWP
WE
tALH
tALS
ALE
tDH
tDS
Command
DQx
NAND Flash Address Latch Cycle
tCLS
CLE
tCS
tWC
tWC
CEF
tWP
tWP
tWP
WE
tWH
tALH tALS
tWH
tALH tALS
tALS
tALH
ALE
tDS
DQx
tDH
tDS
tDH
A9~A16
A0~A7
- 60 -
tDS
tDH
A17~A23
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NAND Flash Input Data Latch Cycle
tCLH
CLE
tCH
CEF
tWC
tALS
tWP
≈
ALE
tWP
tWP
WE
tWH
tDH
tDS
tDH
tDS
tDH
≈
tDS
DQx
DIN n
DIN 1
≈
DIN 0
NAND Flash Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
≈
CEF
tRP
≈
tREA
tREA
tCHZ*
tOH
tREH
tREA
RE
tRHZ*
tRHZ*
Dout
DQx
Dout
≈
tOH
Dout
≈
tRR
R/BF
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
- 61 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NAND Flash Status Read Cycle
tCLS
CLE
tCLS
tCLH
tCS
CEF
tCH
tWP
WE
tCEA
tCHZ*
tOH
tWHR
RE
tDH
tDS
DQx
tIR
tRHZ*
tOH
tREA
Status Output
70h
NAND FLASH READ1 OPERATION(READ ONE PAGE)
CLE
CEF
tCHZ
tWC
tOH
WE
tWB
tAR
ALE
tRHZ
tOH
tRC
tR
≈
RE
DQx
00h
A 0 ~ A7
A9 ~ A16
Column
Address
R/BF
A17 ~ A23
Dout N
Page(Row)
Address
Dout N+1
Dout N+2
Dout N+3
≈ ≈
tRR
Dout 264
Busy
- 62 -
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NAND FLASH READ2 OPERATION(READ ONE PAGE)
CLE
CEF
WE
tR
tWB
tAR
ALE
≈
tRR
A 0 ~ A7
50h
Dout
256+M
A9 ~ A16 A17 ~ A23
R/BF
M Address
Dout
256+M+1
≈
DQx
≈
RE
Dout 264
Selected
Row
A0 ~ A2 : Valid Address
A3 ~ A7 : "L"
256
8
Start
address M
NAND FLASH PAGE PROGRAM OPERATION
CLE
CEF
tWC
tWC
tWC
WE
tWB
tPROG
ALE
DQx
80h
A0 ~ A7 A9 ~ A16 A17 ~ A23
Sequential Data Column
Input Command Address
Page(Row)
Address
≈ ≈
RE
Din
Din
Din
10h
264
N
N+1
1 up to 264 Word Data
Program
Serial Input
Command
≈
R/BF
70h
- 63 -
DQ0
Read Status
Command
DQ0=0 Successful Program
DQ0=1 Error in Program
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
NAND FLASH BLOCK ERASE OPERATION(ERASE ONE BLOCK)
CLE
CEF
tWC
WE
tBERS
tWB
ALE
RE
DQx
60h
A9 ~ A16 A17 ~ A23
DOh
70h
DQ 0
Busy
R/BF
Auto Block Erase
Setup Command
≈
Page(Row)
Address
Erase Command
Read Status
Command
DQ0=0 Successful Erase
DQ0=1 Error in Erase
NAND FLASH MANUFACTURE & DEVICE ID READ OPERATION
CLE
CEF
WE
ALE
tAR
RE
tREA
DQx
90h
00h
Read ID Command
Address 1st Cycle
ECh
Maker Code
- 64 -
73h
Device Code
Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
UtRAM AC CHARACTERISTICS(VccU=2.7~3.1V, TA=-25 to 85°C)
Speed Bins
Parameter List
Symbol
Read Cycle Time
Read
Write
tRC
Units
85ns1)
Min
Max
85
-
ns
Address Access Time
tAA
-
85
ns
Chip Select to Output
tCO
-
85
ns
Output Enable to Valid Output
tOE
-
40
ns
UB, LB Access Time
tBA
-
85
ns
Chip Select to Low-Z Output
tLZ
10
-
ns
UB, LB Enable to Low-Z Output
tBLZ
10
-
ns
Output Enable to Low-Z Output
tOLZ
5
-
ns
Chip Disable to High-Z Output
tHZ
0
25
ns
UB, LB Disable to High-Z Output
tBHZ
0
25
ns
Output Disable to High-Z Output
tOHZ
0
25
ns
Output Hold from Address Change
tOH
5
-
ns
Write Cycle Time
tWC
85
-
ns
Chip Select to End of Write
tCW
70
-
ns
Address Set-up Time
tAS
0
-
ns
Address Valid to End of Write
tAW
70
-
ns
UB, LB Valid to End of Write
tBW
70
-
ns
Write Pulse Width
tWP
60
-
ns
Write Recovery Time
tWR
0
-
ns
Write to Output High-Z
tWHZ
0
25
ns
Data to Write Time Overlap
tDW
35
-
ns
Data Hold from Write Time
tDH
0
-
ns
End Write to Output Low-Z
tOW
5
-
ns
1. The limitation in continuous write operation is up to 50 times. If you want to write continuously over 50 times, please refer to the technical note.
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MCP MEMORY
KAB0xD100M - TxGP
UtRAM TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)(Address Controlled, CSU=OE=VIL, ZZ=WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2)(ZZ=WE=VIH)
tRC1
Address
tAA
tOH
tRC2
tCO
CSU
tHZ
tBA
UB, LB
tBHZ
tOE
OE
tOLZ
tBLZ
Data out
High-Z
tOHZ
tLZ
Data Valid
(READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
3. The minimum read cycle(tRC) is determined later one of the tRC1 and tRC2.
4. tOE(max) is met only when OE becomes enable after tAA(max).
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MCP MEMORY
KAB0xD100M - TxGP
TIMING WAVEFORM OF WRITE CYCLE(1)(WE Controlled, ZZ=VIH)
tWC
Address
tWR(4)
tCW(2)
CSU
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
Data in
tDW
High-Z
tDH
tWHZ
Data out
High-Z
Data Valid
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2)(CSU Controlled, ZZ=VIH)
tWC
Address
CSU
tAS(3)
UB, LB
tCW(2)
tAW
tBW
tWR(4)
tWP(1)
WE
tDW
Data Valid
Data in
Data out
tDH
High-Z
High-Z
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Revision 1.11
August 2003
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MCP MEMORY
KAB0xD100M - TxGP
TIMING WAVEFORM OF WRITE CYCLE(3)(UB, LB Controlled, ZZ=VIH)
tWC
Address
tWR(4)
tCW(2)
CSU
tAW
tBW
UB, LB
tAS(3)
tWP(1)
WE
tDW
tDH
Data Valid
Data in
High-Z
Data out
High-Z
(WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CSU and low WE. A write begins when CSU goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CSU goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CSU going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CSU or WE going high.
TIMING WAVEFORM OF DEEP POWER DOWN MODE
Read Operation Twice or Stay High during 300µs
200µs
≈
0.5µs
ZZ
Normal Operation
Wake up
Suspend
Normal Operation
≈
MODE
Deep Power Down Mode
CSU
(DEEP POWER DOWN MODE)
1. When you toggle ZZ pin low, the device gets into the Deep Power Down mode after 0.5µs suspend period.
2. To return to normal operation, the device needs Wake Up period.
3. Wake Up sequence is just the same as Power up sequences.
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Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
TIMING WAVEFORM OF POWER UP(1)
Read Operation Twice
200µs
≈
VccU(Min)
VccU
ZZ
CSU
(POWER UP(1))
1. After VccU reaches VccU(Min.) following power application, wait 200µs with CSU high and then toggle CSU low and commit Read Operation at least twice. Then you get into the normal operation.
2. Read operation should be executed by toggling CSU pin low.
3. The read operation must satisfy the specified tRC.
4. ZZ pin should be kept high during whole power up sequence.
TIMING WAVEFORM OF POWER UP(2)(No Dummy Cycle)
200µs
300µs
≈
≈
VccU(Min)
VccU
ZZ
CSU
(POWER UP(2))
1. After VccU reaches VccU(Min.) following power application, wait 200µs and wait another 300µs with CSU high if you don’t want to commit dummy read cycle. After total 500µs wait, toggle CSU low, then you get into the normal mode.
2. ZZ pin should be kept high during whole power up sequence.
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Revision 1.11
August 2003
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MCP MEMORY
KAB0xD100M - TxGP
TECHNICAL
NOTE
UtRAM USAGE AND TIMING
INTRODUCTION
DESIGN ACHIEVES SRAM SPECIFIC
OPERATIONS
UtRAM is based on single-transistor DRAM cells. As with any
other DRAM, the data in these cells must be periodically
refreshed to prevent data loss. What makes the UtRAM unique
is that it offers a true SRAM style interface that hides all refresh
operations from the memory controller.
The UtRAM was designed to work just like an SRAM - without
any waits or other overhead for precharging or refreshing its
internal DRAM cells. SAMSUNG Electronics(SAMSUNG) hides
these operations inside with advanced design technology those are not to be seen from outside. Precharging takes place
during every access, overlapped between the end of the cycle
and the decoding portion of the next cycle.
Hiding refresh is more difficult. Every row in every block must
be refreshed at least once during the refresh interval to prevent
data loss. SAMSUNG provides an internal refresh controller for
devices. When all accesses within refresh interval are directed
to one macro-cell, as can happen in signal processing applications, a more sophisticated approach is required to hide
refresh. The pseudo SRAM is sometimes used on these applications, which requires a memory controller that can hold off
accesses when a refresh operation is needed. SAMSUNG’s
unique qualitative advantage over these parts(in addition to
quantitative improvements in access speed and power consumption) is that the UtRAM never need to hold off accesses,
and indeed it has no hold off signal. The circuitry that gives
SAMSUNG this advantage is fairly simple but has not previously been disclosed.
START WITH A DRAM TECHNOLOGY
The key point of UtRAM is its high speed and low power. This
high speed comes from the use of many small blocks such as
32Kbits each to create UtRAM arrays. The small blocks have
short word lines thus with little capacitance eliminating a major
factor of operating current dissipation in conventional DRAM
blocks.
Each independent macro-cell on a UtRAM device consists of a
number of these blocks. Each chip has one or more macro.
The address decoding logic is also fast. UtRAM performs a
complete read operation in every tRC, but UtRAM needs power
up sequence like DRAM.
Power Up Sequence and Diagram
1. Apply power.
2. Maintain stable power for a minium 200µs with CSU=high.
3. Issue read operation at least 2 times.
CSU=VIH
Power On
Initial State
(Wait 200µs)
CSU=VIL, UB or/and LB=VIL
ZZ=VIH
Active
Read Operation(2 times)
Figure 29.
AVOID TIMING
Following figures show you an abnormal timing which is not
supported on UtRAM and its solution.
If your system has a timing which sustains invalid states over
4µs at read mode like Figure 29, there are some guide lines for
proper operation of UtRAM.
When your system has multiple invalid address signals shorter
than tRC on the timing shown in Figure 1, UtRAM needs a normal read timing(tRC) during that cycle(Figure 30) or needs to
toggle CSU once to ’high’ for about ’tRC’(Figure 31).
Over 4µs
CSU
WE
Less than tRC
Address
Put on read operation every 4µs
Figure 30.
Over 4µs
CSU
WE
tRC
Address
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August 2003
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MCP MEMORY
KAB0xD100M - TxGP
Figure 31.
toggle CSU to high every 4µs
Over 4µs
tRC
CSU
WE
Address
Write operation has similar restriction to Read operation. If your
system has a timing which sustains invalid states over 4µs at
write mode and has continuous write signals with length of Min.
tWC over 4µs like Figure 32, you must toggle WE once to high
and make it stay high at least for tRC every 4µs or toggle CSU
once to high for about tRC.
Figure 32.
Over 4µs
CSU
tWP
WE
Address
tWC
Figure 33.
toggle WE to high and make it stay high at least for tRC every 4µs
Over 4µs
CSU
tWP
WE
Address
tWC
tRC
Figure 34.
toggle CSU to high every 4µs
Over 4µs
CSU
tWP
tRC
WE
Address
tWC
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Revision 1.11
August 2003
SEC Only
MCP MEMORY
KAB0xD100M - TxGP
PACKAGE DIMENSION
80-Ball Tape Ball Grid Array Package (measured in millimeters)
Top View
Side View
Bottom View
#A1 INDEX MARK(OPTIONAL)
8.00±0.10
8.00±0.10
0.08 MAX
A
0.80x7=5.60
(Datum A)
8 7 6 5 4
B
3 2 1
A
B
#A1
0.80
D 0.80
E
F
G
H
4.80
J
12.00±0.10
0.45±0.05
12.00±0.10
12.00±0.10
(Datum B)
0.80x12=9.60
C
K
L
M
N
0.32±0.05
2.80
1.30±0.10
80-∅ 0.45±0.05
∅ 0.20 M A B
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Revision 1.11
August 2003