FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 INTRODUCTION 24-QFN-3.5×4.5 The S1M8831A/33 is a Fractional-N frequency synthesizer with integrated prescalers, designed for RF operation up to 1.2GHz/K-PCS and for IF operation up to 520MHz. The fractional-N synthesizer allows fast-locking, low phase noise phase-locked loops to be built easily, thus having rapid channel switching and reducing standby time for extended battery life. The S1M8831A/33 based on ∑ - ∆ fractional-N techniques solves the fractional spur problems in other fractional-N synthesizers based on charge pump compensation. The synthesizer also has an additional feature that the PCS/CDMA channel frequency in steps of 10kHz can be accurately programmed. The S1M8831A/33 contains dual-modulus prescalers. The S1M8831A RF synthesizer adopts an 8/9 prescaler (16/17 for the S1M8833) and the IF synthesizer adopts an 8/9 prescaler. Phase detector gain is user-programmable for maximum flexibility to address IS-95 CDMA and IMT2000. Various program-controlled power down options as well as low supply voltage help the design of wireless cell phones having minimum power consumption. Using the Samsung's proprietary digital phase-locked-loop technique, the S1M8831A/33 has a linear phase detector characteristic and can be used for very stable, low noise PLLs. Supply voltage can range from 2.7V to 4.0V. The S1M8831A/33 is available in a 24-QFN package. FEATURES • High operating frequency dual synthesizer — S1M8831A: 0.71 to 1.2GHz(RF)/ 45 to 520MHz(IF) — S1M8833: 1.6 to 1.65GHz(RF)/ 45 to 520MHz(IF) • Operating voltage range: 2.7 to 4.0V • Low current consumption (S1M8831A: 5.0mA, S1M8833: 7.0mA) • Selectable power saving mode (ICC = 1uA typical @ 3V) • Dual-modulus prescaler and Fractional-N/Integer-N: — S1M8831A — S1M8833 — S1M8831A/33 (RF) 8/9 (RF) 16/17 (IF) 8/9 Fractional-N Fractional-N Integer-N • Excellent in-band phase noise ( – 85dBc/Hz @ PCS, -90dBc/Hz @CDMA) Improved fractional spurious performance ( < 80dBc) • Frequency resolution (= 10kHz/64 @ fref = 9.84MHz) • Fast channel switching time: < 500us • Programmable charge pump output current: from 50uA to 800uA in 50uA steps • Programmability via on-chip serial bus interface 1 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL APPLICATIONS • High-rate data-service cellular telephones (for CDMA): S1M8831A, S1M8833 • High-rate data-service portable wireless communications (for Korean-PCS): S1M8833 • Other wireless communications systems ORDERING INFORMATION Device Package Operating Temperature +S1M8831A01-G0T0 24-QFN-3.5×4.5 -40 to +85C +S1M8833X01-G0T0 + : New Product 2 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 BLOCK DIAGRAM VDDRF 1 VPRF 2 OUT0 OUT1 VDDIF 24 23 22 RF LD RF Charge Pump CPORF 3 DGND 4 foLD Data Out Multiplexer RF Phase Detector IF Phase Detector RF Prescaler 5 finRF 6 21 VPIF 20 CPOIF 19 DGND 18 finIF 17 finIF 16 GNDIF 15 LE 14 DATA 13 CLOCK IF Charge Pump IF Prescaler +- - + RF Programmable Counter Prescaler Control finRF IF LD IF Programmable Counter RF N-Latch Prescaler Control IF N-Latch 2-Bit Control GNDRF 7 OSCx 8 OSCin 9 Frac-N Latch & Σ−∆ Modulator 24-Bit Shift Register RF R-Latch IF R-Latch RF Reference Counter IF Reference Counter 10 11 12 foLD RF_EN IF_EN 3 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL PIN CONFIGURATION OUT0 OUT1 VDDIF 24 23 22 VDDRF 1 21 VPIF VPRF 2 20 CPOIF CPORF 3 19 DGND DGND 4 18 finIF finRF 5 17 finIF finRF 6 16 GNDIF GNDRF 7 15 LE OSCx 8 14 DATA OSCin 9 13 CLCOK S1M8831A/33 10 foLD 11 RF_EN 24-QFN 4 12 IF_EN FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 PIN DESCRIPTION Pin No. Symbol I/O Description 1 VDDRF – RF PLL power supply(2.7V to 4.0V). Must be equal to VDDIF. 2 VPRF – Power supply for RF charge pump. Must be ≥ VDDRF and VDDIF. 3 CPoRF O RF charge pump output. Connected to an external loop filter. 4 DGND – Ground for RF PLL digital circuitry. 5 f inRF I RF prescaler input. Small signal input from the external VCO. 6 f inRF I RF prescaler complementary input. For a single-ended output RF VCO, a bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. 7 GNDRF – Ground for RF PLL analog circuitry. 8 OSCx I RF R counter input (IF_N[22]=0) or not-use (IF_N[22]=1) which can be configured depending on the state of the program bit IF_N[22]. 9 OSCin I Oscillator input to drive both the IF and RF R counter inputs (IF_N[22]=1) or only the IF R counter (IF_N[22]=0) which can be configured depending on the state of the program bit IF_N[22]. 10 foLD O Multiplexed output of N or R divider and RF/IF lock detect. 11 RF_EN I RF PLL Enable (enable when high, power down when low). Controls the RF PLL to power down directly, not depending on a program control. Also sets the charge pump output to be in TRI-STATE when LOW. Powers up when HIGH depends on the state of RF_CTL_WORD. 12 IF_EN I IF PLL Enable(enable when high, power-down when low). Controls the IF PLL to power down directly. The same as RF_EN except that power-up depends on the state of IF_CTL_WORD. 13 CLOCK I CMOS clock input. Data for the various counters is clocked into the 24-bit shift register on the rising edge. 14 DATA I Binary serial data input. Data entered MSB (Most Significant Bit) first. 15 LE I Load enable when LE goes HIGH. High impedance CMOS input. 16 GNDIF – Ground for IF analog circuitry. 17 f inIF I IF Prescaler complementary input. For a single-ended output IF VCO, a bypass capacitor should be placed as close as possible to this pin. 18 finIF I IF prescaler input. Small signal input from the VCO. 19 DGND – Ground for IF PLL digital circuitry. 20 CPoIF O IF charge pump output. Connected to an external loop filter. 5 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL PIN DESCRIPTION (Continued) 6 Pin No. Pin Name I/O Descriptions 21 VPIF – Power supply for IF charge pump. Must be ≥ VDDRF and VDDIF. 22 VDDIF – IF PLL power supply (2.7V to 4.0V). Must be equal to VDDRF. 23 OUT1 O Programmable CMOS output. Level of the output is controlled by RF_N[19] bit. 24 OUT0 O Programmable CMOS output. Level of the output is controlled by RF_N[18] bit. In the speedy lock mode, the OUT0 and OUT1 pins can be utilized as synchronous switches between active low and tri-state. FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 EQUIVALENT CIRCUIT DIAGRAM CLOCK, DATA, LE foLD OSCin, OSCx CPORF, CPOIF finRF, finRF, finIF, finIF finRF, finIF finRF, finIF Vbias 7 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Characteristics Symbol Value Unit VDD 0.0 to 4.0 V Voltage on any pin with GND = 0 volts VI -0.3 to VDD + 0.3 V Power dissipation PD 600 mW Operating temperature Ta -40 to +85 °C TSTG -65 to +150 °C Pin No. ESD Level Unit Human body model All < ± 2000 V Machine model All < ± 300 V Charge device model All < ± 800 V Power supply voltage Storage temperature ELECTROSTATIC CHARACTERISTICS Characteristics NOTE: These devices are ESD sensitive. These devices must be handled in an ESD protected environment. 8 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 ELECTRICAL CHARACTERISTICS (VDD = 3.0V, VP = 3.0V, Ta = 25°C, unless otherwise specified.) Characteristic Power supply voltage Power supply current S1M8831A RF+IF Symbol Min. Typ. Max. Unit VDD 2.7 3.0 4.0 V VP VDD 3.0 4.0 IDD Test Conditions Fractional-N mode (fosc = 19.68MHz, 5.0 S1M8833 RF+IF RF R = 2) 7.0 S1M8831A RF+IF Quiescent State 3.5 S1M8833 RF+IF 5.5 IF only 1.5 Power down current IPWDN VDD = 3.0V 1 mA 10 µA Digital Inputs: CLOCK, DATA and LE High level input voltage VIH VDD = 2.7V to 4.0V Low level input voltage VIL VDD = 2.7V to 4.0V High level input current IIH VIH = VDD = 4.0V Low level input current IIL VIL = 0V, VDD = 4.0V 0.7VDD V 0.3VDD V -1.0 +1.0 µA -1.0 +1.0 µA +100 µA Reference Oscillator Input: OSCin IIHR VIH = VDD = 4.0V IILR VIL = 0V, VDD = 4.0V High level output voltage VOH Iout = -500µA Low level output voltage VOL Iout = +500µA Input current -100 µA VDD-0.4 V Digital Output: foLD 0.4 V 9 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL ELECTRICAL CHARACTERISTICS (Continued) (VDD = 3.0V, VP = 3.0V, Ta = 25°C, unless otherwise specified.) Characteristic Symbol Test Conditions Min. Typ. Max. Unit Operating Frequency, Input Sensitivity (Programmable Divider, PFD) RF operating frequency S1M8833 f inRF S1M8831A IF operating frequency f inIF Reference oscillator input frequency OSCin Phase detector operating frequency f PD RF input sensitivity PfinRF IF input sensitivity PfinIF Reference oscillator input sensitivity VOSCin Fractional-N mode (fosc = 19.68MHz, RF R = 2) 1.6 1.65 GHz Fractional-N mode (fosc = 19.68MHz, RF R = 2) 0.71 1.2 GHz 45 520 MHz 2 40 MHz 10 MHz VDD = 3.0 VDD = 3.0V -15 0 dBm VDD = 4.0V -10 0 dBm VDD = 2.7V to 4.0V -10 0 dBm 0.5 VDD VPP Charge Pump Outputs: CPoRF, CPoIF RF charge pump output current ICPRFSOURCE_min ICPRFSIINK_min ICPRFSOURCE_ VCP = VP/2, RF_CP_WORD=0000 -50 uA VCP = VP/2, RF_CP_WORD=0000 +50 uA VCP = VP/2, RF_CP_WORD=1111 -800 uA VCP = VP/2, RF_CP_WORD=1111 +800 uA VCP = VP/2, CP_GAIN_8=0 -100 uA VCP = VP/2, CP_GAIN_8=0 +100 uA VCP = VP/2, CP_GAIN_8=1 -800 uA VCP = VP/2, CP_GAIN_8=1 +800 uA max ICPRFSIINK_max IF charge pump output current ICPRFSOURCE_min ICPRFSIINK_min ICPRFSOURCE_max ICPRFSIINK_max 10 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 ELECTRICAL CHARACTERISTICS (Continued) (VDD = 3.0V, VP = 3.0V, Ta = 25°C, unless otherwise specified.) Characteristic Symbol Charge pump leakage current ICPL Test Conditions 0.5V ≤ VCP ≤ VP0.5V Min. Typ. -2.5 Max. Unit +2.5 nA Sink vs. Source mismatch ICP-SIINK vs ICP-SOURCE VCP = VP/2 3 10 % Output current magnitude variation vs. Voltage ICP vs VCP 0.5V ≤ VCP ≤ VP-0.5V 10 15 % ICP vs TA VCP = VP/2 10 Output current vs. Temperature % Serial Data Control CLOCK frequency f CLOCK 10 MHz CLOCK pulse width high tCWH 50 ns CLOCK pulse width low tCWL 50 ns DATA set up time to CLOCK rising edge tDS 50 ns DATA hold time after CLOCK rising edge tDH 10 ns LE pulse width tLEW 50 ns CLOCK rising edge to LE rising edge tCLE 50 ns 11 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL FUNCTIONAL DESCRIPTION finRF finRF + - RF Prescaler RF N Counter RF Phase Detector Serial Data Control OSCx RF R Counter OSCin IF R Counter finIF finIF + - IF Prescaler IF N Counter CPoRF CMOS Output MUX OUT0 RF LD ∑ -∆ Modulator CLOCK DATA LE RF Charge Pump foLD Data Out Multiplexer foLD CMOS Output MUX OUT1 IF LD IF Phase Detector IF Charge Pump CPoIF The Samsung S1M8831A/33 is RF/IF dual frequency synthesizer IC which supports Fractional-N mode for RF PLL and Integer-N mode for IF PLL depending on a program control. S1M8831A/33 combined with external LPFs and external VCOs forms PLL frequency synthesizer. The frequency synthesizer consists of prescalers, pulse-swallowed programmable N counters, programmable reference R counters, phase detectors, programmable charge pumps, analog LD (Lock Detector), serial data control, etc. An input buffer in the prescalers amplifies an RF input power of -10dBm from external RF/IF VCOs to a sufficient ECL switching level to drive the following ECL divider so that it can normally operate even in a smaller input power less than -10dBm. The amplified VCO output signal is divided by the prescaler with a pre-determined divide ratio (div. 8/9 in S1M8831A, div. 16/17 in S1M8833, div. 8/9 in IF), the N counter, or the Fractional-N circuitry ( Σ - ∆ modulator). External reference signal is divided by the R counter to set the comparison frequency of the PFD. The divide ratios of the programmable counters can be programmed via the serial bus interface. These two signals drive the both inputs of the phase detector. The phase detector drives the charge pump by comparing frequencies and phases of the above two signals. The charge pump and the external LPF make the control voltage for the external VCO and finally the VCO generates the appropriate frequency signal. 12 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 When the PLL is in the locked state, the RF VCO's frequency will be NINT + NFRAC times the comparison frequency, where NINT is the integer divide ratio and NFRAC is the fractional component. The S1M8831A/33 has new improved features compared to conventional Integer-N PLLs. The Fractional-N PLL is available for the RF. The fractional synthesis allows the PFD comparison frequency to be increased while maintaining the same channel frequency as in AMPS and IS-95A/B/C. It makes possible to widen a loop bandwidth as wide as 20kHz or more for a faster lock-up time and to improve in-band phase noise performance due to a reduced divide ratio N. Such S1M8831A/33 in the Fractional-N mode is suitable for CDMA, GSM and Korean PCS band applications. Also, from the programmability of the charge pump, the user can easily design a stable loop due to free selection of loop components and reach to a low spurs, a low power PLLs due to an optimized current selection. Prescaler The RF/IF prescaler consists of a differential input buffer and ECL frequency dividers. The input buffer amplifies an input signal from an external VCO to the required level set by sensitivity requirements. The output of the amplifier delivers a differential signal to the divider with the correct DC level. The buffer may be either singleended or differentially driven. The single-ended operation is preferred in typical applications due to external VCO. In this case, we recommend that the complementary input fin of the input buffer be AC coupled to ground through external capacitors, even though it is internally coupled to ground via an internal 10pF capacitor. The other input pin fin of the buffer also needs external capacitor for decoupling the DC component and controlling the input power level. The RF prescalers of S1M8831A and S1M8833 provide 8/9 and 16/17 prescaler ratio, respectively. The IF prescaler of S1M8831A/33 contains 8/9 dual modulus prescaler. Reference Oscillator Inputs The reference oscillator frequency is provided by an external reference such as TCXO the OSCin and OSCx pins. When the OSC bit is LOW, the oscillator input pins (OSCin and OSCx) drive the IF R and R counters separately. When the OSC bit is HIGH, on the other hand, the oscillator input pin OSCin drives both IF R and RF R counters. Programmable Dividers (RF/IF N Counters) The RF N counter can be configured as a fractional counter. The fractional-N counter is selected when the FracN_SEL bit becomes HIGH. In the fractional mode, the S1M8831A is capable of offering a continuous integer divide range from 72 to 1008 and the S1M8833 offering a continuous integer divide range from 161 to 168. The S1M8831A/33 IF N counter supports an integer counter mode only, not including fractional counter, and is capable of operating from 45MHz to 520MHz offering a continuous integer divide range from 72 to 32767. 13 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL ∑ - ∆ Modulator The RF part of S1M8831A/33 adopts the Σ -∆ modulator as a core of the fractional counter that makes it possible to obtain divide ratio N to be a fractional number between two contiguous integers. The Σ -∆ modulator effectively randomizes the quantization noise generated from digitizing process and results in extreme suppression of inband noise power by pushing it out to out-of-band as in conventional Σ -∆ data converter. This technique eliminates the need for compensation current injection into the loop filter and improves fractional spurious performance, suitable for high-tier applications. The ∑-∆ modulator operates only for fractional-N mode, when the Frac-N_SEL is HIGH. For proper use of the fractional mode, the user should be kept in mind that 1. A fractional number should be set in the range from -0.5 to 0.5 in step of 1/62976. 2. The clock frequency fixed at 9.84MHz ( = 19.68MHz/2) is recommended for the ∑-∆ modulator which is an optimum condition for achieving better electrical performances related to the fractional noise and power consumption. Only when using the clock frequency, the S1M8831A/33 guarantees the exact frequency resolutions: 10kHz for CDMA PCS and 30kHz for CDMA cellular. Note that the clock frequency much lower than 9.84MHz can deteriorate the fractional noise performance. Phase-Frequency Detector (PFD) and Charge Pump (CP) The RF/IF phase detector composed of PFD and CP outputs pump current into an external loop filter in proportional to the phase difference between outputs of N and R counter . The phase detector has a better linear transfer characteristic due to a feedback loop to eliminate dead zone. The polarity of the PFD can be programmed using RF_PFD_POL/IF_PFD_POL depending on whether RF/IF VCO characteristics are positive or negative. (programming descriptions for phase detector polarity) Power-Down (or Power-Save) Control Each PLL is individually power controlled by the enable pins (RF_EN and IF_EN pins) or program control bits (PWDN, PWDN_RF/IF). The enable pins override the program control bits. When both enable pins are HIGH, the program control bits determine the state of power control. Power down forces all the internal blocks to be deactivated and the charge pump output to be in the TRISTATE. The control register, however, remains active for serial programming and is capable of loading and latching in data during the power down. 14 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 PROGRAMMING DESCRIPTION The S1M8831A/33 can be programmed via the serial bus interface. The interface is made of 3 functional signals: clock, data, and latch enable(LE). Serial data is moved into the 24-bit shift register on the rising edge of the clock. These data enters MSB first. When LE goes HIGH, data in the shift register is moved into one of the 4 latches (by the 2-bit control). MSB LSB Data Flow (MSB First) DATA[23:2] CTL[1:0] Control Bit Map (CTL[1:0]) Control Bits Data Location CTL2(CTL[1]) CTL1(CTL[0] 0 0 RF/IF R counter 0 1 IF N counter 1 0 RF N counter 1 1 RF Frac counter Data Bit Map (DATA[23:2]) First Bit 23 Register Bit Location 22 21 RIF_R IF_N 20 19 18 17 16 15 14 TEST TEST OSC 13 12 11 10 Last Bit 9 8 7 6 5 4 3 2 IF_R_CNTR(15 bits) IF_CTL_ IF_CP_ WORD WORD RF_N RF_CTL_WORD CMOS RF_Frac RF_NA_CNTR(4 bits) TEST IF_NB_CNTR(3 bits) IF_NA_CNT 1 0 0 0 0 1 1 0 1 1 R(3 bits) RF_CP_WORD RF_NB_CNTR(7 bits) FRAC_CNTR(17 bits) FoLD(4 bits) NOTE: Test bits are reserved and should be set to be zero(Low) for normal usage. 15 S1M8831A/33 Control Words FRACTIONAL-N RF/INTEGER-N IF DUAL PLL Control bits Acronym OSC IF_N[22] OSC Separate inputs; OSCin: for IF, OSCx: for RF Common input Reference through OSCin for oscillator input both RF and IF control IF_CTL_WORD IF_N[21] IF_CNT_RST Normal operation IF counter reset IF IF_N[20] PWDN_IF Power up Power down IF IF_N[19] PWDN Asynchronous power down Synchronous power down RF and IF IF_N[18] IF_CP_GAIN 1X 8X IF charge pump IF_N[17] IF_PFD_POL Negative slope Positive slope IF PFD RF_N[23] RF_CNT_RST Normal operation RF counter reset RF RF_N[22] PWDN_RF Power up Power down RF RF_N[21] Frac-N_SEL Integer-N mode Fractional-N mode RF; PLL mode selection RF_N[20] Speedy_Lock CMOS output Speedy Lock mode RF_N[19] OUT1 Voltage LOW Voltage HIGH pin #23 RF_N[18] OUT0 Voltage LOW Voltage HIGH pin #24 RF_N[17:14] RF_CP_LVL RF_N[13] RF_PFD_POL RF_N[5:2] foLD IF_CP_WORD RF_CTL_WORD CMOS RF_CP_WORD foLD LOW (0) HIGH (1) Comments Select 16-level charge pump current (RF charge pump gain for control codes in detail) RF charge pump Negative slope RF PFD Positive slope Select LDs and monitoring mode of internal counters. (foLD control for control codes in detail) Lock Detector (LD), test mode — Counter reset mode resets R & N counters. — IF charge pump current can be selected to high current (8X) or low current (1X) mode. — In the Speedy Lock mode, the OUT0 and OUT1 pins can be utilized as synchronous switches between active low and tri-state. The Speedy Lock mode activates the OUT0 and OUT1 pins to be connected to GROUND with a low impedance (< 150Ω) while a high charge pump gain (≥ S 8X) is selected and otherwise to the TRISTATE. — For using a programmable CMOS output, the CMOS output bit(RF_N[20]=L) should be activated and then the desired logic level should be programmed with the control bits RF_N[18] for OUT0 and RF_N[19] for OUT1. 16 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 Programmable Reference Counter (IF_R_CNTR[16:2]) If the control bit is 00, data is moved from the 24-bit shift register into the R-latch which sets the IF reference counter. Serial data format is shown in the table below. MSB RIF_R[23:0] TEST LSB IF_R_CNTR[16:2] ; 3 ~ 32767 23 0 17 16 0 2 1 0 Division Ratio of the IF R Counter, IF_R_CNTR(RI) Reserved for Test Control Bits • 15-Bit IF R Counter Division Ratio Division ratio: 3 to 32767 (The divide ratios less than 3 are prohibited) Data are shifted in MSB first Division Ratio • RI RI RI RI RI RI RI RI RI RI RI RI RI RI RI 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • • • • • • • • • • • • • • • • 32767 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RF R Counter Division Ratio Division Ratio: 2 (fixed value. Note it is not programmable.) 17 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL Programmable Counter (N CoUnter) If the control bits are 01(IF), 10, and 11(RF), data is transferred from the 24-bit shift register into the N/Frac-latch. N Counter consists of swallow counter (A counter; 3-bit for IF & S1M8831A RF and 4-bit for S1M8833), main counter (B counter; 7-bit for S1M8831A/33 RF and 12-bit for IF), and fractional counter (F counter; 17-bit for S1M8831A/33 RF). Serial data format is shown below. IF N Counter MSB TEST 23 IF_N[23:0] OSC 22 IF_CTL_ WORD [21:19] 21 IF_CP-WORD [18:17] LSB IF_NA_CNTR [4:2] ; 0 - 7 IF_NB_CNTR[16:5] ; 3 - 4095 17 16 19 18 5 4 Program Code 0 2 1 1 0 Division Ratio of the IF N Counter Control Bits • IF Main Counter Division Ratio (B Counter) IF_NB_ CNTR[16:5] ; for S1M8831A/33 Division Ratio(B) N N N N N N N N N N N N 11 10 9 8 7 6 5 4 3 2 1 0 3 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 1 0 0 • • • • • • • • • • • • • 4095 1 1 1 1 1 1 1 1 1 1 1 1 Division Ratio: 3 to 4095 (The division ratios less than 3 are prohibited) • Swallow Counter Division Ratio (A Counter) IF_NA_CNTR[4:2] ; for S1M8831A/33 Division Ratio(A) N N N 2 1 0 0 0 0 0 1 0 0 1 • • • • 7 1 1 1 Division Ratio: 0 to 7 (B > A) 18 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 RF N Counter MSB RF_N[23:0] RF_CTL_WORD [23:21] 23 RF_CP_WORD [17:13] CMOS[20:18] 21 20 18 17 LSB RF_NB_CNTR[12:16] ; 3 - 127 13 12 FoLD[5:2] 1 6 5 0 2 1 0 Division Ratio of the RF N Counter Program Code Control Bits RF_Frac[23:0] RF_NA_CNTR [23:20] • TEST FRAC_CNTR[18:2] 1 1 RF Main Counter Division Ratio (B Counter) RF_NB_ CNTR[12:6] ; for S1M8831A/33 Division Ratio(B) N N N N N N N 6 5 4 3 2 1 0 3 0 0 0 0 0 1 1 4 0 0 0 0 1 0 0 • • • • • • • • 127 1 1 1 1 1 1 1 Division Ratio: 3 to 127 (The division ratios less than 3 are prohibited) • RF Swallow Counter Division Ratio (A Counter) RF_NA_CNTR[23:20] ; for S1M8831A Division Ratio(A) RF_NA_CNTR[23:20] ; for S1M8833 N N N N 3 2 1 0 0 x 0 0 0 1 x 0 0 • • • 7 x 1 Division Ratio: 0 to 7 (B > A) x = Don' t care condition Division Ration(A) N N N N 3 2 1 0 0 0 0 0 0 1 1 0 0 0 1 • • • • • • • 1 1 15 1 1 1 1 Division Ratio: 0 to 15 (B > A) 19 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL RF Fractional Counter RF_Frac[23:0] MSB RF_NA_CNTR [23:20] 23 TEST 20 19 LSB FRAC_CNTR[18:2] 1 18 1 2 1 Program Code 0 Division Ratio of the RF Fractional Counter Control Bits • RF Fractional Counter Value (F Counter) FRAC_ CNTR[18:2] ; for S1M8831A/33 RF Counter F F F F F F F F F F F F F F F F F Value(F) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31488 0 0 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 • • • • • • • • • • • • • • • • • • 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 • • • • • • • • • • • • • • • • • • -31488 1 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 F Counter Value: -31488(2's complementary) to 31488 NOTE: For a negative integer, the counter value should be inputted as the corresponding 2's complementary binary code. For instance, the 2's complementary binary code of -2 is 1 1111 1111 1111 1110. 20 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 Programmable PFD and Charge Pump IF Charge Pump Gain (IF_CP_WORD; IF_N[18]) Control Words Control Bits Acronym LOW (0) HIGH (1) Comments IF_CP_WORD IF_N[18] IF_CP_GAIN 1X (100uA) 8X (800uA) IF charge pump LOW (0) HIGH (1) Comments RF Charge Pump Gain (RF_CP_WORD; RF_N[17:14]) Control Words Control Bits Acronym RF_CP_WORD RF_N[17:14] RF_CP_LVL Icpo (uA) Select 16-level charge pump current RF charge pump 8X 4X 2X 1X RF_N[17] RF_N[16] RF_N[15] RF_N[14] 50 0 0 0 0 100 0 0 0 1 • • • • • 200 0 0 1 1 250 0 1 0 0 • • • • • 400 0 1 1 1 450 1 0 0 0 • • • • • 800 1 1 1 1 21 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL Phase Detector Polarity (RF_CP_WORD/IF_CP_WORD; RF_N[13]/IF_N[17]) Depending on VCO characteristics, IF_N[17] and RF_N[13] bits should be set as follows: Control Bits LOW (0) HIGH (1) Comments IF_N[17] Negative Slope Positive Slope IF PFD RF_N[13] Negative Slope Positive Slope RF PFD VCO Characteristics (1) VCO Output Frequency (2) VCO Input Voltage 22 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 Program Mode Control Power Down Mode Operation Control Words Control bits Acronym LOW (0) HIGH (1) Comments IF_CTL_WORD IF_N[20] PWDN_IF Power Up Power Down IF IF_N[19] PWDN Asynchronous Power Down Synchronous Power Down RF and IF RF_N[22] PWDN_RF Power Up Power Down RF RF_CTL_WORD Each PLL is individually power controlled by the enable pins (RF_EN and IF_EN pins) or program control bits (PWDN, PWDN_RF/IF). The enable pins override the program control bits. When both enable pins are HIGH, the program control bits determine the state of power control. Power down forces all the internal analog blocks to be deactivated and the charge pump output to be in a TRISTATE. The oscillator circuitry function becomes disabled dependent on the state of IF and RF power-down bits, IF_N[20] and RF_N[22]. The RF(or IF) oscillator buffer is powered down when the power down bit (RF_N[22] or IF_N[20]) becomes HIGH. The control register and R/N counters, however, remains active for permitting serial programming and is capable of loading and latching in data during the power down. The PLL returns to the active power-up mode when IF_N[20] and RF_N[22] become LOW. There are synchronous and asynchronous power-down modes for S1M8831A/33. The power-down bit IF_N[19] is used to select between synchronous and asynchronous power down. Synchronous power down mode occurs if IF_N[19] bit is HIGH and then the power down bit (RF_N[22] or IF_N[20]) becomes HIGH. In the synchronous power down mode, the power-down function will go into power down mode upon the completion of a charge pump pulse event because it is synchronized with the charge pump and thus can diminish undesired frequency jumps. Asynchronous power down mode occurs if IF_N[19] bit is LOW and then the power down bit (RF_N[22] or IF_N[20]) becomes HIGH. Activation of the asynchronous function will go into power-down mode immediately. RF Power Down Mode Table RF_N[22] IF_N[19] Power Down Mode Status 0 0 RF PLL active 0 1 RF PLL active, only charge pump to TRISTATE 1 0 Asynchronous power down 1 1 Synchronous power down IF Power Down Mode Table IF_N[20] IF_N[19] Power Down Mode Status 0 0 IF PLL active 0 1 IF PLL active, only charge pump to TRISTATE 1 0 Asynchronous power down 1 1 Synchronous power down 23 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL Reference Oscillator Input Control Control Words Control bits Acronym LOW (0) HIGH (1) Comments OSC IF_N[22] OSC separate inputs; common input through OSCin for both RF and IF reference oscillator input control OSCin: for IF, OSCx: for RF The reference oscillator frequency is provided from an external reference such as TCXO through the OSCin and OSCx pins. When the OSC bit is LOW, the oscillator input pins( OSCin and OSCx) drive the IF R and RF R counters separately. When the OSC bit is HIGH, on the other hand, the oscillator input pin OSCin drives the IF R and RF R counters commonly. IF_N[22] = LOW PWDN_IF PWDN_RF IF RF IF_N[20] RF_N[22] 0 0 OSCin OSCx 0 1 OSCin LOW(powerdown) 1 0 LOW(powerdown) OSCx 1 1 LOW(powerdown) LOW(powerdown) PWDN_IF PWDN_RF IF RF IF_N[20] RF_N[22] 0 0 OSCin OSCin 0 1 OSCin LOW(powerdown) 1 0 LOW(powerdown) OSCin 1 1 LOW(powerdown) LOW(powerdown) IF_N[22] = HIGH 24 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 Programmable Counter Reset Control Control Words Control Bits Acronym LOW (0) HIGH (1) Comments IF_CTL_WORD IF_N[21] IF_CNT_RST Normal Operation IF Counter Reset IF RF_CTL_WORD RF_N[23] RF_CNT_RST Normal Operation RF Counter Reset RF Counter Reset Mode Resets R & N Counters. RF Fractional-N Selection Control Words Control Bits Acronym LOW (0) HIGH (1) Comments RF_CTL_WORD RF_N[21] Frac-N_SEL Reserved Fractional-N Mode RF; PLL Mode Selection Comments CMOS Output Control Control Words Control Bits Acronym LOW (0) HIGH (1) CMOS RF_N[20] Speedy Lock CMOS Output Speedy Lock Mode RF_N[19] OUT1 Voltage LOW Voltage HIGH Pin #23 RF_N[18] OUT0 Voltage LOW Voltage HIGH Pin #24 In the Speedy Lock mode, the OUT0 and OUT1 pins can be utilized as synchronous switches between active low and a tri-state. The Speedy Lock mode activates the OUT0 and OUT1 pins to be connected to GROUND with a low impedance ( < 150Ω) while a high charge pump gain ( ≥ 8X) is selected and otherwise to a tri-state. For using a programmable CMOS output, the CMOS output bit(RF_N[20] = LOW) should be activated and then the desired logic level should be programmed with the control bits RF_N[18] for OUT0 and RF_N[19] for OUT1. 25 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL foLD Control Control Words Control Bits Acronym foLD RF_N[5:2] foLD LOW (0) HIGH (1) Select LDs and monitoring mode of internal counters. Comments Lock Detector(LD), Test Mode foLD[3] foLD[2] foLD[1] foLD[0] foLD Output State 0 0 0 0 Disabled (default LOW) 0 0 0 1 RF and IF analog lock detect 0 0 1 0 Reserved test mode 0 0 1 1 Reserved test mode X 1 0 0 Reserved test mode X 1 0 1 IF R counter output X 1 1 0 IF N counter output X 1 1 1 RF R counter output 1 0 0 0 RF N counter output 1 0 0 1 Reserved test mode 1 0 1 0 Reserved test mode 1 0 1 1 Reserved test mode — When the PLL is locked and the analog lock detect mode is selected, the foLD output is HIGH, with narrow pulses LOW. Lock Detector (LD) There is analog mode for S1M8831A/33. The foLD bits, RF_N[5:2], are used to select the lock detection mode and to output the selected lock signal through the foLD pin. The foLD output becomes HIGH with narrow pulsed LOW while both RF and IF PLLs are locked and thereby the output should be low-pass filtered for a DC locked voltage HIGH. 26 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 Pulse Swallow Function The RF VCO's frequency fVCO becomes NINT + NFRAC times the comparison frequency (fOSC/R) where NINT is the integer divide ratio and NFRAC is the fractional component; fVCO = (NINT + NFRAC) × fOSC/R = N × fOSC/R where NINT = (P × B) + A, RF PLL: NFRAC = F/62976, -31488 ≤ F ≤ 31488, B > P, and R = 2 IF PLL: NFRAC = 0, B > A, and 3 ≤ R ≤ 32767 f VCO : External VCO output frequency f OSC : External reference frequency (From external oscillator) R : Preset divide ratio of programmable R counter (RF: 2, IF: 3 to 32767); P : Preset modulus of dual modulus prescaler (S1M8831 RF: P=8, S1M8833 RF: P=16, IF: P=8) B : Preset value of main counter (S1M8831A/33 RF: 3 to 126, IF: 3 to 4095) A : Preset value of swallow counter division ratio (S1M8831 RF: 0 ≤ A ≤ 7, S1M8833 RF: 0 ≤ A ≤ 15, IF: 0 ≤ A ≤ 7, A < B) NFRAC : Fractional component of Pulse-swallowed division ratio N (for IF: NFRAC = 0) F : Preset value of fractional register (-31488 ≤ F ≤ 31488); For a negative integer, F should be inputted as its 2's complementary binary code. For examples in S1M8831 fractional-N mode (fOSC = 19.68MHz, R=2, P=8) 1) for fvco = 955.02MHz 0000) ; N = 97.05487805, B=12, A=1, F=3456 (= 0 0000 1101 1000 2) for fvco = 955.03MHz ; N = 97.05589431, B=12, A=1, F=3520 3) for fvco = 956.25MHz ; N = 97.17987805, B=12, A=1, F=11328 4) for fvco = 979.35MHz ; N = 99.52743902, B=12, A=4, F=-29760 ∴ F= 0.52743903 X 62976 = 33125 → 33125 > 31488 (A=3+1=4) = 33215 – 62976 = -29760 (1 1000 1011 1100 0000) For examples in S1M8833 fractional-N mode (fOSC = 19.68MHz, R=2, P=16) 1) for fvco = 1620.87MHz(CH25) ; N = 164.722561, B=10, A=5, F=-17472 (= 1 1011 1011 1100 0000) 2) for fvco = 1620.88MHz ; N = 164.7235772, B=10, A=5, F=-17408 3) for fvco = 1622.12MHz(CH50) ; N = 164.8495935, B=10, A=5, F=-9472 4) for fvco = 1632.12MHz(CH250) ; N = 165.8658537, B=10, A=6, F=-8448 5) for fvco = 1648.37MHz(CH575) ; N = 167.5172764, B=10, A=8, F=-30400 27 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL Serial Data Input Timing MSB DATA LSB DATA[23] DATA[22] DATA[10] DATA[9] CTL[1] CTL[0] CLOCK tDS tCWL tCWH tLEW LE tDH tCLE Phase Detector and Charge Pump Characteristics Phase difference detection range: -2π to +2π When the positive-slope polarity of PFD is selected, IF_N[17] = HIGH or RF_N[13] = HIGH; fr fp LD CPo fr > fp 28 fr = fp fr < fp fr < fp fr < fp FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 SIMPLIFIED SCHEMATIC DIAGRAM FOR RF SENSITIVITY TEST 2.7V to 4.0V RF Signal Generator 50Ω Microstrip 100pF 10dB ATTN 51Ω VDD fin fin 100pF VP 100pF S1M8831A /33 2.2µF 100pF 2.2µF OSCin LE foLD DATA CLOCK Frequency Counter PC Parallel Port 12kΩ 39kΩ NOTES: 1. Sensitivity limit is determined when the error of the divided RF output (fOLD) becomes 10Hz. 2. fVCO = 1.0GHz, N = 1000, P = 8, R = 2 in S1M8831 Integer-N test mode fVCO = 1.6GHz, N = 1600, P = 16, R = 2 in 1M8833 Integer-N test mode 29 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL TYPICAL APPLICATION CIRCUIT VP R3 VCO 100pF 0.01µF 10pF C3 RF Out C2 R1 VDD C1 Reference Input 1000pF 100pF 0.01µF 10pF 51Ω 100pF 22Ω Rin foLD 9 8 7 6 5 4 3 2 1 OSCin OSCx GNDRF finRF finRF DGND CPORF VPRF VDDRF 10 foLD 0.1µF OUT0 24 VDD 11 RF_EN S1M8831A/33 OUT1 23 0.1µF 12 IF_EN VDDIF CLCOK DATA LE GNDIF finIF finIF DGND CPOIF VPIF 13 14 15 16 17 18 19 20 21 From Controller 22 22Ω VDD Rin 1000pF 100pF 0.01µF 56pF IF Out 56pF VP <RF VCO Module: ALPS Part No> . CDMA : UCVA4X103A . K-PCS : UCVW4X102A . US-PCS : UCVA3X120A VCO R13 100pF C13 C12 R11 C11 NOTE: The role of Rin: Rin makes a large portion of VCO output power go to the load rather than the PLL. The value of Rin depends on the VCO power level. 30 0.01µF FRACTIONAL-N RF/INTEGER-N IF DUAL PLL S1M8831A/33 PCB LAYOUT GUIDE In doing PCB layouts for S1M8831A/33, we recommend that you apply the following design guide to your handsets, thus improving the phase noise and reference spurious performances of the phones. 1. The S1M8831A/33 has external four power supply pins to supply on-chip bias, each for analog and digital blocks of RF and IF PLLs. Basically in doing PCB layout, it is important that power supply lines should be separated from one another and thus coupling noises through the voltage supply lines can be minimized. If you have some troubles with the direction to separate, you can choose the following recommendations for your convenience; • Tying analog power lines, VCCRF and VCCIF, is possible. • Tying digital power lines, VP1 and VP2, is possible. • A point connecting the analog and digital power lines should be near to battery line as close as possible. It minimizes coupling noise effects from a digital switching noise into analog blocks. We also recommend that a passive RC low pass filter (R(22Ω), C(100nF)) be utilized for suppressing high frequency noise on the analog power supply line and reducing any digital noise couplings. 2. VCO power lines should be well separated from those of PLL because VCO is generally a very sensitive device from power line noises and PLL is a digital noise generator. 3. For more improvement of reference spurious performance, it is recommended that the LPF ground be tied to the PLL ground, not the VCO ground. 31 S1M8831A/33 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL PACKAGE DIMENSIONS 1.00MAX 0.27 + 0.05 0.70 + 0.05 4.50 + 0.10 #1 INDEX AREA B 3.50 + 0.10 C A (0.05) (0.05) 0.08 4X0.50 + 0.10 #24 #1 2X4.00 #1 ID MARK 2X 0.10 20X0.50 24X0.30 + 0.05 2X1.00 2X 0.10 32 C C 0.10 M C B C S C