SAMSUNG KM416V4100C

KM416V4000C, KM416V4100C
CMOS DRAM
4M x 16bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 4,194,304 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6), power consumption(Normal or Low power) are
optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 Fast Page Mode DRAM family is fabricated using Samsung′s
advanced CMOS process to realize high band-width, low power consumption and high reliability.
• Fast Page Mode operation
• 2CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic TSOP(II) packages
FEATURES
• Part Identification
- KM416V4000C/C-L(3.3V, 8K Ref.)
- KM416V4100C/C-L(3.3V, 4K Ref.)
• Active Power Dissipation
Unit : mW
Speed
8K
4K
-45
324
468
-5
288
432
-6
252
396
• +3.3V±0.3V power supply
• Refresh Cycles
Refresh
cycle
Normal
L-ver
KM416V4000C*
8K
64ms
128ms
KM416V4100C
4K
FUNCTIONAL BLOCK DIAGRAM
Refresh time
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
RAS
UCAS
LCAS
W
Refresh Timer
Refresh Counter
tRAC
tCAC
tRC
tPC
-45
45ns
12ns
80ns
31ns
-5
50ns
13ns
90ns
35ns
-6
60ns
15ns
110ns
40ns
A0~A12
(A0~A11)*1
Row Address Buffer
A0~A8
(A0~A9)*1
Col. Address Buffer
Vcc
Vss
VBB Generator
Lower
Data in
Buffer
Row Decoder
Refresh Control
• Performance Range
Speed
Control
Clocks
Memory Array
4,194,304 x 16
Cells
Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
Sense Amps & I/O
Part
NO.
Lower
Data out
Buffer
Upper
Data in
Buffer
Upper
Data out
Buffer
DQ0
to
DQ7
OE
DQ8
to
DQ15
KM416V4000C, KM416V4100C
CMOS DRAM
PIN CONFIGURATION (Top Views)
•KM416V40(1)00CS
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
N.C
VCC
W
RAS
N.C
N.C
N.C
N.C
A0
A1
A2
A3
A4
A5
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
N.C
VSS
LCAS
UCAS
OE
N.C
N.C
A12(N.C)*
A11
A10
A9
A8
A7
A6
VSS
(400mil TSOP(II))
*(N.C) : N.C for 4K Refresh Product
Pin Name
Pin function
A0 - A12
Address Inputs(8K Product)
A0 - A11
Address Inputs(4K Product)
DQ0 - 15
Data In/Out
VSS
Ground
RAS
Row Address Strobe
UCAS
Upper Column Address Strobe
LCAS
Lower Column Address Strobe
W
Read/Write Input
OE
Data Output Enable
VCC
Power(+3.3V)
N.C
No Connection
KM416V4000C, KM416V4100C
CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Symbol
Rating
Units
VIN,VOUT
-0.5 to +4.6
V
Voltage on VCC supply relative to VSS
VCC
-0.5 to +4.6
V
Storage Temperature
Tstg
-55 to +150
°C
PD
1
W
IOS Address
50
mA
Power Dissipation
Short Circuit Output Current
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, T A= 0 to 70°C)
Symbol
Min
Typ
Max
Units
Supply Voltage
Parameter
VCC
3.0
3.3
3.6
V
Ground
VSS
0
0
0
V
Input High Voltage
VIH
2.0
-
VCC+0.3*1
V
Input Low Voltage
VIL
-
0.8
V
*2
-0.3
*1 : VCC+1.3V at pulse width ≤15ns which is measured at VCC
*2 : -1.3 at pulse width ≤15ns which is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0≤VIN≤VCC+0.3V,
all other pins not under test=0 Volt)
II(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V≤VOUT≤VCC)
IO(L)
-5
5
uA
Output High Voltage Level(IOH=-2mA)
VOH
2.4
-
V
Output Low Voltage Level(IOL=2mA)
VOL
-
0.4
V
KM416V4000C, KM416V4100C
CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol
Power
Speed
ICC1
Don′t care
ICC2
Max
Units
KM416V4000C
KM416V4100C
-45
-5
-6
90
80
70
130
120
110
mA
mA
mA
Normal
L
Don′t care
1
1
1
1
mA
mA
ICC3
Don′t care
-45
-5
-6
90
80
70
130
120
110
mA
mA
mA
ICC4
Don′t care
-45
-5
-6
70
60
50
70
60
50
mA
mA
mA
ICC5
Normal
L
Don′t care
0.5
200
0.5
200
mA
uA
ICC6
Don′t care
-45
-5
-6
130
120
110
130
120
110
mA
mA
mA
ICC7
L
Don′t care
350
350
uA
ICCS
L
Don′t care
350
350
uA
ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.)
ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH)
ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.)
ICC4* : Fast Page Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tPC=min.)
ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=CAS-before-RAS cycling or 0.2V,
W, OE=VIH, Address=Don′t care, DQ=Open, TRC=31.25us
ICCS : Self Refresh Current
RAS=UCAS=LCAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open
*Note :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one fast page mode cycle time, tPC.
KM416V4000C, KM416V4100C
CMOS DRAM
CAPACITANCE (TA=25°C, V CC=3.3V, f=1MHz)
Symbol
Min
Max
Units
Input capacitance [A0 ~ A12]
Parameter
CIN1
-
5
pF
Input capacitance [RAS, UCAS, LCAS, W, OE]
CIN2
-
7
pF
Output capacitance [DQ0 - DQ15]
CDQ
-
7
pF
AC CHARACTERISTICS (0°C≤TA≤70°C, See note 2)
Test condition : VCC =3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
Parameter
-45
Symbol
Min
-5
Max
Min
-6
Max
Min
Units
Note
Max
Random read or write cycle time
tRC
80
Read-modify-write cycle time
tRWC
115
Access time from RAS
tRAC
45
50
60
ns
3,4,10
Access time from CAS
tCAC
12
13
15
ns
3,4,5
Access time from column address
tAA
23
25
30
ns
3,10
90
110
133
ns
153
ns
CAS to output in Low-Z
tCLZ
0
Output buffer turn-off delay
tOFF
0
13
Transition time (rise and fall)
tT
1
50
RAS precharge time
tRP
25
RAS pulse width
tRAS
45
RAS hold time
tRSH
12
CAS hold time
tCSH
45
CAS pulse width
tCAS
12
10K
13
10K
15
10K
ns
0
0
0
13
1
50
30
10K
50
ns
3
0
13
ns
6
1
50
ns
2
40
10K
13
60
ns
10K
15
50
ns
ns
60
ns
RAS to CAS delay time
tRCD
18
33
20
37
20
45
ns
4
RAS to column address delay time
tRAD
13
22
15
25
15
30
ns
10
CAS to RAS precharge time
tCRP
5
5
5
ns
Row address set-up time
tASR
0
0
0
ns
Row address hold time
tRAH
8
10
10
ns
Column address set-up time
tASC
0
0
0
ns
13
Column address hold time
13
tCAH
8
10
10
ns
Column address to RAS lead time
tRAL
23
25
30
ns
Read command set-up time
tRCS
0
0
0
ns
Read command hold time referenced to CAS
tRCH
0
0
0
ns
8
Read command hold time referenced to RAS
8
tRRH
0
0
0
ns
Write command hold time
tWCH
8
10
10
ns
Write command pulse width
tWP
8
10
10
ns
Write command to RAS lead time
tRWL
13
15
15
ns
Write command to CAS lead time
tCWL
12
13
15
ns
16
Data set-up time
tDS
0
0
0
ns
9,19
Data hold time
tDH
10
10
10
ns
9,19
KM416V4000C, KM416V4100C
CMOS DRAM
AC CHARACTERISTICS (Continued)
Parameter
-45
Symbol
Min
-5
Max
Min
-6
Max
Min
Units
Note
Max
Refresh period (Normal)
tREF
Refresh period (L-ver)
tREF
Write command set-up time
tWCS
0
0
0
ns
7
CAS to W delay time
tCWD
32
36
38
ns
7,15
RAS to W delay time
tRWD
67
73
83
ns
7
Column address to W delay time
tAWD
43
48
53
ns
7
CAS precharge W delay time
tCPWD
48
53
60
ns
CAS set-up time (CAS -before-RAS refresh)
tCSR
5
5
5
ns
17
CAS hold time (CAS -before-RAS refresh)
tCHR
10
10
10
ns
18
RAS to CAS precharge time
tRPC
5
5
5
ns
Access time from CAS precharge
tCPA
Fast Page mode cycle time
Fast Page mode read-modify-write cycle time
CAS precharge time (Fast page cycle)
64
64
128
128
26
30
64
ms
128
ms
35
ns
3
tPC
31
35
40
ns
tPRWC
70
76
85
ns
tCP
9
10
10
RAS pulse width (Fast page cycle)
tRASP
45
RAS hold time from CAS precharge
tRHCP
28
OE access time
tOEA
OE to data delay
tOED
12
Output buffer turn off delay time from OE
tOEZ
0
OE command hold time
tOEH
12
13
15
ns
Write command set-up time (Test mode in)
tWTS
10
10
10
ns
11
Write command hold time (Test mode in)
tWTH
15
15
15
ns
11
W to RAS precharge time (C-B-R refresh)
tWRP
10
10
10
ns
W to RAS hold time (C-B-R refresh)
tWRH
10
10
10
ns
RAS pulse width (C-B-R self refresh)
tRASS
100
100
100
us
20,21,22
RAS precharge time (C-B-R self refresh)
tRPS
80
90
110
ns
20,21,22
CAS hold time (C-B-R self refresh)
tCHS
-50
-50
-50
ns
20,21,22
200K
50
200
30
12
13
0
ns
200
35
13
13
60
ns
15
13
13
0
14
ns
ns
3
ns
13
ns
6
KM416V4000C, KM416V4100C
CMOS DRAM
TEST MODE CYCLE
Parameter
( Note 11 )
-45
Symbol
Min
-5
Max
Min
-6
Max
Min
Units
Note
Max
Random read or write cycle time
tRC
85
Read-modify-write cycle time
tRWC
120
Access time from RAS
tRAC
50
55
65
ns
3,4,10,12
Access time from CAS
tCAC
17
18
20
ns
3,4,5,12
Access time from column address
tAA
3,10,12
RAS pulse width
tRAS
50
10K
55
10K
CAS pulse width
tCAS
17
10K
18
10K
RAS hold time
tRSH
17
18
20
ns
CAS hold time
tCSH
50
55
65
ns
Column Address to RAS lead time
tRAL
28
30
35
ns
CAS to W delay time
tCWD
37
41
43
ns
7
RAS to W delay time
tRWD
72
78
88
ns
7
Column Address to W delay time
tAWD
48
53
58
ns
7
Fast Page mode cycle time
tPC
36
40
45
ns
Fast Page mode read-modify-write cycle time
tPRWC
75
tRASP
50
Access time from CAS precharge
tCPA
OE access time
tOEA
OE command hold time
115
138
28
RAS pulse width (Fast page cycle)
OE to data delay
95
160
30
81
200K
55
31
ns
35
ns
65
10K
ns
20
10K
90
200K
65
35
17
ns
18
ns
ns
200K
ns
40
ns
20
ns
tOED
17
18
18
ns
tOEH
17
18
20
ns
3
KM416V4000C, KM416V4100C
CMOS DRAM
NOTES
1. An initial pause of 200§ Á is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is
achieved.
2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 1 TTL load and 100pF.
4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
5. Assumes that tRCD≥tRCD(max).
6. tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced Voh
or Vol.
7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric characteristics only. If tWCS≥tWCS (min), the cycles is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD ≥tCWD(min), tRWD≥tRWD(min) and tAWD ≥tAWD(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameters are referenced to the CAS leading edge in early write cycles and to the W falling edge in read-modifywrite cycles.
10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
11. These specifications are applied in the test mode.
12. In test mode read cycle, the value of tRAC , tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
KM416V40(1)00C Truth Table
RAS
LCAS
UCAS
W
OE
DQ0 - DQ7
DQ8-DQ15
STATE
H
X
X
X
X
Hi-Z
Hi-Z
Standby
L
H
H
X
X
Hi-Z
Hi-Z
Refresh
L
L
H
H
L
DQ-OUT
Hi-Z
Byte Read
L
H
L
H
L
Hi-Z
DQ-OUT
Byte Read
L
L
L
H
L
DQ-OUT
DQ-OUT
Word Read
L
L
H
L
H
DQ-IN
-
Byte Write
L
H
L
L
H
-
DQ-IN
Byte Write
L
L
L
L
H
DQ-IN
DQ-IN
Word Write
L
L
L
H
H
Hi-Z
Hi-Z
-
KM416V4000C, KM416V4100C
CMOS DRAM
13. tASC, tCAH are referenced to the earlier CAS falling edge.
14. tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle.
15. tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.
16. tCWL is specified from W falling edge to the earlier CAS rising edge.
17. tCSR is referenced to earlier CAS falling before RAS transition low.
18. tCHR is referenced to the later CAS rising high after RAS transition low.
RAS
LCAS
UCAS
tCSR
tCHR
19. tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge.
LCAS
UCAS
tDS
DQ0 ~ DQ15
tDH
Din
20. If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP.
21. For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.
22. For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and
after self refresh in order to meet refresh specification.