HANBit HMD1M4Z1 4Mbit(1Mx4bit) Fast Page Mode, 1K Refresh, 20Pin ZIP, 5V Design Part No. HMD1M4Z1 DESCRIPTION The HMD1M4Z1 is an 1M x 4 bits Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage (+5V ), access time (-5, -6), power consumption(Normal or Low power), and package type (ZIP) are optional features of this Module. The HMD1M4Z1 have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. The HMD1M4Z1 is optimized for application to the systems, which are required high density and large capacity such as main memory for main frames and mini computers, personal computer and high performance microprocessor systems. The HMD1M4Z1 provides common data and outputs. Features PIN ASSIGNMENT w Fast Page Mode operation w CAS-before-RAS refresh capability PIN SYMBOL w RAS-only and Hidden refresh capability 1 /OE w Fast parallel test mode capability 2 /CAS w TTL(5V) compatible inputs and outputs 3 DQ2 w Early write or output enable controlled write 4 DQ3 w Available in 20pin ZIP packages 5 VSS w Single +5V± 10% power supply 6 DQ0 w 1,024 Refresh Cycles/16ms 7 DQ1 8 /WE w Performance Range tRAC tCAC tRC tPC 9 /RAS HMD1M4Z1-5 50 15 90 35 10 A9 HMD1M4Z1-6 60 15 110 40 11 A0 12 A1 13 A2 14 A3 Speed PIN DESCRIPTION 15 VCC FUNCTION Read/Write Enable 16 A4 17 A5 Vcc Power (+5V) 18 A6 19 A7 Vss Ground 20 A8 NC No Connection PIN FUNCTION PIN A0 – A9 Address Inputs /WE DQ0 – Data Input/Output DQ3 /RAS /CAS /OE Row Address Strobe Column Address Strobe Data Output Enable URL:www.hbe.co.kr REV.1.0(August.2002) 1 HANBit Electronics Co.,Ltd. HANBit HMD1M4Z1 ABSOLUTE MAXIMUM RATINGS* SYMBOL PARAMETER RATING UNIT 0 ~ 70 C Storage Temperature (Plastic) -55 ~ 150 C Voltage on any Pin Relative to Vss -1.0 ~ 7.0 V VCC Power Supply Voltage -1.0 ~ 7.0 V IOUT Short Circuit Output Current 50 mA Power Dissipation 600 mW Ambient Temperature under Bias TA TSTG VIN/VOUT PD *NOTE: 1. Stress greater than above absolute Maximum Ratings? May cause permanent damage to the device. RECOMMENDED DC OPERATING CONDITIONS (TA = 0 ~ 70C) PARAMETER SYMBOL MIN TYP. MAX UNIT Supply Voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 V Input High Voltage VIH 2.4 - Vcc+1 V Input Low Voltage VIL -1.0 - 0.8 V *NOTE: All voltages referenced to Vcc DC AND OPERATING CHARACTERISTICS SYMBOL VOH VOL ICC1 ICC2 ICC3 ICC4 PARAMETER MIN Output High Level Voltage (IOUT = -5mA) 2.4 Output Low Level Voltage (IOUT = 4.2mA) 0 MAX UNIT V 0.4 Operating Current -5 85 (/RAS,/CAS,Address Cycling : tRC = tRC min) -6 75 V mA Standby Current (/RAS,/CAS = VIH) - 2 mA /RAS Only Refresh Current -5 85 (/RAS Cycling, /CAS = VIH,: tRC = tRC min) -6 75 Fast Page Mode Current -5 65 mA (/RAS =VIL, /CAS, Address Cycling : tPC = tPC min) -6 55 mA 1 mA mA ICC5 Standby Current (/RAS,/CAS >= Vcc – 0.2V) ICC6 /CAS before /RAS Refresh Current (tRC = tRC min) -5 85 -6 75 mA - - uA -5 5 uA -5 5 uA Self Refresh Current ICCS (/RAS=/UCAS=/LCAS=VIL, /WE=/OE=A0~A9= Vcc – 0.2V or 0.2V, DQ0~DQ31= Vcc – 0.2V, 0.2V or Open) Input Leakage Current II(L) IO(L) (Any Input (0V<=VIN<= VIN + 0.5V, All Other Pins Not Under Test = 0V) Output Leakage Current(DOUT is Disabled, 0V<=V OUT<= Vcc) URL:www.hbe.co.kr REV.1.0(August.2002) 2 HANBit Electronics Co.,Ltd. HANBit HMD1M4Z1 Note: 1. Icc depends on output load condition when the device is selected. Icc (max) is specified at the output open condition. 2. Address can be changed once or less while /RAS = VIL. 3. Address can be changed once or less while /CAS = V IH CAPACITANCE o ( TA=25 C, Vcc = 5V+/- 10%, f = 1Mhz ) DESCRIPTION SYMBOL MIN MAX UNITS NOTE Input Capacitance (A0-A9) CI1 - 5 pF 1 Input Capacitance (/WE,/RAS, /CAS0- C I2 - 7 pF 1,2 CDQ1 - 7 pF 1,2 /CAS3,/OE) Input/Output Capacitance (DQ0-31) Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. /CAS = VIH to disable DOUT. AC CHARACTERISTICS o ( 0 C ≤ TA ≤ 70oC , Vcc = 5V±10%, VIH /VIL = 2.4/0.8V, VOH /VOL =2.4/0.4V, See notes 1,2) -5 SYMBOL -6 PARAMETER UNIT MIN MAX MIN NOTE MAX tRC Random Read or Write Cycle Time 90 110 ns tRWC Read-modify-writer cycle time 132 152 ns tRAC Access Time from /RAS 50 60 ns 3,4,10 tCAC Access Time from /CAS 15 15 ns 3,4,5 taa Access Time from Column Address 25 30 ns 3,10 tOFF Output Buffer Turn-off Time 0 12 0 12 ns 6 tT Transition Time (Rise and Fall) 3 50 3 50 ns 2 tRP /RAS Precharge Time 30 tRAS /RAS Pulse Width 50 tRSH /RAS Hold Time 15 15 ns tCSH /CAS Hold Time 50 60 ns tCAS /CAS Pulse Width 15 10K 15 10K ns tRCD /RAS to /CAS Delay Time 20 35 20 45 ns 4 tRAD /RAS to Column Address Delay Time 15 25 15 30 ns 10 tCRP /CAS to /RAS Precharge Time 5 5 ns tASR Row Address Setup Time 0 0 ns tRAH Row Address Hold Time 10 10 ns tASC Column Address Setup Time 0 0 ns 11 tCAH Column Address Hold Time 10 10 ns 11 tRAL Column Address to /RAS Lead Time 25 30 ns tRCS Read Command Setup Time 0 0 ns URL:www.hbe.co.kr REV.1.0(August.2002) 40 10K 3 60 ns 10K ns HANBit Electronics Co.,Ltd. HANBit HMD1M4Z1 tRCH Read Command Hold Time to /CAS 0 0 ns 8 tRRH Read Command Hold Time to /RAS 0 0 ns 8 tWCH Write Command Hold Time 10 10 ns tWP Write Command Pulse Width 10 10 ns tRWL Write Command to /RAS Lead Time 15 15 ns tCWL Write Command to /CAS Lead Time 13 15 ns tDS Data-in Setup Time 0 0 ns 9 tDH Data-in Hold Time 10 10 ns 9 tREF Refresh Period (1024 Cycle) twcs Write Command Setup Time 0 0 ms 7 tCWD /CAS to /WE delay time 37 37 ms 7,13 tRWD /RAS to /WE delay time 72 82 ns 7 tAWD Column Address to /WE delay time 47 52 ns 7 tCPWD /CAS precharge to /WE delay time 52 57 ns 7 10 10 ns 10 10 ns 5 5 ns 16 16 ms /CAS Setup Time tCSR 15 (/CAS-before-/RAS Refresh Cycle) /CAS Hold Time tCHR 16 (/CAS-before-/RAS Refresh Cycle) tRPC /RAS Precharge to /CAS Hold Time tCPA Access Time from /CAS Precharge tPC Fast Page Mode Cycle Time 35 40 ns tCP Fast Page Mode /RAS Precharge Time 10 10 ns tRASP Fast Page Mode /CAS Pulse Time 50 /RAS tRHCP 30 200K 35 60 200K ns 3 12 ns Hold Time time from /CAS 30 35 ns Precharge tOEA /OE Access Time tOED /OE to data delay 15 12 15 12 ns 3 ns Output buffer turn off delay time from 0 tOEZ 12 0 12 ns /OE tOEH /OE command hold time 15 15 ns tRASS /RAS Pulse Width(CBR self refresh) 100 100 us tPRS /RAS Precharge Time(CBR self refresh) 90 110 ns tCHS /CAS Hold Time(CBR self refresh) -50 -50 ns Note: 1. An initial pause of 200us is required after power-up followed by any 8 /RAS-only refresh or /CAS-before-/RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are VIH / VIL. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also, transition times are measured between . VIH and VIL are assumed to be 5ns for all inputs. 3. Measured with a load circuit equivalent to 2TTL loads and 100pF. URL:www.hbe.co.kr REV.1.0(August.2002) 4 HANBit Electronics Co.,Ltd. HANBit HMD1M4Z1 4. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC . 5. Assumes that tRCD <= tRCD (max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH / VOL . 7. TWCS, TRWD, TCWD, TCPWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristics only. If twcs >= twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If tCWD >= tCWD (min), tRWD >= tRWD (min), TCPWD>= TCPWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycles. 9. These parameters are referenced to /CAS falling edge in early write cycles and to /WE falling edge in /OE controlled write cycle and read-modify-write cycles. 10. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 11. tASC, tCAH are are referenced to the earlier /CAS falling edge. 12. tCP is specified from the later /CAS rising edge in the previous cycle to the earlier /CAS falling edge in the next cycle. 13. tCWD is referenced to the later /CAS falling edge at word read-modify-write cycle. 14. tCWL is specified from /WE falling edge to the earlier /CAS rising edge . 15. tCSR is referenced to the earlier /CAS falling edge before /RAS transition low. 16. tCHR is referenced to the later /CAS rising edge after /RAS transition low. PACKAGING INFORMATION URL:www.hbe.co.kr REV.1.0(August.2002) 5 HANBit Electronics Co.,Ltd. HANBit HMD1M4Z1 1.94 ± 0.20 1.94 ± 0.20 1.27 ± 0.20 97. 80 ± 0. 20 1.8±0.30 mm 2.54 mm ORDERING INFORMATION Part Number Density Org. Package HMD1M4Z1-5 4Mbit 1M x 4Bit 20 Pin-ZIP HMD1M4Z1-6 4Mbit 1M x 4Bit 20 Pin-ZIP URL:www.hbe.co.kr REV.1.0(August.2002) 6 Component Vcc MODE SPEED 1EA 5V FP 50ns 1EA 5V FP 60ns Number HANBit Electronics Co.,Ltd.