SAMSUNG KM44C4003C

KM44C4003C, KM44C4103C
CMOS DRAM
4M x 4Bit CMOS Quad CAS DRAM with Fast Page Mode
DESCRIPTION
This is a family of 4,194,304 x 4 bit Quad CAS with Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access
of memory cells within the same row. Refresh cycle (2K Ref. or 4K Ref.), access time (-5 or -6), power consumption(Normal or Low
power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only
refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. Four separate CAS pins provide for
seperate I/O operation allowing this device to operate in parity mode.
This 4Mx4 Fast Page Mode Quad CAS DRAM family is fabricated using Samsung′s advanced CMOS process to realize high bandwidth, low power consumption and high reliability.
FEATURES
• Fast Page Mode operation
• Part Identification
• Four seperate CAS pins provide for separate I/O operation
• CAS-before-RAS refresh capability
- KM44C4003C/C-L (5V, 4K Ref.)
- KM44C4103C/C-L (5V, 2K Ref.)
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast paralleltest mode capability
• TTL compatible inputs and outputs
• Active Power Dissipation
Unit : mW
• Early Write or output enable controlled write
• JEDEC Standard pinout
Refresh Cycle
Speed
4K
2K
• Available in Plastic SOJ and TSOP(II) packages
• Single +5V±10% power supply
-5
495
605
-6
440
550
FUNCTIONAL BLOCK DIAGRAM
• Refresh Cycles
Refresh
cycle
Normal
Refresh period
C4003C
4K
64ms
C4103C
2K
32ms
L-ver
RAS
CAS0 - 3
W
Control
Clocks
Vcc
Vss
VBB Generator
128ms
Data in
Refresh Timer
Refresh Control
• Performance Range
Refresh Counter
Speed
tRAC
tCAC
tRC
tPC
Remark
-5
50ns
13ns
90ns
35ns
5V/3.3V
-6
60ns
15ns
110ns
40ns
5V/3.3V
A0-A11
(A0 - A10) *1
A0 - A9
(A0 - A10) *1
Memory Array
4,194,304 x 4
Cells
Row Address Buffer
Col. Address Buffer
Buffer
Row Decoder
Column Decoder
Note) *1 : 2K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
Sense Amps & I/O
Part
NO.
DQ0
to
DQ3
Data out
Buffer
OE
KM44C4003C, KM44C4103C
CMOS DRAM
PIN CONFIGURATION (Top Views)
• KM44C40(1)03CS
• KM44C40(1)03CK
VCC
DQ0
DQ1
W
RAS
*A11(N.C)
CAS0
CAS1
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
DQ3
DQ2
CAS3
OE
A9
CAS2
N.C
A8
A7
A6
A5
A4
VSS
VCC
DQ0
DQ1
W
RAS
*A11(N.C)
CAS0
CAS1
A10
A0
A1
A2
A3
VCC
*A11 is N.C for KM44C4103C(5V, 2K Ref. product)
K : 300mil 28 SOJ
S : 300mil 28 TSOP II
Pin Name
Pin Function
A0 - A11
Address Inputs (4K Product)
A0 - A10
Address Inputs (2K Product)
DQ0 - 3
Data In/Out
VSS
Ground
RAS
Row Address Strobe
CAS0~CAS3
Column Address Strobe
W
Read/Write Input
OE
Data Output Enable
VCC
Power(+5.0V)
N.C
No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
DQ3
DQ2
CAS3
OE
A9
CAS2
N.C
A8
A7
A6
A5
A4
VSS
KM44C4003C, KM44C4103C
CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Units
VIN, VOUT
-1.0 to +7.0
V
VCC Inputs
-1.0 to +7.0
V
Tstg
-55 to +150
°C
Power Dissipation
PD
1
W
Short Circuit Output Current
IOS
50
mA
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Units
Supply Voltage
VCC
4.5
5.0
5.5
V
Ground
VSS
0
0
0
V
Input High Voltage
VIH
2.4
-
VCC+1.0*1
V
Input Low Voltage
VIL
-1.0*2
-
0.8
V
*1 : VCC+2.0V/20ns, Pulse width is measured at VCC
*2 : -2.0/20ns, Pulse width is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0≤VIN≤VIN+0.5V,
all other input pins not under test=0 Volt)
II(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V≤VOUT ≤VCC)
IO(L)
-5
5
uA
Output High Voltage Level(IOH=-5mA)
VOH
2.4
-
V
Output Low Voltage Level(IOL=4.2mA)
VOL
-
0.4
V
KM44C4003C, KM44C4103C
CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol
Power
Speed
ICC1
Don′t care
ICC2
Max
Units
KM44C4003C
KM44C4103C
-5
-6
90
80
110
100
mA
mA
mA
Normal
L
Don′t care
2
1
2
1
mA
mA
ICC3
Don′t care
-5
-6
90
80
110
100
mA
mA
mA
ICC4
Don′t care
-5
-6
80
70
90
80
mA
mA
mA
ICC5
Normal
L
Don′t care
1
250
1
250
mA
uA
ICC6
Don′t care
-5
-6
90
80
110
100
mA
mA
mA
ICC7
L
Don′t care
300
300
uA
ICCS
L
Don′t care
250
250
uA
ICC1 * : Operating Current (RAS and CAS, Address cycling @tRC=min.)
ICC2 : Standby Current (RAS=CAS=W=VIH)
ICC3 * : RAS-only Refresh Current (CAS=VIH, RAS, Address cycling @tRC=min.)
ICC4 * : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @tPC=min.)
ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)
ICC6 * : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min.)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V,
DQ=Don′t care, TRC=31.25us(4K/L-ver), 62.5us(2K/L-ver), TRAS =TRAS min~300ns
ICCS : Self Refresh Current
RAS=CAS=0.2V, W=OE=A0 ~ A11=VCC-0.2V or 0.2V,
DQ0 ~ DQ3=VCC-0.2V, 0.2V or Open
*Note : ICC1 , ICC3 , ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1 , ICC3 and ICC6 address can be changed maximum once while RAS=VIL. In ICC4 ,
address can be changed maximum once within one fast page mode cycle time, tPC.
KM44C4003C, KM44C4103C
CMOS DRAM
CAPACITANCE (TA=25°C, VCC=5V, f=1MHz)
Parameter
Symbol
Min
Max
Units
Input capacitance [A0 ~ A11]
CIN1
-
5
pF
Input capacitance [RAS, CASx, W, OE]
CIN2
-
7
pF
Output capacitance [DQ0 - DQ3]
CDQ
-
7
pF
AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)
Test condition : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
Parameter
-5
Symbol
Min
-6
Max
Min
Units
Notes
Max
Random read or write cycle time
tRC
90
110
ns
Read-modify-write cycle time
tRWC
133
155
ns
Access time from RAS
tRAC
50
60
ns
3,4,10
Access time from CAS
tCAC
13
15
ns
3,4,5,18
Access time from column address
tAA
30
ns
3,10
CAS to output in Low-Z
tCLZ
0
ns
3,18
Output buffer turn-off delay
tOFF
0
13
0
15
ns
6
Transition time (rise and fall)
tT
3
50
3
50
ns
2
RAS precharge time
tRP
30
RAS pulse width
tRAS
50
RAS hold time
tRSH
13
15
ns
14
CAS hold time
tCSH
50
60
ns
17
CAS pulse width
tCAS
13
10K
15
10K
ns
23
RAS to CAS delay time
tRCD
20
37
20
45
ns
4,16
RAS to column address delay time
tRAD
15
25
15
30
ns
10
CAS to RAS precharge time
tCRP
5
5
ns
15
Row address set-up time
tASR
0
0
ns
Row address hold time
tRAH
10
10
ns
Column address set-up time
tASC
0
0
ns
16
Column address hold time
tCAH
10
10
ns
16
Column address to RAS lead time
tRAL
25
30
ns
Read command set-up time
tRCS
0
0
ns
Read command hold time referenced to
tRCH
0
0
ns
8,15
Read command hold time referenced to
tRRH
0
0
ns
8
Write command hold time
tWCH
10
10
ns
14
Write command pulse width
tWP
10
10
ns
Write command to RAS lead time
tRWL
13
15
ns
Write command to CAS lead time
tCWL
13
15
ns
25
0
40
10K
60
ns
10K
ns
17
KM44C4003C, KM44C4103C
CMOS DRAM
AC CHARACTERISTICS (Continued)
Parameter
-5
Symbol
Min
-6
Max
Min
Units
Notes
Max
Data set-up time
tDS
0
0
ns
9
Data hold time
tDH
10
10
ns
9
Refresh period (2K, Normal)
tREF
32
32
ms
Refresh period (4K, Normal)
tREF
64
64
ms
Refresh period (L-ver)
tREF
128
128
ms
Write command set-up time
tWCS
0
0
ns
7,16
CAS to W delay time
tCWD
36
40
ns
7,14
RAS to W delay time
tRWD
73
85
ns
7
Column address to W delay time
tAWD
48
55
ns
7
CAS precharge to W delay time
tCPWD
53
60
ns
7
CAS set-up time (CAS -before-RAS refresh)
tCSR
5
5
ns
16
CAS hold time (CAS -before-RAS refresh)
tCHR
10
10
ns
15
RAS to CAS precharge time
tRPC
5
5
ns
16
Access time from CAS precharge
tCPA
ns
3,15
Fast Page mode cycle time
tPC
35
40
ns
19
Fast Page read-modify-write cycle time
tPRWC
76
85
ns
19
CAS precharge time (Fast Page cycle)
tCP
10
ns
20
RAS pulse width (Fast Page cycle)
tRASP
50
RAS hold time from CAS precharge
tRHCP
30
OE access time
tOEA
OE to data delay
tOED
Output buffer turn off delay time from OE
30
35
10
200K
60
200K
35
13
13
ns
ns
15
15
ns
21
ns
22
ns
6
tOEZ
0
OE command hold time
tOEH
13
15
ns
Write command set-up time (Test mode in)
tWTS
10
10
ns
11
Write command hold time (Test mode in)
tWTH
10
10
ns
11
W to RAS precharge time(C-B-R refresh)
tWRP
10
10
ns
W to RAS hold time(C-B-R refresh)
tWRH
10
10
ns
13
0
15
RAS pulse width (C-B-R self refresh)
tRASS
100
100
us
25,26,27
RAS precharge time (C-B-R self refresh)
tRPS
90
110
ns
25,26,27
CAS hold time (C-B-R self refresh)
tCHS
-50
-50
ns
25,26,27
Hold time CAS low to CAS high
tCLCH
5
5
ns
13,24
KM44C4003C, KM44C4103C
CMOS DRAM
TEST MODE CYCLE
Parameter
( Note 11 )
-5
Symbol
Min
-6
Max
Min
Units
Notes
Max
Random read or write cycle time
tRC
95
115
ns
Read-modify-write cycle time
tRWC
138
160
ns
Access time from RAS
tRAC
55
65
ns
3,4,10,12
Access time from CAS
tCAC
18
20
ns
3,4,5,12
Access time from column address
tAA
30
35
ns
3,10,12
RAS pulse width
tRAS
55
10K
65
10K
ns
CAS pulse width
tCAS
18
10K
20
10K
ns
RAS hold time
tRSH
18
20
ns
CAS hold time
tCSH
55
65
ns
Column address to RAS lead time
tRAL
30
35
ns
CAS to W delay time
tCWD
41
45
ns
7
RAS to W delay time
tRWD
78
90
ns
7
Column address to W delay time
tAWD
53
60
ns
7
7
CAS precharge to W delay time
tCPWD
58
65
ns
Fast Page mode cycle time
tPC
40
45
ns
Fast Page read-modify-write cycle time
tPRWC
81
90
ns
RAS pulse width (Fast Page cycle)
tRASP
55
Access time from CAS precharge
tCPA
OE access time
tOEA
OE to data delay
OE command hold time
200K
65
35
18
200K
ns
40
ns
20
ns
tOED
18
20
ns
tOEH
18
20
ns
3
KM44C4003C, KM44C4103C
CMOS DRAM
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
4. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only.
If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC .
5. Assumes that tRCD ≥tRCD (max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
7. tWCS , tRWD , tCWD , tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If tWCS ≥tWCS (min), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD ≥tCWD (min), tRWD ≥tRWD (min), tAWD ≥tAWD (min) and tCPWD ≥tCPWD (min), then the cycle is a readmodify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions
is satisfied, the condition of the data out is indeterminate.
8. tRCH and tRRH must be satisfied for a read cycle.
9. These parameters are referenced to the first CAS falling edge in early write cycles and to W falling edge in OE controlled write
cycle and read-modify-write cycles.
10. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only.
If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA.
11. These specifications are applied in the test mode.
12. In test mode read cycle, the values of tRAC, tAA and tCAC are delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding 5ns to the specified value in this data sheet.
13. In order to hold the address latched by the first CAS going low, the parameter tCLCH must be met.
14. The last CASx edge to go low.
15. The last CASx edge to go high.
16. The first CASx edge to go low.
17. The first CASx edge to go high.
18. Output parameter is refrenced to corresponding CASx input.
19. The last rising CASx edge to next cycle′s last rising CASx edge.
20. The last rising CASx edge to first falling CASx edge.
21. The first DQx controlled by the first CASx to go low.
22. The last DQx controlled by the last CASx to go high.
23. Each CASx must meet minimum pulse width.
24. The last falling CASx edge to the first rising CASx edge.
25. If tRASS ≥100us, then RAS precharge time must use tRPS instead of tRP.
26. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be executed
within 64ms/32ms before and after self refresh, in order to meet refresh specification.
27. For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.
KM44C4003C, KM44C4103C
CMOS DRAM
READ CYCLE
NOTE : DOUT = OPEN
tRC
tRAS
RAS
tRP
VIH VIL -
tCSH
tCRP
CAS0
tRCD
tCRP
tRSH
VIH -
tCAS
VIL -
tCRP
CAS1
VIH VIL -
tCRP
CAS2
VIH VIL -
tCRP
CAS3
tCLCH
VIH VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tASC
ROW
ADDRESS
tRAL
tCAH
COLUMN
ADDRESS
tRCH
tRCS
W
tRRH
VIH VIL -
tROH
tAA
OE
VIH -
tOEZ
tOEA
VIL -
tOFF
tCAC
DQ0 ~ DQ3
VIH VIL -
tRAC
tCLZ
OPEN
DATA-OUT
tOLZ
Don′t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
WRITE CYCLE ( EARLY WRITE )
tRC
tRAS
RAS
tRP
VIH VIL -
tCSH
tCRP
CAS0
tRCD
tCRP
tRSH
tCAS
VIH VIL -
tCRP
CAS1
VIH VIL -
tCRP
CAS2
VIH VIL -
tCRP
CAS3
tCLCH
VIH VIL -
tCSH
tRAD
tASR
A
VIH VIL -
tRAH
tASC
ROW
ADDRESS
tRAL
tCAH
COLUMN
ADDRESS
tWCS
W
OE
VIH -
tWCH
tWP
VIL -
VIH VIL -
DQ0 ~ DQ3
VIH VIL -
tDS
tDH
DATA-IN
Don′t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
WRITE CYCLE ( OE CONTROLLED WRITE )
tRC
tRAS
RAS
tRP
VIH VIL -
tCSH
tCRP
CAS0
tCRP
tRCD
tRSH
VIH -
tCAS
VIL -
tCRP
CAS1
VIH VIL -
tCRP
CAS2
VIH VIL -
tCRP
CAS3
tCLCH
VIH VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tRAL
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tCWL
tRWL
W
OE
VIH -
tWP
VIL -
VIH VIL -
DQ0 ~ DQ3
VIH VIL -
tOED
tOEH
tDS
tDH
DATA-IN
Don′t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
READ - MODIFY - WRTIE CYCLE
tRC
tRAS
RAS
tRP
VIH VIL -
tCSH
tCRP
CAS0
tCRP
tRCD
tRSH
VIH -
tCAS
VIL -
tCRP
CAS1
VIH VIL -
tCRP
CAS2
VIH VIL -
tCRP
CAS3
tCLCH
VIH VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tRAL
tASC
tCAH
ROW
ADDRESS
COLUMN
ADDRESS
tRWL
tAWD
tCWD
W
tCWL
VIH -
tWP
VIL -
tRWD
OE
tOEA
VIH VIL -
tCLZ
tCAC
DQ0 ~ DQ3
VOH VOL -
tAA
tOED
tOEZ
tRAC
VALID
DATA-OUT
tDS
tDH
VALID
DATA-IN
tOLZ
Don′t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
FAST PAGE READ CYCLE
NOTE : DOUT = OPEN
tRP
tRASP
RAS
VIH -
tRHCP
VIL -
tCRP
CAS0
VIH -
tASC
tRSH
tCAS
¡ó
tCLCH
VIL VIH -
CAS2
tCP
tCAS
tCAS
VIL -
tPC
tCP
tRCD
VIH CAS1
¡ó
tPC
tCAS
VIL -
¡ó
VIH CAS3
tRAD
VIL -
¡ó
tCSH
tASR
A
VIH VIL -
ROW
ADDR
COLUMN
ADDRESS
tRCS
W
OE
tASC
tCAH
tRAH
tCAH
COLUMN
ADDRESS
tRCH
tRCS
VIH VIL -
tAA
tOEA
tAA
tCPA
VIH VIL -
tASC
¡ó
tCAH
COLUMN
ADDRESS
¡ó
tRRH
tRCH
tRCS
¡ó
¡ó
tRCH
tAA
tCPA
¡ó
tCAC
DQ0
DQ1
DQ2
DQ3
VIH -
tRAC
tCLZ
VALID
DATA-OUT
VIL VIH -
VIL VIH VIL -
tCLZ
¡ó
tOEZ
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
¡ó
tCLZ
tCLZ
VALID
DATA-OUT
tOLZ
tOEZ
tOEZ
tCLZ
VIL VIH -
tOEZ
¡ó
VALID
DATA-OUT
tCLZ
¡ó
VALID
DATA-OUT
Don′t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
FAST PAGE WRITE CYCLE ( EARLY WRITE )
tRP
tRASP
RAS
tRHCP
VIH VIL -
CAS0
CAS1
CAS2
CAS3
OE
tCAS
VIH -
VIH -
tCAS
tCAS
VIL -
¡ó
VIH -
VIH VIL -
tCAS
tRAD
tASC
VIL -
¡ó
tCSH
tCAH
tRAH
ROW
ADDR
tASC
COLUMN
ADDRESS
VIH -
tWCH
tCAH
COLUMN
ADDRESS
tWCS
tASC
¡ó
¡ó
tWCH
tWP
tCAH
COLUMN
ADDRESS
tWCS
¡ó
tWCH
tWP
tWP
VIL -
¡ó
VIH VIL -
¡ó
VIH VIL VIH VIL VIH VIL -
tDH
tDS
VIH VIL -
tDH
tDS
tDH
¡ó
VALID
DATA-IN
VALID
DATA-IN
¡ó
tDH
VALID
DATA-IN
tDS
tDH
¡ó
VALID
DATA-IN
tDH
¡ó
tDS
VALID
DATA-IN
tDH
¡ó
VALID
DATA-IN
VALID
DATA-IN
tDS
DQ3
tCAS
VIL -
tDS
DQ2
tCAS
¡ó
tCAS
tDS
DQ1
tRSH
¡ó
tDS
DQ0
tCP
tCAS
VIL -
tWCS
W
tPC
tCP
tRCD
VIH -
tASR
A
¡ó
tPC
tCRP
¡ó
tDH
¡ó
VALID
DATA-IN
¡ó
Don′t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
FAST PAGE READ - MODIFY - WRITE CYCLE
tRP
tRASP
RAS
VIH -
tPRWC
VIL -
tRSH
CAS0
CAS1
CAS2
CAS3
VIH -
VIH -
tCLCH
tCAS
VIL VIH -
tCAS
tCAS
VIL VIH -
tCAS
tCLCH
VIL -
VIH VIL -
tCSH
tRAD
tRAH
tASC
ROW
ADDR
tRAL
tCAH
tCAH
tASC
COL.
ADDR
COL.
ADDR
tRCS
W
tCAS
tCAS
VIL -
tASR
A
tRWL
tCWL
tCWL
VIH -
tWP
VIL -
tWP
tCWD
tCWD
tAWD
OE
tCRP
tCP
tRCD
tAWD
tRWD
tOEA
VIH -
tOEA
VIL -
tOED
tCAC
tCAC
tAA
DQ0 ~ DQ3
tRAC
tOEZ
tDH
tOED
tDH
tAA
tDS
tDS
tOEZ
VIH VIL -
tCLZ
tCLZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
Don′t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
RAS - ONLY REFRESH CYCLE
NOTE : W, OE, DIN = Don′t care
DOUT = OPEN
tRAS
RAS
tRC
tRP
VIH VIL -
tRPC
tCRP
CASX
VIH VIL -
tASR
A
tCRP
VIH VIL -
tRAH
ROW
ADDR
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Don′t care
tRC
tRP
RAS
tRAS
tRP
VIH VIL -
tRPC
tCP
CASX
tRPC
tCSR
VIH -
tWRP
W
tCHR
VIL -
tWRH
VIH VIL -
DQ0 ~ DQ3
VIH -
tOFF
OPEN
VIL Don′t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
HIDDEN REFRESH CYCLE ( READ )
tRC
tRC
tRP
tRAS
RAS
VIH VIL -
tCRP
CASX
tRP
tRAS
tRCD
tRSH
tCHR
VIH VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tASC
tCAH
COLUMN
ADDRESS
ROW
ADDRESS
tWRH
tRCS
W
VIH VIL -
tAA
OE
VIH -
tOEA
VIL -
tOFF
tCAC
tRAC
DQX
VIH VIL -
OPEN
tCLZ
tOEZ
DATA-OUT
Don′t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
RAS
VIH -
tRCD
tRSH
VIL -
OE
VIH VIL -
tRAH
tASC
tCAH
ROW
ADDRESS
COLUMN
ADDRESS
VIH -
tWCH
tWP
VIL -
VIH VIL -
tDS
DQX
tCHR
tRAD
tWCS
W
tRP
VIH -
tASR
A
tRAS
VIL -
tCRP
CASX
tRC
tRP
tRAS
VIH VIL -
tDH
DATA-IN
Don′t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don′t care
tRP
RAS
tRASS
tRPS
VIH VIL -
tRPC
tRPC
tCP
CASX
tCHS
VIH -
tCSR
VIL -
DQ0 ~ DQ3
VOH -
tOFF
OPEN
VOL -
TEST MODE IN CYCLE
NOTE : OE, A = Don′t care
tRC
tRP
RAS
tRAS
tRP
VIH VIL -
tRPC
tCP
CASX
tRPC
VIH -
tCSR
tWTS
W
tCHR
VIL -
tWTH
VIH VIL -
DQ0 ~ DQ3
VIH VIL -
tOFF
OPEN
Don′t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
PACKAGE DIMENSION
28 SOJ 300mil
Units : Inches (millimeters)
0.280 (7.11)
0.260 (6.61)
0.300 (7.62)
0.330 (8.39)
0.340 (8.63)
#28
0.006 (0.15)
0.012 (0.30)
#1
0.148 (3.76)
MAX
0.027 (0.69)
MIN
0.741 (18.82)
MAX
0.720 (18.30)
0.730 (18.54)
0.0375 (0.95)
0.050 (1.27)
0.026 (0.66)
0.032 (0.81)
0.015 (0.38)
0.021 (0.53)
28 TSOP(II) 300mil
0.300 (7.62)
0.355 (9.02)
0.371 (9.42)
Units : Inches (millimeters)
0.004 (0.10)
0.010 (0.25)
0.741 (18.81)
MAX
0.721 (18.31)
0.729 (18.51)
0.037 (0.95)
0.050 (1.27)
0.047 (1.20)
MAX
0.002 (0.05)
MIN
0.012 (0.30)
0.020 (0.50)
0.010 (0.25)
TYP
0.018 (0.45)
0.030 (0.75)
0~8
O