CMOS SRAM KM6264B Family 8Kx8 bit Low Power CMOS Static RAM FEATURE SUMMARY GENERAL DESCRIPTION • Process Technology : CMOS • Organization : 8K x 8 • Power Supply Voltage : Single 5V ± 10% • Low Data Retention Voltage : 2V(Min) • Three state output and TTL Compatible • Package Type : JEDEC Standard 28-DIP, 28-SOP The KM6264B family is fabricated by SAMSUNG's advanced CMOS process technology. The family can support various operating temperature ranges and has various package types for user flexibility of system design. The family also support low data retention voltage for battery back-up operations with low data retention current. PRODUCT FAMILY Product Family Operating Temperature KM6264BL Commercial KM6264BL-L (0~70 °C) KM6264BLE Extended KM6264BLE-L (-25~-85 °C) KM6264BLI Industrial KM6264BLI-L (-40~85 °C) Speed Power Dissipation PKG Type Standby(Isb1, Max) Operating(Icc2) 100uA 70/100/120ns 28-DIP, 28-SOP 10uA 100uA 100*ns 28-SOP 100*ns 28-SOP 55mA 50uA 100uA 50uA * measured with 30pF test load PIN DESCRIPTION FUNCTIONAL BLOCK DIAGRAM Y-Decoder 28 Vcc A12 2 27 /WE A7 3 26 CS2 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 /OE A2 8 21 A10 A1 9 20 /CS1 28-Pin DIP 28-Pin SOP A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 Vss 14 15 I/O4 A0~A12 Cell Array I/O1~8 1 I/O Buffer Control Logic 1 X-Decoder N.C /CS1, CS2 /WE, /OE Pin Name Function A0~A12 Address Inputs /WE Write Enable Input /CS1, CS2 Chip Select Input /OE Output Enable Input I/O1~I/O8 Data Input/Output Vcc Power(5V) Vss Ground N.C No Connection Revision. 0.0 Auust. 1996 ELECTRONICS CMOS SRAM KM6264B Family PRODUCT LIST & ORDERING INFORMATION PRODUCT LIST Extended Temp Products (-25~85 °C) Commercial Temp Products (0~70 °C) Part Name Function Part Name Function Industrial Temp Products (-40~85 °C) Part Name Function KM6264BLP-7 28-DIP, 70ns, L-pwr KM6264BLGE-10 28-SOP, 100ns, L-pwr KM6264BLGI-10 28-SOP, 100ns, L-pwr KM6264BLP-7L 28-DIP, 70ns, , LL-pwr KM6264BLGE-10L 28-SOP, 100ns, LL-pwr KM6264BLGI-10L 28-SOP, 100ns, LL-pwr KM6264BLP-10 28-DIP, 100ns, , L-pwr KM6264BLP-10L 28-DIP, 100ns, LL-pwr KM6264BLP-12 28-DIP, 120ns, , L-pwr KM6264BLP-12L 28-DIP, 120ns, LL-pwr KM6264BLG-7 28-SOP, 70ns, L-pwr KM6264BLG-7L 28-SOP, 70ns, LL-pwr KM6264BLG-10 28-SOP, 100ns, L-pwr KM6264BLG-10L 28-SOP, 100ns, LL-pwr KM6264BLG-12 28-SOP, 120ns, L-pwr KM6264BLG-12L 28-SOP, 120ns, LL-pwr ORDERING INFORMATION K M6 2 X 64 B X X XX - XX X L-Low Low Power, Blank-Low Power or High Power Access Time : 7=70ns, 10=100ns, 12=120ns Operating Temperature : I=Industrial, E=Extended, Blank=Commercial Package Type : G=SOP, P=DIP, L-Low Power or Low Low Power, Blank-High Power Die Version : B=3rd generation Density : 64=64K bit Blank=5V Organization : 2= x8 SEC Standard SRAM 2 Revision. 0.0 Auust. 1996 ELECTRONICS CMOS SRAM KM6264B Family ABSOLUTE MAXIMUM RATINGS * Item Ratings Symbol Unit Remark Voltage on any pin relative to Vss Vin, Vout -0.5 to Vcc+0.5 V - Voltage on Vcc supply relative to Vss Vcc -0.5 to 7.0 V - Power Dissipation Pd 1.0 W - Storage temperature Tstg -65 to 150 °C - Operating Temperature Ta 0 to 70 °C KM6264BL/L-L -25 to 85 °C KM6264BLE/LE-L -40 to 85 °C KM6264BLI/LI-L - - Soldering temperature and time Tsolder 260 °C, 10sec(Lead Only) * Stresses greater than those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS* Item Supply voltage Symbol Min Typ** Max Unit Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 V Input high voltage Vih 2.2 - Vcc+0.5 V Input low voltage Vil -0.5*** - 0.8 V * 1) Commercial Product : Ta=0 to 70 ° C, unless otherwise specified 2) Extended Product : Ta=-25 to 85 ° C, unless otherwise specified 3) Industrial Product : Ta=-40 to 85 ° C, unless otherwise specified ** Ta=25 ° C *** Vil(min)=-3.0V for ¡ Â50ns pulse CAPACITANCE * (f=1MHz, Ta=25 °C) Item Input capacitance Input/Output capacitance Symbol Test Condition Min Max Unit Cin Vin=0V - 6 pF Cio Vio=0V - 8 pF * Capacitance is sampled not 100% tested 3 Revision. 0.0 Auust. 1996 ELECTRONICS CMOS SRAM KM6264B Family DC AND OPERATING CHARACTERISTICS Item Symbol Test Conditions* Min Typ** Max Unit Input leakage current Ili Vin=Vss to Vcc -1 - 1 uA Output leakage current Ilo /CS1=Vih or CS2=Vil or /WE=Vil -1 - 1 uA Vi/o=Vss to Vcc Operating power supply current Icc /CS1=Vil, CS2=Vih - 7 15 mA Average operating current Icc1 Vin=Vil or Vih, Ii/o=0mA - - 10 mA - - 55 mA - - 0.4 V 2.4 - - V Cycle time=1us, 100% duty /CS1¡ Â0.2V, CS2 ¡ ÃVcc-0.2V Icc2 Min cycle, 100% duty /CS1=Vil, CS2=Vih, Ii/o=0mA Output low voltage Vol Iol=2.1mA Output high voltage Voh Ioh= -1.0mA Standby Current(TTL) Isb /CS1=Vih or CS2=Vil Standby Current (CMOS) - - 1 mA /CS1¡ ÃVcc-0.2V L - 2 100 uA CS2¡ ÃVcc-0.2V or LL - 1 10 uA KM6264BLE CS2 ¡ Â0.2V L - - 100 uA KM6264BLE-L Others 0~Vcc LL - - 50 uA KM6264BLI L - - 100 uA KM6264BLI-L LL - - 50 uA KM6264BL Isb1 KM6264BL-L * 1) Commercial Product : Ta=0 to 70 ° C, Vcc=5V+/-10%, unless otherwise specified 2) Extended Product : Ta=-25 to 85 ° C, Vcc=5V+/-10%, unless otherwise specified 3) Industrial Product : Ta=-40 to 85 ° C, Vcc=5V+/-10%, unless otherwise specified ** Ta=25 ° C A.C CHARACTERISTICS TEST CONDITIONS (1. Test Load and Test Input/Output Reference)* Item Value Input pulse level 0.8 to 2.4V Input rise fall time 5ns Remark - Input and output reference voltage 1.5V Output load(See right) CL=100pF+1TTL CL* * Including scope and jig capacitance * See test condition of DC and AC Operating characteristics 4 Revision. 0.0 Auust. 1996 ELECTRONICS CMOS SRAM KM6264B Family TEST CONDITIONS (2. Temperature and Vcc Conditions) Product Family Temperature Power Supply(Vcc) Speed Bin Comments KM6264BL/L-L 0~70 °C 5V +/- 10% 70/100/120ns Commercial KM6264BLE/LE-L -25~85 °C 5V +/- 10% 100*ns Extended KM6264BLI/LI-L -40~85 °C 5V +/- 10% 100*ns Industrial * measured with 30pF test load PARAMETER LIST FOR EACH SPEED BIN Speed Bins Parameter List Symbol 70ns 100ns 120ns Units Min Max Min Max Min Max Read Read cycle time Address access time tRC 70 - 100 - 120 - ns tAA - 70 - 100 - 120 ns Chip select to output tCO - 70 - 100 - 120 ns Output enable to valid output tOE - 35 - 50 - 60 ns Chip select to low-Z output tLZ 5 - 10 - 10 - ns tOLZ 5 - 5 - 5 - ns tHZ 0 30 0 35 0 40 ns 0 30 0 35 0 40 ns 10 - 10 - 10 - ns 70 - 100 - 120 - ns 60 - 80 - 85 - ns - 0 - 0 - ns Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output tOHZ Output hold from address change tOH Write Write cycle time tWC Chip select to end of write tCW Address set-up time tAS 0 Address valid to end of write tAW 60 - 80 - 85 - ns Write pulse width tWP 40 - 60 - 70 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 30 0 30 0 30 ns tDW 30 - 40 - 50 - ns tDH 0 - 0 - 0 - ns tOW 5 - 5 - 10 - ns Data to write time overlap Data hold from write time End write to output low-Z 5 Revision. 0.0 Auust. 1996 ELECTRONICS CMOS SRAM KM6264B Family DATA RETENTION CHARACTERISTICS Item Symbol Vcc for data retention Vdr Data retention current Idr Test Condition* /CS***¡ ÃVcc-0.2V L-Ver Vcc=3.0V KM6264BL Min Typ** Max Unit 2.0 - 5.5 - 1 50 LL-Ver - 0.5 5 KM6264BLE L-Ver - - 50 KM6264BLE-L LL-Ver - - 25 KM6264BLI L-Ver - - 50 KM6264BLI-L LL-Ver - - 25 See data retention 0 - - waveform 5 - - KM6264BL-L /CS¡ ÃVcc-0.2V Data retention set-up time tSDR Recovery time tRDR V uA ms * 1) Commercial Product : Ta=0 to 70 ° C, unless otherwise specified 2) Extended Product : Ta=-25 to 85 ° C, unless otherwise specified 3) Industrial Product : Ta=-40 to 85 ° C, unless otherwise specified ** Ta=25 ° C *** /CS1¡ ÃVcc-0.2, CS2 ¡ ÃVcc-0.2(/CS1 Controlled) or CS2 ¡ Ã0.2(CS2 Controlled) DATA RETENTION TIMING DIAGRAM 1) /CS1 controlled tSDR Data retention mode tRDR Vcc 4.5V 2.2V Vdr /CS1¡ ÃVcc-0.2V /CS1 GND 2) CS2 controlled Data retention mode Vcc 4.5V tRDR tSDR CS2 Vdr CS2¡ Â 0.2V 0.4V GND 6 Revision. 0.0 Auust. 1996 ELECTRONICS CMOS SRAM KM6264B Family TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE (1) (Address Controlled) (/CS=/OE=Vil, CS2=/WE=Vih) tRC Address tAA tOH Data Out Previous Data Valid Data Valid TIMING WAVEFORM OF READ CYCLE(2) (/WE= V IH) t RC Address t AA tCO1 t OH /CS1 CS2 tCO2 tHZ(1,2) t HZ tOE /OE t OLZ tOHZ t LZ Data out High - Z Data Vailid Notes(Read Cycle) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max) is less than tLZ(Min) both for a given device and device to device interconnection. 7 Revision. 0.0 Auust. 1996 ELECTRONICS CMOS SRAM KM6264B Family TIMING WAVEFORM OF WRITE CYCLE(1) (/WE Controlled) t WC Address t CW(2) t WR1(4) /CS t AW CS2 tCW(2) t WP(1) /WE t AS t DW Data in Data Vailid t OW t WHZ Data out t DH Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (/CS1 Controlled) t WC Address t AS t WR1(4) t CW(2) /CS1 t AW CS2 tCO2 t WP(1) /WE t DW Data in Data out t DH Data Vailid High - Z High - Z 8 Revision. 0.0 Auust. 1996 ELECTRONICS CMOS SRAM KM6264B Family TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled) t WC Address t WR2(4) t CW(2) tAS(3) /CS1 t AW CS2 t CW(2) t WP(1) /WE t DH t DW Data in Data Vailid Data out High - Z High - Z Notes(Write Cycle) 1. A write occurs during the overlap of a low /CS1, a high CS2 and a low /WE. A write begins at the latest transition among /CS1 going low, CS2 going high and /WE going low. A write ends at the earliest transition among /CS1 going high, CS2 going low and /WE going high, tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of /CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends at /CS1, or /WE going high, tWR2 applied in case a write ends at CS2 going to low. FUNCTIONAL DESCRIPTION /CS1 CS2 /WE /OE Mode I/O Pin Current Mode H X X X Power Down High-Z Isb, Isb1 X L X X Power Down High-Z Isb, Isb1 L H H H Output Disable High-Z Icc L H H L Read Dout Icc L H L X Write Din Icc * X means don't care 9 Revision. 0.0 Auust. 1996 ELECTRONICS CMOS SRAM KM6264B Family Unit : Millimeters (Inches) PACKAGE DIMENSION 28 PIN PLASTIC SMALL OUTLINE PACKAGE (450mil ) 0 ~ 8° #15 #28 11.81 ± 0.30 0.465 ± 0.012 8.38 ± 0.20 0.330 ± 0.008 #1 1.02 ± 0.20 0.040 ± 0.008 #14 18.69 MAX 0.736 1.27 0.050 0.15 0.006 + 0.10 - 0.05 + 0.004 - 0.002 2.59 ± 0.20 0.102 ± 0.008 18.29 ± 0.20 0.720 ± 0.008 0.89 0.41 ± 0.10 0.035 0.016 ± 0.004 28 PIN PLASTIC DUAL INLINE PACKAGE 3.00 MAX 0.118 0.05 MIN 0.002 0.10 MAX 0.004 (600mil) 36.72 MAX 1.446 0 ~ 15° #15 13.60 ± 0.20 0.535 ± 0.008 #28 #1 15.24 0.600 #14 3.81 ± 0.20 0.150 ± 0.008 36.32 ± 0.20 1.430 ± 0.008 + 0.10 0.25 - 0.05 + 0.004 0.010 - 0.002 5.08 MAX 0.200 3.30 ± 0.30 0.130 ± 0.012 1.65 0.065 2.54 0.100 0.38 MIN 0.015 0.46 ± 0.10 0.018 ± 0.004 1.52 ± 0.10 0.060 ± 0.004 10 Revision. 0.0 Auust. 1996 ELECTRONICS