KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD GENERAL DESCRIPTION 48-QFP-0707 The KS7212 is a CMOS integrated circuit designed for making various timing pulses for B/W CCD camera. FEATURES - Compatible with both EIA and CCIR mode (EIA : KC73125(U)-M, CCIR : KC73129(U)-M) - Built in auto iris function (Electronic Exposure) - Mirror mode timing generation - Field interlace mode only - Timing and sync one chip IC - Oscillation frequency EIA : 19.06992MHz, CCIR : 18.93750MHz ORDERING INFORMATION APPLICATION - B/W CCD Camera Device KS7212 Package 48-QFP-0707 Operating Temperature -20~75°C ϕH1 ϕH2 RG XSUB XV2 XV1 XSG1 XV3 37 36 35 33 30 29 28 27 26 25 XV4 ϕH3 38 XSG3 ϕH4 BLOCK DIAGRAM 24 CL 43 1/2 X2 41 X1 40 GATE1 1/606 Horizontal ROM F/F TS2 45 GATE2 TS1 46 TS0 47 PWR 48 1/525 or 1/625 Vertical ROM F/F High/Low Control Shutter Speed Count Shutter Speed Control 1 2 3 4 7 8 9 10 11 12 MD2 MD1 EE1 EE2 FLD PBLK CSYNC CBLK VD HD Shutter Speed ROM 22 SHP 21 SHD 18 CLP1 17 CLP2 16 CLP3 15 DFDO 14 CLEN 13 WIN KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD PIN DESCRIPTIONS No Symbol I/O Description Remark 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 MD2 MD1 EE1 EE2 VSS1 VDD1 FLD PBLK CSYNC CBLK VD HD WIN CLEN DFDO CLP3 CLP2 CLP1 VSS2 VDD2 SHD SHP VSS3 XV4 XSG3 V3 XSG1 XV1 XV2 XSUB VDD3 VSS4 ϕRG VDD4 ϕH2 ϕH1 ϕH3 ϕH4 VSS5 I I I I O O O O O O O O O O O O O O O O O O O O O O O O O O - * Information (1) * Information (1) * Information (2) * Information (2) 40 X1 I 41 42 X2 VDD5 O O 43 CL O 44 45 46 47 48 VSS6 TS2 TS1 TS0 PWR I I I - CCIR/EIA mode selection NORMAL/MIRROR mode selection EE mode control input 1 EE mode control input 2 Ground +5V Field separation pulse Pre - blanking pulse Composite Sync.pulse Composite Blanking pulse Vertical driving pulse Horizontal driving pulse Window pulse 1/2 HD frequency pulse 1/2 VD frequency pulse Clamp pulse 3 (Dummy black level) Clamp pulse 2 (Optical black level) Clamp pulse 1 (Optical black level) Ground +5V Data Sample & Hold pulse Pre - Charge Sample & Hold pulse Ground Vertical transfer clock 4 Read out Pulse 3 Vertical transfer clock 3 Read out Pulse 1 Vertical transfer clock 1 Vertical transfer clock 2 Shutter speed control for auto Iris +5V Ground Reset gate pulse +5V Horizontal transfer pulse 2 ( Mirror mode) Horizontal transfer pulse 1 ( Normal mode’H’) Horizontal transfer pulse 3 ( Normal mode’H2’) Horizontal transfer pulse 4 ( Mirror mode ) Ground Oscillation clock Input EIA : 19,069928MIHz CCIR : 18.93750MHz Oscillation clock Output +5V 1/2 Oscillation clock EIA : 9.953496Mhz CCIR : 9.46875MHz Ground Test Input 2 Test Input 1 Test Input 0 Power On Reset KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD Information 1) MD2 and MD1 mode selection ( Pull - down ) MD2 L H MD1 L H L H MODE EIA NORMAL EIA MIRROR CCIR NORMAL CCIR MIRROR Information 2 ) EE2 and EE1 shutter speed mode selection ( Pull- up ) EE2 L H EE1 L H L H MODE SHUTTER SPEED STOP SHUTTER SPEED UP SHUTTER SPEED DOWN SHUTTER SPEED STOP ABSOLUTE MAXIMUM RATINGS Characteristics Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Symbol Value Unit VCC VI VO T OPR T STG 7 VSS-0.5 ~ VDD+0.5 VSS-0.5 ~ VDD+0.5 -20 ~ +75 -55 ~ +150 V V V °C °C ELECTRICAL CHARACTERISTICS (VDD=5V, Ta=25°C, unless otherwise specified) Characteristics Supply Voltage Input Voltage Output Voltage 1 Output Voltage 2 (CL, RG, SHP, SHD) Output Voltage 3 (H1, H2, H3, H4) Symbol VDD VIH VIL VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 Test Condition IOH1=-2mA ICL1=4mA ICH2=-4mA IOL2=3mA ICH3=-8mA ICL3=8mA Min 4.75 0.7VDD VDD-0.5 VDD-0.5 VDD-0.5 - Typ 5.0 - Max 5.25 0.3VDD 0.4 0.4 0.4 Unit V V V V V V V V V KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD AC CHARACTERISTICS tr tf twh 90% 0.9VDD twl 10% twh twl 0.1VDD tr tf Unit PULSES Min. XSG1 , XSG3 2.3 Typ. Max. Min. Typ. Max. Min. 2.5 XV1 , XV2 , XV3 , XV4 H1 , H2 , H3 , H4 26 32 RG 11 13 XSUB 1.5 2.0 SHP , SHD , CLP1 , CLP2 , CLP3 , DFD0 , CLEN , WIN , HD , VD , CBLK , CSYNC , FLD 26 Typ. Max. Min. Typ. Max. 0.5 0.5 us 0.015 0.24 us 32 11 51 5 11 12 5 0.5 13 14 12 16 13 14 ns ns 0.5 us 16 ns KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD OPERATING PRINCIPLES & METHOD POWER ON RESET KS7212 has two reset methods. The one is power on reset and the other is normal reset. When user wants to use power on reset , which generates automatical reset signal that is needed to initialize the KS7212 internal system when power is on, user should be connect 1000pF capacitor at PWR ( pin 48 ) termial. Power on reset system has internal 100Kohm pull up resister. So , user can control reset signal timing when user changes value of capacitor , which is connected to PWR terminal. When user wants to use normal reset , user should be remove capacitor from PWR terminal , and supplies reset signal to PWR terminal. 48 KS7212 RESET SIGNAL 48 KS7212 1000pF 2.4 ~ 2.6 V 840ns Fig. 1 POWER ON RESET When use u-Com system , reset signal can be should be larger than four times of CL clock. Fig. 2 NORMAL RESET supplied three times and times of 1 signal KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD APPLICATION CIRCUIT ( EIA , NORMAL mode ) TO VERTICAL DRIVER TO CCD VDD 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 40 19.0699MHz X-tal 21 KS7212 41 42 19 TIMING & SYNC GEN 43 17 45 16 46 15 47 14 48 13 2 3 4 5 6 7 8 9 10 11 12 TO SIGNAL PROCESSOR VDD Application circuit for EIA : 19.06992MHz CCIR : 18.93750MHz 18 44 1 * 20 normal mode KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD HIGH SPEED TIMING RELATIONSHIP X1 H1 PG CCD OUT SHP SHD V4 V3 V2 V1 V4 V3 V2 XSG2 XSG1 EVEN ODD V1 HD 43.5uS 39.5uS 2.5uS 1.1uS 2.5uS 2.0uS UNIT : µS CCD VERTICAL DRIVING PULSE TIMING DIAGRAM KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD FLD EVEN VD ODD VD VSYNC EQSYNC HSYNC HBLK HD 2.45 1.47 4.89 10.76 6.36 26.89 1/2H 4.86 UNIT uS KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD FLD EVEN VD ODD VD VSYNC EQSYNC HSYNC HBLK HD 1.48 2.47 4.93 11.70 6.41 27.07 1/2H 4.93 HORIZONTAL TIMING CHART FOR CCIR UNIT uS KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD CLP3 CLP2 CLP1 ODD VD VSYNC EQSYNC HSYNC HBLK HD 2.724 2.45 4.89 10.76 6.36 26.89 1/2H 4.86 UNIT uS HORIZONTAL TIMING CHART FOR MIRROR EIA MODE KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD CLP3 CLP2 CLP1 ODD VD VSYNC EQSYNC HSYNC HBLK HD 2.745 2.47 4.93 11.70 6.41 27.07 1/2H 4.93 UNIT uS HORIZONTAL TIMING CHART FOR MIRROR CCIR MODE KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD SHD SHP PG H4 H3 H2 H1 OSC1 H1, H2, H3, H4, PG, SHP, SHD TIMING CHART AT MIRROR MODE OF CCIR KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD WIN FLD CBLK CSYNC VD HD WIN FLD CBLK CSYNC VD HD FIELD O FIELD E 9H 9H FIELD E FIELD O 20H 20H 80.5H 80H EIA VERTICAL TIMING CHART KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD WIN FLD CBLK CSYNC VD HD WIN FLD CBLK CSYNC VD HD FIELD O FIELD E 7.5H FIELD E 7.5H FIELD O 25H 25H 96.5H 97H CCIR VERTICAL TIMING CHART KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD PBLK CLP3 CLP2 24 6 10 1 35 135 246 15 CLP1 5 4 3 2 1 525 491 492 492 493 13 5 24 6 13 57 2 46 8 280 CCD OUT V4 V3 V2 V1 XSG2 XSG1 HD BLK VD FLD VERTICAL TIMING CHART FOR EIA KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD 290 285 275 270 265 260 25 20 520 PBLK CLP3 CLP2 24 6 10 1 35 135 246 15 CLP1 5 4 3 2 1 625 582 581 582 583 135 2 46 13 5 7 24 68 330 CCD OUT V4 V3 V2 V1 XSG2 XSG1 HD BLK VD FLD VERTICAL TIMING CHART FOR CCIR KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD 340 335 325 320 315 310 25 20 620 KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD PACKAGE DIMENSION 48-QFP-0707 unit : mm 9.00 + − 0.30 0~ 8 7.00 + − 0.20 0.1 3 + 0 7.00 −+ 0.20 0.10 MAX 0.50 −+ 0.20 9.00 −+ 0.30 - 0 .10 .05 # 48 #1 ( 0.75 ) 0.18 + − 0.10 0.50 0.10 MAX 0.00 MIN 1.40 + − 0.10 1.60 MAX