CXP85112B/85116B CXP85220A/85224A/85228A/85232A CMOS 8-bit Single-chip Microcomputer Description The CXP85112B/85116B, CXP85220A/85224A/ 85228A/85232A is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, vector interruption, on-screen display function, I2C bus interface, PWM generator, remote control reception circuit, HSYNC counter, power source frequency counter and watch dog timer besides the basic configurations of 8-bit CPU, ROM, RAM, and l/O port. The CXP85112B/85116B, CXP85220A/85224A/ 85228A/85232A also provides a power-on reset function and a sleep function that enables lower power consumption. 64 pin SDIP (Plastic) 64 pin QFP (Plastic) Structure Silicon gate CMOS IC Features • Wide-range instruction system (213 instructions) to cover various types of data — 16-bit arithmetic/multiplication and division/boolean bit operation instructions • Minimum instruction cycle 1µs at 4MHz operation • Incorporated ROM capacity 12K bytes (CXP85112B) 16K bytes (CXP85116B) 20K bytes (CXP85220A) 24K bytes (CXP85224A) 28K bytes (CXP85228A) 32K bytes (CXP85232A) • Incorporated RAM capacity 352 bytes (CXP85112B/85116B) 448 bytes (CXP85220A/85224A/85228A/85232A) • Peripheral functions — On-screen display function 12 × 16 dots, 128 types 21 words × 4 Iines (more than 4 Iines possible) Double scan mode compatible, jitter elimination circuit — I2C bus interface — PWM output 14 bits, 1 channel 6 bits, 8 channels — Remote control reception circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO — A/D converter 4 bits, 4channels, successive approximation method (Conversion time of 40µs/4MHz) — HSYNC counter — Power supply frequency counter — Watch dog timer — Serial I/O 8-bit clock synchronization — Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer • Interruption 14 factors, 14 vectors, multi-interruption possible • Standby mode Sleep • Package 64-pin plastic SDIP/QFP • Piggyback/evaluation chip CXP85100A, CXP85190 (Custom font compatible) CXP85200A, CXP85290 (Custom font compatible) Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E93Z17B86 HSYNC COUNTER AC TIMER A/D CONVERTER I2C INTERFACE UNIT PD4/HSI PD5/ACI PE2/AN0 to PE5/AN3 PF4/SCL0 PF5/SCL1 PF6/SDA0 PF7/SDA1 FIFO TIMER/COUNTER PD7/EC PE7/TO REMOCON SERIAL I/O PD3/SI PD2/SO PD1/SCK PD6/RMC ON SCREEN DISPLAY 2 2 PE0/INT0 SPC700 CPU CORE ROM 12K/16K/20K/24K/28K/32K BYTES 6 BIT PWM 8CH 14 BIT PWM WATCH DOG TIMER PD0/INT2 PE6/PWM EXLC XLC B G R BLK HSYNC VSYNC PE1/INT1 INTERRUPT CONTROLLER PF0/PWM0 to PF7/PWM7 VDD VSS RST MP XTAL EXTAL PRESCALER/ TIME BASE TIMER RAM 352/448 BYTES CLOCK GEN./ SYSTEM CONTROL PORT A PF0 to PF7 PE6 to PE7 PE0 to PE5 PD0 to PD7 PB0 to PB7 PA0 to PA7 PC0 to PC7 PORT B PORT C PORT D PORT E –2– PORT F Block Diagram CXP85112B/85116B, CXP85220A/85224A/85228A/85232A CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Pin Assignment 1 (Top View) 64 pin SDIP Package PA7 1 64 VDD PA6 2 63 NC PA5 3 62 VSS PA4 4 61 MP PA3 5 60 PF0/PWM0 PA2 6 59 PF1/PWM1 PA1 7 58 PF2/PWM2 PA0 8 57 PF3/PWM3 PB7 9 56 PF4/PWM4/SCL0 PB6 10 55 PF5/PWM5/SCL1 PB5 11 54 PF6/PWM6/SDA0 PB4 12 53 PF7/PWM7/SDA1 PB3 13 52 BLK PB2 14 51 R PB1 15 50 G PB0 16 49 B PC7 17 48 VSYNC PC6 18 47 HSYNC PC5 19 46 EXLC PC4 20 45 XLC PC3 21 44 PE0/INT0 PC2 22 43 PE1/INT1 PC1 23 42 PE2/AN0 PC0 24 41 PE3/AN1 PD7/EC 25 40 PE4/AN2 PD6/RMC 26 39 PE5/AN3 PD5/ACI 27 38 PE6/PWM PD4/HSI 28 37 PE7/TO PD3/SI 29 36 RST PD2/SO 30 35 EXTAL PD1/SCK 31 34 XTAL VSS 32 33 PD0/INT2 Note) 1. NC (Pin 63) must be connected to VDD. 2. Vss for both Pins 32 and 62 must be grounded. 3. MP (Pin 61) must be connected to GND. –3– CXP85112B/85116B, CXP85220A/85224A/85228A/85232A PF2/PWM2 PF1/PWM1 PF0/PWM0 MP NC VDD VSS PA7 PA6 PA5 PA4 PA2 PA3 Pin Assignment 2 (Top View) 64 pin QFP Package 64 63 62 61 60 59 58 57 56 55 54 53 52 PA1 1 51 PF3/PWM3 PA0 2 50 PF4/PWM4/SCL0 PB7 3 49 PF5/PWM5/SCL1 PB6 4 48 PF6/PWM6/SDA0 PB5 5 47 PF7/PWM7/SDA1 PB4 6 46 BLK PB3 7 45 R PB2 8 44 G PB1 9 43 B PB0 10 42 VSYNC PC7 11 41 HSYNC PC6 12 40 EXLC PC5 13 39 XLC PC4 14 38 PE0/INT0 PC3 15 37 PE1/INT1 PC2 16 36 PE2/AN0 PC1 17 35 PE3/AN1 PC0 18 34 PE4/AN2 PD7/EC 19 33 PE5/AN3 Note) PE7/TO PE6/PWM RST EXTAL XTAL PD0/INT2 VSS PD1/SCK PD2/SO PD3/SI PD4/HSI PD5/ACI PD6/RMC 20 21 22 23 24 25 26 27 28 29 30 31 32 1. NC (Pin 56) must be connected to VDD. 2. Vss for both Pins 26 and 58 must be grounded. 3. MP (Pin 55) must be connected to GND. –4– CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Pin Description Symbol I/O Description PA0 to PA7 I/O (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) PB0 to PB7 I/O (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) PC0 to PC7 I/O (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) PD0/INT2 I/O/Input PD1/SCK I/O/I/O PD2/SO I/O/Output PD3/SI I/O/Input PD4/HSI I/O/Input PD5/ACI I/O/Input PD6/RMC I/O/Input Input for remote control reception circuit. PD7/EC I/O/Input External event input for timer/counter. PE0/INT0 PE1/INT1 Input/Input External interruption request inputs. Active at falling edge. (2 pins) PE2/AN0 to PE5/AN3 Input/Input PE6/PWM Output/Output PE7/TO Output/Output PF0/PWM0 to PF3/PWM3 Output/Output PF4/PWM4/ SCL0 PF5/PWM5/ SCL1 Output/Output/ I/O PF6/PWM6/ SDA0 PF7/PWM7/ SDA1 Output/Output/ I/O R, G, B, BLK Output 4-bit outputs for CRT display. HSYNC Input Horizontal synchronizing signal input for CRT display. VSYNC Input Vertical synchronizing signal input for CRT display. External interruption request input. Active at falling edge. (Port D) 8-bit I/O port. I/O can be set ina a unit of single bits. Capable of driving 12mA sink current. (8 pins) Serial clock I/O. Serial data output. Serial data input. HSYNC counter input. Input for power supply frequency counter. (Port E) Analog inputs for A/D converter. 8-bit port. Lower (4 pins) 6 bits are for inputs; upper 2 bits are for 14-bit PWM output. outputs. (CMOS output) Rectangular waveform output for Timer 1. (Duty output 50%) (Port F) 6-bit PWM outputs. 8-bit output port, (8 pins) operating as N-ch open drain output for high current Transfer clock I/Os for I2C bus (12mA). interface. Lower 4 bits are medium voltage drive outputs (12V), upper 4bits are 5V Transfer data I/Os for I2C data bus. drive outputs. (8 pins) –5– CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Symbol I/O Description EXLC Input XLC Output EXTAL Input XTAL Output RST I/O Low-level active, system reset. RST is an I/O, from whlch Low level is output when the built-in power-on reset function is activated at the rise of power on. (Mask option) MP Input Microprocessor mode input. For this device, this pin must be grounded. Clock oscillation I/Os for CRT display. Oscillation frequency is set using the external L and C. Crystai connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. VDD Vcc supply. Vss GND. Both Vss must be grounded. –6– CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Input/Output Circuit Formats for Pins Pin Circuit format Port A Port B Port C PA0 to PA7 PB0 to PB7 PC0 to PC7 AAAA AAAA AAAA AAAA Data for Ports A, B, and C Direction for Ports A, B, and C Data bus RD (Ports A, B, and C) 24 pins Port D PD0/INT2 PD3/SI PD4/HSI PD5/ACI PD6/RMC PD7/EC When reset AA AA AA Input protection circuit IP AAAA AAAA AAAA Port D data Port D direction Hi-Z AA AA AA AA High current 12mA Hi-Z IP Data bus RD (Port D) INT2, SI, HSI, ACI, RMC, EC Schmitt input 6 pins Port D SCK or SO Output eneble AAAA AAAA PD1/SCK PD2/SO AA AA AA AA High current 12mA Port D data IP Port D direction Schmitt input Data bus RD (Port D) SCK only 2 pins –7– Hi-Z CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Pin Port E PE0/INT0 PE1/INT1 AAAA Circuit format When reset Schmitt input (To interruption circuit) IP Hi-Z Data bus 2 pins RD (Port E) Port E PE2/AN0 to PE5/AN3 AA A AAA Input multiplexer To A/D converter IP Hi-Z Data bus 4 pins RD (Port E) Port E PE6/PWM PE7/TO AAAA AAAA AAAA AA AA TO, PWM Port E data 2 pins Port selection High level Port F PWM PF0/PWM0 to PF3/PWM3 AAAAA AAAAA AAAAA AA AA AA AA Middle tension proof 12V Port F data High current 12mA Port selection 4 pins Port F SCL, SDA PF4/PWM4/ SCL0 PF5/PWM5/ SCL1 PF6/PWM6/ SDA0 PF7/PWM7/ SDA1 I2C output enable AAAA AAAA AAAA AA AA PWM Port F data Port selection Hi-Z IP Schmitt input SCL, SDA (To I2C circuit) 4 pins Hi-Z BUS SW To other I2C pins –8– CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Pin BLK R G B 4 pins Circuit format When reset AAAA AAAA AA BLK, R, G, B Output polarity Hi-Z → output active by writing into the output polarity register. AAA AAAAAA AAAA AA AA AA AA AA A AA A Hi-Z Schmitt input HSYNC VSYNC 2 pins EXLC XLC EXTAL XTAL 2 pins RST 1 pin MP EXLC IP Oscillation control Oscillation terminated CRT display clock IP AA AA AA AA A A EXTAL • Diagram shows circuit composition during oscillation. IP • Feedback resistor is removed during stop. Oscillation XTAL AA AA AAAA Mask option OP Pull-up resistance Schmitt input Low level From power-on reset circuit (Mask option) CPU mode IP 1 pin Hi-Z Input polarity XLC 2 pins HSYNC VSYNC IP –9– Hi-Z CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Absolute Maximum Ratings Item (Vss = 0V reference) Symbol Rating Unit V Remarks Supply voltage VDD Input voltage VIN –0.3 to +7.0 –0.3 to +7.0∗1 Output voltage VOUT –0.3 to +7.0∗1 V Medium voltage drive output voltage VOUTP –0.3 to +15.0 V High level output current IOH –5 mA High level total output current ∑IOH –50 mA Total for all output pins IOL 15 mA IOLC 20 mA Excludes high current outputs High current outputs∗2 Low level total output current ∑IOL 130 mA Total for all output pins Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD 1000 mW SDIP 600 mW QFP Low level output current V Pins PF0 to PF3 ∗1 VIN and VOUT must not exceed VDD + 0.3V. ∗2 The high current operation transistor is the N-ch transistor of PD and PF0 to PF3. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Supply voltage High level input voltage (Vss = 0V reference) Symbol Min. Max. Unit 4.5 5.5 V Guaranteed operation range 3.5 5.5 V Low-speed mode guaranteed operation range∗1 2.5 5.5 V VIH 0.7VDD VDD V VIHS 0.8VDD VDD V VDD VIHEX Low level input voltage Operating temperature VDD – 0.4 VDD + 0.3 V Remarks Guaranteed data hold range during stop Includes I2C Schmitt input∗2 CMOS Schmitt input∗3 EXTAL∗4 VIL 0 0.3VDD V VILS 0 0.2VDD V Includes I2C Schmitt input∗2 CMOS Schmitt input∗3 VILEX –0.3 0.4 V EXTAL∗4 Topr –20 +75 °C ∗1 Specifies only for 1/16 frequency demultiplication mode and sleep mode. ∗2 Value for each pin of normal input ports (PA, PB, PC, PE2 to PE5), PF4 to PF7, and MP. ∗3 Value of the following pins: PD0/lNT2, PD1/SCK, PD2, PD3/Sl, PD4/HSl, PD5/ACI, PD6/RMC, PD7/EC, PE0/INT0, PE1/lNT1, HSYNC, VSYNC, RST. ∗4 Specifies only during external clock input. – 10 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Electrical Characteristics DC Characteristics Item High level output current Low level output current (Ta = –20 to +75°C, Vss = 0V reference) Symbol VOH VOL IIHE Input current Pins Conditions Min. PA to PD, PE6, PE7, R, G, B, BLK VDD = 4.5V, IOH = –0.5mA 4.0 V VDD = 4.5V, IOH = –1.2mA 3.5 V PA to PD, PE6, PE7, R, G, B, BLK, PF0 to PF3, RST∗1 VDD = 4.5V, IOL = 1.8mA 0.4 V VDD = 4.5V, IOL = 3.6mA 0.6 V PD, PF0 to PF3 VDD = 4.5V, IOL = 12.0mA 1.5 V PF4 to PF7 (SCL0, SCL1, SDA0, SDA1) VDD = 4.5V, IOL = 3.0mA 0.4 V VDD = 4.5V, IOL = 4.0mA 0.6 V EXTAL IIHL Typ. Max. Unit VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA –1.5 –400 µA IILR RST∗2 VDD = 5.5V, VIL = 0.4V I/O leakage current IIZ PA to PE, HSYNC, VSYNC, R, G, B, BLK, RST∗2, MP VDD = 5.5V VI = 0, 5.5V ±10 µA Open drain output leakage current (N-ch Tr in off state) PF0 to PF3 VDD = 5.5V, VOH = 12.0V 50 µA ILOH PF4 to PF7 VDD = 5.5V, VOH = 5.5V 10 µA SCL0: SCL1 SDA0: SDA1 VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V 120 Ω 8 20 mA 0.5 2 mA — — µA 10 20 pF Impedance connected RBS to I2C bus switch (output Tr in off state) IDD VDD∗3 Power supply current Operation mode∗3 (1/2 frequency demultiplier clock) 4MHz crystal oscillation (C1 = C2 = 22pF) All outputs open IDDSL Sleep mode Stop mode∗4 IDDST Input capacity CIN Pins other than VDD and Vss Clock 1MHz 0V for all pins excluding — ∗1 RST specifies only when the power-on reset circuit has been selected througn mask option. ∗2 RST specifies input current when the pull-up resistance has been selected; Ieakage current when no resistance has been selected. ∗3 Specifies only when the oscillatlon of OSD has been terminated. ∗4 This device does not enter the stop mode. – 11 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A AC Characteristics (1) Clock timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol System clock frequency fC System clock input pulse width tXL, tXH tCR, tCF tEH, tEL tER, tEF System clock input rise time, fall time Event clock input clock pulse width Event count input clock rise time, fall time Pins Conditions Min. Max. Unit 4.5 MHz XTAL EXTAL Fig. 1, Fig. 2 3.5 EXTAL Fig. 1, Fig. 2 External clock drive 100 EXTAL Fig. 1, Fig. 2 External clock drive EC Fig. 3 EC Fig. 3 ns 200 tsys + 50∗1 ns ns 20 ms ∗1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (address: 00FEH). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 1. Clock timing AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA Crystal oscillation Ceramic oscillation EXTAL External clock EXTAL XTAL C1 C2 XTAL OPEN Fig. 2. Clock applying condition 0.8VDD EC 0.2VDD tEH tEF tEL Fig. 3. Event count clock timing – 12 – tER CXP85112B/85116B, CXP85220A/85224A/85228A/85232A (2) Serial transfer Item SCK cycle time (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol tKCY Pins SCK Conditions Min. tKH tKL SCK SI input setup time (for SCK ↑) tSIK SI SI input hold time (for SCK ↑) tKSI ns 8000/fc ns 400 ns 4000/fc – 50 ns SCK input mode 100 ns SCK output mode 200 ns SCK input mode 200 ns SCK output mode 100 ns SCK ↓ → SO delay time tKSO SCK input mode SCK output mode SI SO SCK input mode 200 ns SCK output mode 100 ns Note) The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL. tKCY tKL tKH 0.8VDD SCK 0.2VDD tSIK tKSI 0.8VDD SI Unit 1000 Input mode Output mode SCK High and Low level widths Max. Input data 0.2VDD tKSO 0.8VDD SO Output data 0.2VDD Fig. 4. Serial transfer timing – 13 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A (3) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol External interruption High and Low level widths Reset input Low level width tIH tIL tRSL Pins Conditions INT0 to INT2 RST Min. Max. Unit 1 µs 8/fc µs tIH tIL 0.8VDD INT0 to INT2 (Falling edge) 0.2VDD Fig. 5. Interruption input timing tRSL RST 0.2VDD Fig. 6. RST input timing (4) Power on reset Power on reset∗ (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins tR tOFF Power supply rise time Power supply cut-off time VDD Conditions Power-on reset Repetitive power-on reset Min. Max. Unit 0.05 50 ms 1 ms ∗ Specifies only when the power-on reset function has been selected. VDD 4.5V 0.2V 0.2V tR tOFF The power supply should be raised smoothly. Fig. 7. Power-on reset – 14 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A (5) A/D converter characteristics Item Symbol (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Max. Unit Resolution 4 Bits Linearity error ±1 LSB Zero transition voltage VZT∗1 Full-scale transition voltage VFT∗2 Conversion time Sampling time tCONV tSAMP Analog input voltage VIAN Pin Condition Ta = 25°C VDD = 5.0V Vss = 0V AN0 to AN3 Min. Typ. –10 160 320 mV 4370 4530 4690 mV 160/fc µs 12/fc µs 0 VDD V Digital conversion value FH EH ∗1 VZT: Value at which the digital conversion value changes from 0H to 1H and vice versa. ∗2 VFT: Value at which the digital conversion value changes from EH to FH and vice versa. Linearity error 1H 0H VZT VFT Analog input Fig. 8. Definition of A/D converter terms Note) The 4-bit conversion specifies values based on the upper 5 bits of the A/D data register (ADD: Address 00F5H), compensated into 4-bit data. A program example is shown below: (A/D converter program example) MOV A, ADD LSR A LSR A LSR A LSR A ADC A, #00H CMP A, #10H BNE ADC_SKIP MOV A, #0FH ADC_SKIP: ; ACC ← conversion data ; Shift to the right (4 times) ; ; ; ; Addition with carry (data increment if AD3 = 1) ; ; ; – 15 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A (6) I2C bus timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins Conditions Min. Max. Unit 0 100 kHz SCL clock frequency fSLC SCL Bus free time prior to transfer start tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO SDA, SCL 4.7 µs SDA, SCL 4.0 µs SCL 4.7 µs SCL 4.0 µs SDA, SCL µs SDA, SCL 4.7 0∗1 SDA, SCL 250 ns Transfer start hold time Clock Low level width Clock High level width Setup time during repetitive transfer Data hold time Data setup time SDA, SCL rise time SDA, SCL fall time Transfer end setup time µs SDA, SCL 1 µs SDA, SCL 300 ns SDA, SCL 4.7 µs ∗1 The data hold time does not take into consideration SCL rise time (300ns max.). Ensure that the data hold time exceeds 300ns. SDA tBUF tR tF tHD; STA SCL tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH St tSU; DAT tSU; STO P Fig. 9. I2C bus transfer timing I2C device RS I2C device RS RS R S RP RP SDA0 (or SDA1) SCL0 (or SCL1) Fig. 10. Recommended circuit example for I2C device • Pull-up resistors (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). • Serial resistance (Rs = 300Ω and under) of SDA0 (or SDA1) and SCL0 (or SCL1) reduces spike noise caused by CRT flashover. – 16 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A (7) OSD (On-Screen Display) timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins Condition Min. Max. Unit EXLC XLC Fig. 12 4 13 MHz OSD clock frequency fOSC HSYNC pulse width tHWD tVWD HSYNC Fig. 11 1.2 µs VSYNC Fig. 11 1.0 H* HSYNC after-edge rise time/fall time tHCG HSYNC Fig. 11 200 ns VSYNC after-edge rise time/fall time tVCG VSYNC Fig. 11 1.0 µs VSYNC pulse width * H indicates 1HSYNC period. tHWD tHCG 0.8VDD HSYNC when Bit 5 of OPOL register (01FBH) is set to "0" 0.2VDD tVWD tVCG 0.8VDD VSYNC when Bit 4 of OPOL register (01FBH) is set to "0" 0.2VDD Fig. 11. OSC timing EXLC XLC L C1 C2 Fig. 12. LC oscillation circuit example – 17 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Supplement AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA (i) EXTAL (ii) EXTAL XTAL Rd C1 XTAL Rd C2 C1 C2 Fig. 13. Recommended Oscillation circuit Model Manufacturer MURATA MFG CO., LTD. RIVER ELETEC CORPORATION KINSEKI LTD. C1 (pF) fc (MHz) CSA4.00MG 4.00 CSA4.19MG 4.19 CST4.00MGW∗ 4.00 CST4.19MGW∗ 4.19 Rd (Ω) 30 30 0 (ii) 10 10 0 4.19 (i) 4.00 HC-49/U (-S) 18 4.19 ∗ Indicates types with on-chip grounding capacitance (C1 and C2). Mask option table Item Circuit example (i) 4.00 HC-49/U03 C2 (pF) Content Reset pin pull-up resistance Non-existent Existent Power-on reset circuit Non-existent Existent – 18 – 18 0 CXP85112B/85116B, CXP85220A/85224A/85228A/85232A IDD vs. VDD IDD vs. fc (fc = 4MHz, Ta = 25°C typical) (VDD = 5V, Ta = 25°C typical) 12 15 1/2 frequency demultiplication mode 10 10 1 Sleep mode 9 IDD – Power supply current [mA] IDD – Power supply current [mA] 1/4 frequency demultiplication mode 1/16 frequency demultiplication mode 1/2 frequency demultiplication mode 11 8 7 1/4 frequency demultiplication mode 6 5 4 3 1/16 frequency demultiplication mode 2 0.1 1 Sleep mode 0 2 3 4 5 6 1 OSD oscillation vs. C Calculated curves (reference value by theoretical calculation) L – Inductasce [µH] 100 5.0MHz 6.5MHz 10 13.0MHz 1 0 1 2π LC 3 4 5 6 fc – System clock [MHz] VDD – Supply voltage [V] fosc = 2 C = C1//C2 50 100 C1, C2 – Capacitance [pF] Fig. 14. Characteristics curves – 19 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Unit: mm + 0.1 0.05 0.25 – 64PIN SDIP (PLASTIC) + 0.4 57.6 – 0.1 64 19.05 + 0.3 17.1 – 0.1 33 1 0° to 15° 32 3.0 MIN 0.5 MIN + 0.4 4.75 – 0.1 1.778 0.5 ± 0.1 0.9 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SDIP-64P-01 LEAD TREATMENT SOLDER PLATING EIAJ CODE SDIP064-P-0750 LEAD MATERIAL 42 ALLOY PACKAGE MASS 8.6g JEDEC CODE 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.1 0.15 – 0.05 0.15 32 64 20 1 16.3 52 17.9 ± 0.4 33 + 0.2 0.1 – 0.05 19 + 0.35 2.75 – 0.15 + 0.15 0.4 – 0.1 1.0 0.2 M 0° to10° 0.8 ± 0.2 51 + 0.4 14.0 – 0.1 Package Outline PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING SONY CODE QFP-64P-L01 LEAD TREATMENT EIAJ CODE QFP064-P-1420 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 1.5g JEDEC CODE – 20 –