SAMSUNG M393T6553BZ3

512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
DDR2 Registered SDRAM MODULE
240pin Registered Module based on 512Mb B-die
72-bit ECC
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
DDR2 Registered DIMM Ordering Information
Part Number
Density
Organization
Component Composition
Number of Rank
Height
M393T6553BG(Z)3-CD5/CC
512MB
64Mx72
64Mx8(K4T51083QB)*9EA
1
30mm
M393T6553BG(Z)0-CD5/CC
512MB
64Mx72
64Mx8(K4T51083QB)*9EA
1
30mm
M393T2953BG(Z)3-CD5/CC
1GB
128Mx72
64Mx8(K4T51083QB)*18EA
2
30mm
M393T2953BG(Z)0-CD5/CC
1GB
128Mx72
64Mx8(K4T51083QB)*18EA
2
30mm
M393T2950BG(Z)3-CD5/CC
1GB
128Mx72
128Mx4(K4T51043QB)*18EA
1
30mm
M393T2950BG(Z)0-CD5/CC
1GB
128Mx72
128Mx4(K4T51043QB)*18EA
1
30mm
M393T5750BS(Y)3-CD5/CC
2GB
256Mx72
128Mx4(K4T51043QB)*36EA
2
30mm
M393T5750BS(Y)0-CD5/CC
2GB
256Mx72
128Mx4(K4T51043QB)*36EA
2
30mm
Note: “Z” and “Y” of Part number(11th digit) stand for Lead-free products.
Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.
Features
• Performance range
D5(DDR2-533)
CC(DDR2-400)
Unit
Speed@CL3
400
400
Mbps
Speed@CL4
533
400
Mbps
Speed@CL5
-
-
Mbps
CL-tRCD-tRP
4-4-4
3-3-3
CK
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95°C
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA - 128Mx4/64Mx8
• All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
Address Configuration
Organization
Row Address
Column Address
Bank Address
128Mx4(512Mb) based Module
A0-A13
A0-A9,A11
BA0-BA1
Auto Precharge
A10
64Mx8(512Mb) based Module
A0-A13
A0-A9
BA0-BA1
A10
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Pin Configurations (Front side/Back side)
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
1
VREF
121
VSS
31
DQ19
151
VSS
61
A4
181
VDDQ
91
VSS
211
DM5/DQS14
NC/DQS14
2
VSS
122
DQ4
32
VSS
152
DQ28
62
VDDQ
182
A3
92
DQS5
212
3
DQ0
123
DQ5
33
DQ24
153
DQ29
63
A2
183
A1
93
DQS5
213
VSS
4
DQ1
124
VSS
34
DQ25
154
VSS
64
VDD
184
VDD
94
VSS
214
DQ46
DQ47
5
VSS
125
DM0/DQS9
35
VSS
155
DM3/DQS12
95
DQ42
215
6
DQS0
126
NC/DQS9
36
DQS3
156
NC/DQS12
65
VSS
185
CK0
96
DQ43
216
VSS
7
DQS0
127
VSS
37
DQS3
157
VSS
66
VSS
186
CK0
97
VSS
217
DQ52
DQ53
KEY
8
VSS
128
DQ6
38
VSS
158
DQ30
67
VDD
187
VDD
98
DQ48
218
9
DQ2
129
DQ7
39
DQ26
159
DQ31
68
NC/Par_In
188
A0
99
DQ49
219
VSS
10
DQ3
130
VSS
40
DQ27
160
VSS
69
VDD
189
VDD
100
VSS
220
RFU
RFU
11
VSS
131
DQ12
41
VSS
161
CB4
70
A10/AP
190
BA1
101
SA2
221
12
DQ8
132
DQ13
42
CB0
162
CB5
71
BA0
191
VDDQ
102
NC(TEST)
222
VSS
13
DQ9
133
VSS
43
CB1
163
VSS
72
VDDQ
192
RAS
103
VSS
223
DM6/DQS15
NC/DQS15
14
VSS
134
DM1/DQS10
44
VSS
164
DM8/DQS17
73
WE
193
S0
104
DQS6
224
15
DQS1
135
NC/DQS10
45
DQS8
165
NC/DQS17
74
CAS
194
VDDQ
105
DQS6
225
VSS
16
DQS1
136
VSS
46
DQS8
166
VSS
75
VDDQ
195
ODT0
106
VSS
226
DQ54
17
VSS
137
RFU
47
VSS
167
CB6
76
S14
196
A13
107
DQ50
227
DQ55
18
RESET
138
RFU
48
CB2
168
CB7
77
ODT1
197
VDD
108
DQ51
228
VSS
19
NC
139
VSS
49
CB3
169
VSS
78
VDDQ
198
VSS
109
VSS
229
DQ60
DQ61
20
VSS
140
DQ14
50
VSS
170
VDDQ
79
VSS
199
DQ36
110
DQ56
230
21
DQ10
141
DQ15
51
VDDQ
171
80
DQ32
200
DQ37
111
DQ57
231
VSS
22
DQ11
142
VSS
52
CKE0
172
CKE14
VDD
81
DQ33
201
VSS
112
VSS
232
DM7/DQS16
NC/DQS16
23
VSS
143
DQ20
53
VDD
173
NC
82
VSS
202
DM4/DQS13
113
DQS7
233
24
DQ16
144
DQ21
54
NC
174
83
DQS4
203
NC/DQS13
114
DQS7
234
VSS
25
DQ17
145
VSS
55
NC/Err_Out
175
NC
VDDQ
84
DQS4
204
VSS
115
VSS
235
DQ62
DQ63
26
VSS
146
DM2/DQS11
56
VDDQ
176
A12
85
VSS
205
DQ38
116
DQ58
236
27
DQS2
147
NC/DQS11
57
A11
177
A9
86
DQ34
206
DQ39
117
DQ59
237
VSS
28
DQS2
148
VSS
58
A7
178
VDD
87
DQ35
207
VSS
118
VSS
238
VDDSPD
29
VSS
149
DQ22
59
VDD
179
A8
88
VSS
208
DQ44
119
SDA
239
SA0
30
DQ18
150
DQ23
60
A5
180
A6
89
DQ40
209
120
SCL
240
SA1
90
DQ41
210
DQ45
VSS
NC = No Connect, RFU = Reserved for Future Use
1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.
2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)
3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity.
4. CKE1,S1 Pin is used for double side Registered DIMM.
Pin Description
Pin Name
CK0
CK0
CKE0, CKE1
Description
On die termination
Clock inputs, negative line
DQ0~DQ63
Data Input/Output
Clock Enables
CB0~CB7
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
S0, S1
Chip Selects
Address Inputs
Data strobes
DQS0~DQS8
Data strobes, negative line
DM(0~8),DQS(9~17) Data Masks / Data strobes (Read)
DQS9~DQS17
RFU
Address Input/Autoprecharge
NC
BA0, BA1
DDR2 SDRAM Bank Address
TEST
SCL
Serial Presence Detect (SPD) Clock Input
SDA
SPD Data Input/Output
Data check bits Input/Output
DQS0~DQS8
A10/AP
SA0~SA2
Description
ODT0~ODT1
RAS
A0~A9, A11~A13
Pin Name
Clock Inputs, positive line
VDD
VDDQ
Data strobes (Read), negative line
Reserved for Future Use
No Connect
Memory bus test tool
(Not Connect and Not Useable on DIMMs)
Core Power
I/O Power
SPD address
VSS
Ground
Par_In
Parity bit for the Address and Control bus
VREF
Input/Output Reference
Err_Out
Parity error found in the Address and Control bus
RESET
Register and PLL control pin
VDDSPD
SPD Power
*The VDD and VDDQ pins are tied to the single power-plane on PCB.
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Input/Output Functional Description
Symbol
Type
Function
CK0
Input
CK0
Input
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.
CKE0~CKE1
Input
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low
initiates the Power Down mode, or the Self Refresh mode.
S0~S1
Input
Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is disabled, new commands are ignored but previous operations continue.
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are
high.
ODT0~ODT1
Input
I/O bus impedance control signals.
RAS, CAS, WE
Input
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the
SDRAM.
VREF
Supply
Reference voltage for SSTL_18 inputs
VDDQ
Supply
Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity
BA0~BA1
Input
Selects which SDRAM bank of four is activated.
A0~A9,A10/AP
A11~A13
Input
During a Bank Activate command cycle, Address defines the row address.
During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is
used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is
selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge
command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks
will be precharged regardless of the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge.
DQ0~63,
CB0~CB7
In/Out
Data and Check Bit Input/Output pins
DM0~DM8
Input
Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once
the write command is registered into the SDRAM.
VDD, VSS
Supply
Power and ground for the DDR SDRAM input buffers and core logic
DQS0~DQS17
In/Out
Positive line of the differential data strobe for input and output data.
DQS0~DQS17
In/Out
Negative line of the differential data strobe for input and output data.
SA0~SA2
Input
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range.
SDA
In/Out
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA
bus line to VDDSPD to act as a pullup.
SCL
Input
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time
to VDDSPD to act as a pullup.
VDDSPD
Supply
RESET
Input
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to
3.6 Volt operation).
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs
will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchronized with the input clock )
Par_In
Input
Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even)
Err_Out
Input
Parity error found in the Address and Control bus
TEST
In/Out
Used by memory bus analysis tools (unused on memory DIMMs)
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Functional Block Diagram: 512MB, 64Mx72 Module(populated as 1 rank of x8 DDR2 SDRAMs)
M393T6553BG(Z)3 / M393T6553BG(Z)0
RS0
DQS0
DQS0
DM0/DQS9
NC/DQS9
DQS4
DQS4
DM4/DQS13
NC/DQS13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
DQS1
DQS1
DM1/DQS10
NC/DQS10
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
D4
DQS5
DQS5
DM5/DQS14
NC/DQS14
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
DQS2
DQS2
DM2/DQS11
NC/DQS11
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
D5
DQS6
DQS6
DM6/DQS15
NC/DQS15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
DQS3
DQS3
DM3/DQS12
NC/DQS12
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
D6
DQS7
DQS7
DM7/DQS16
NC/DQS16
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
DQS8
DQS8
DM8/DQS17
NC/DQS17
Serial PD
SCL
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
D8
1:1
R
E
G
I
S
T
E
R
RESET
RST
A1
A2
SA0 SA1 SA2
CK0
CK0
RESET
S0*
BA0-BA1
A0-A13
RAS
CAS
WE
CKE0
ODT0
SDA
WP A0
P
L
L
OE
RSO-> CS : DDR2 SDRAMs D0-D8
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D8
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D8
RRAS -> RAS : DDR2 SDRAMs D0-D8
RCAS -> CAS : DDR2 SDRAMs D0-D8
RWE -> WE : DDR2 SDRAMs D0-D8
RCKE0 -> CKE : DDR2 SDRAMs D0-D8
RODT0 -> ODT0 : DDR2 SDRAMs D0-D8
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
D7
VDDSPD
Serial PD
VDD/VDDQ
D0 - D8
VREF
D0 - D8
VSS
D0 - D8
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK7 -> CK : Register
PCK7 -> CK : Register
Notes :
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. Unless otherwise noted, resister values are 22 Ohms
* S0 connects to DCS and VDD connects to CSR on the register.
PCK7
PCK7
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Functional Block Diagram: 1GB, 128Mx72 Module(populated as 2 rank of x8 DDR2 SDRAMs)
M393T2953BG(Z)3 / M393T2953BG(Z)0
RS1
RS0
DQS0
DQS0
DM0/DQS9
NC/DQS9
DQS4
DQS4
DM4/DQS13
NC/DQS13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
DQS DQS
DM/ NU/ CS
RDQS RDQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D9
DQS1
DQS1
DM1/DQS10
NC/DQS10
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
DQS DQS
D13
DQS5
DQS5
DM5/DQS14
NC/DQS14
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
DQS DQS
D10
DQS2
DQS2
DM2/DQS11
NC/DQS11
DM/ NU/ CS
RDQS RDQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
DQS DQS
D14
DQS6
DQS6
DM6/DQS15
NC/DQS15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
DQS DQS
D11
DQS3
DQS3
DM3/DQS12
NC/DQS12
DM/ NU/ CS
RDQS RDQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
DQS DQS
D15
DQS7
DQS7
DM7/DQS16
NC/DQS16
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
DQS DQS
D12
DQS8
DQS8
DM8/DQS17
NC/DQS17
DM/ NU/ CS
RDQS RDQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D7
Serial PD
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
S0*
S1*
BA0-BA1
A0-A13
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1:2
R
E
G
I
S
T
E
R
RESET**
RST
PCK7**
D8
DQS DQS
DM/ NU/ CS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
SCL
SDA
WP A0
D17
A1
A2
SA0 SA1 SA2
CK0
P
L
L
DM/ NU/ CS
RDQS RDQS
DQS DQS
D16
VDDSPD
Serial PD
VDD/VDDQ
D0 - D17
VREF
D0 - D17
VSS
D0 - D17
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17
CK0
PCK7 -> CK : Register
RSO-> CS : DDR2 SDRAMs D0-D8
OE
RESET
PCK7 -> CK : Register
RS1-> CS : DDR2 SDRAMs D9-D17
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D17
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17
RRAS -> RAS : DDR2 SDRAMs D0-D17
RCAS -> CAS : DDR2 SDRAMs D0-D17
Notes :
RWE -> WE : DDR2 SDRAMs D0-D17
1. DQ-to-I/O wiring may be changed per nibble.
RCKE0 -> CKE : DDR2 SDRAMs D0-D8
2. Unless otherwise noted, resister values are 22 Ohms
RCKE1 -> CKE : DDR2 SDRAMs D9-D17
3. RS0 and RS1 alternate between the back and front sides of the DIMM
RODT0 -> ODT0 : DDR2 SDRAMs D0-D8
RODT1 -> ODT1 : DDR2 SDRAMs D9-D17
* S0 connects to DCS and S0 connects to CSR on a Register, S1 connects to DCS and S0 connects to CSR on another Register.
** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.
PCK7**
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Functional Block Diagram: 1GB, 128Mx72 Module(populated as 1 rank of x4 DDR2 SDRAMs)
M393T2950BG(Z)3 / M393T2950BG(Z)0
VSS
RS0
DM0/DQS9
NC/DQS9
DQS0
DQS0
DM
DQ0
DQ1
DQ2
DQ3
DQS1
DQS1
I/O 0
I/O 1
I/O 2
I/O 3
DM
DQ8
DQ9
DQ10
DQ11
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
D0
CS
DQS DQS
D1
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
D3
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DQ36
DQ37
DQ38
DQ39
D4
DQS5
DQS5
CS
DQS DQS
D10
CS
DQS DQS
D11
CS
DQS DQS
D12
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
D13
DM5/DQS14
NC/DQS14
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
DM
DQ44
DQ45
DQ46
DQ47
D5
DQS6
DQS6
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
D14
Serial PD
DM6/DQS15
NC/DQS15
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
SCL
DM
DQ52
DQ53
DQ54
DQ55
D6
DQS7
DQS7
I/O 0
I/O 1
I/O 2
I/O 3
CS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
DM
DQ60
DQ61
DQ62
DQ63
D7
DQS8
DQS8
D15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
RST
PCK7**
PCK7**
A2
CS
D8
DQS DQS
DM
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
VDDSPD
Serial PD
VDD/VDDQ
D0 - D17
VREF
D0 - D17
VSS
D0 - D17
D16
CS
DQS DQS
D17
CK0
1:2
R
E
G
I
S
T
E
R
RESET**
A1
SA0 SA1 SA2
DM8/DQS17
NC/DQS17
DM
S0*
BA0-BA1
A0-A13
RAS
CAS
WE
CKE0
ODT0
SDA
WP A0
DQS DQS
DM7DQS16
NC/DQS16
DM
CB0
CB1
CB2
CB3
D9
DM4/DQS13
NC/DQS13
DM
DQ56
DQ57
DQ58
DQ59
I/O 0
I/O 1
I/O 2
I/O 3
DM
DQ28
DQ29
DQ30
DQ31
DQS4
DQS4
DQ48
DQ49
DQ50
DQ51
DQS DQS
DM3/DQS12
NC/DQS12
DM
DQ40
DQ41
DQ42
DQ43
DM
DQ20
DQ21
DQ22
DQ23
D2
DQS3
DQS3
DQ32
DQ33
DQ34
DQ35
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM2/DQS11
NC/DQS11
DM
DQ24
DQ25
DQ26
DQ27
I/O 0
I/O 1
I/O 2
I/O 3
DM
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2
DQ16
DQ17
DQ18
DQ19
DM
DQ4
DQ5
DQ6
DQ7
DM1/DQS10
NC/DQS10
RSO-> CS : DDR2 SDRAMs D0-D17
CK0
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D17
RESET
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17
RRAS -> RAS : DDR2 SDRAMs D0-D17
RCAS -> CAS : DDR2 SDRAMs D0-D17
RWE -> WE : DDR2 SDRAMs D0-D17
RCKE0 -> CKE : DDR2 SDRAMs D0-D17
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17
P
L
L
OE
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK7 -> CK : Register
PCK7 -> CK : Register
Notes :
1. DQ-to-I/O wiring may be changed per nibble.
2. Unless otherwise noted, resister values are 22 Ohms
* S0 connects to DCS of Register1, CSR of Register2. CSR of register 1 and DCS of register 2 connects to VDD
** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Functional Block Diagram: 2GB, 256Mx72 Module(populated as 2 rank of x4 DDR2 SDRAMs)
M393T5750BS(Y)3 / M393T5750BS(Y)0
VSS
RS1
RS0
DM0/DQS9
NC/DQS9
DQS0
DQS0
DM
DQ0
DQ1
DQ2
DQ3
DQS1
DQS1
CS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DQ8
DQ9
DQ10
DQ11
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQS DQS
DM/
I/O 0
I/O 1
I/O 2
I/O 3
D0
DQS DQS
DM/
I/O 0
I/O 1
I/O 2
I/O 3
D1
CS
DQS DQS
DM
DQ4
DQ5
DQ6
DQ7
DM1/DQS10
NC/DQS10
D18
CS
DQS DQS
DM
DQ12
DQ13
DQ14
DQ15
D19
DQS2
DQS2
DQ16
DQ17
DQ18
DQ19
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQS DQS
DM/
I/O 0
I/O 1
I/O 2
I/O 3
D2
CS
DQS DQS
DM
DQ20
DQ21
DQ22
DQ23
D20
DQS3
DQS3
DM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
D3
CS
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DQ28
DQ29
DQ30
DQ31
D21
DQS4
DQS4
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
D10
CS
DQS DQS
D27
CS
DQS DQS
D28
CS
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
D11
CS
DQS DQS
D29
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
D12
CS
DQS DQS
D30
DM4/DQS13
NC/DQS13
DM
DQ32
DQ33
DQ34
DQ35
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
D4
CS
DQS DQS
DM
DQ36
DQ37
DQ38
DQ39
D22
DQS5
DQS5
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
D13
CS
DQS DQS
D31
DM5/DQS14
NC/DQS14
DM
DQ40
DQ41
DQ42
DQ43
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
D5
CS
DQS DQS
DM
DQ44
DQ45
DQ46
DQ47
D23
DQS6
DQS6
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
D14
CS
DQS DQS
D32
DM6/DQS15
NC/DQS15
DM
DQ48
DQ49
DQ50
DQ51
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
D6
CS
DQS DQS
DM
DQ52
DQ53
DQ54
DQ55
D24
DQS7
DQS7
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
D15
CS
DQS DQS
D33
DM7DQS16
NC/DQS16
DM
DQ56
DQ57
DQ58
DQ59
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
D7
CS
DQS DQS
DM
DQ60
DQ61
DQ62
DQ63
D25
DQS8
DQS8
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
D16
CS
DQS DQS
D34
DM8/DQS17
NC/DQS17
DM
CB0
CB1
CB2
CB3
CS
I/O 0
I/O 1
I/O 2
I/O 3
S0*
D8
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
DM
CB4
CB5
CB6
CB7
D26
Serial PD
RSO-> CS : DDR2 SDRAMs D0-D17
1:2
R
E
G
I
S
T
E
R
RST
PCK7**
DQS DQS
D9
DM3/DQS12
NC/DQS12
DQ24
DQ25
DQ26
DQ27
PCK7**
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM2/DQS11
NC/DQS11
DM
S1*
BA0-BA1
A0-A13
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
RESET**
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
D17
VDDSPD
CS
DQS DQS
D35
Serial PD
SCL
SDA V /V
RS1-> CS : DDR2 SDRAMs D18-D35
D0 - D35
DD DDQ
WP A0 A1 A2
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D35
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35
VREF
D0 - D35
SA0 SA1 SA2
RRAS -> RAS : DDR2 SDRAMs D0-D35
VSS
D0 - D35
RCAS -> CAS : DDR2 SDRAMs D0-D35
RWE -> WE : DDR2 SDRAMs D0-D35
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35
RCKE0 -> CKE : DDR2 SDRAMs D0-D17
P
RCKE1 -> CKE : DDR2 SDRAMs D18-D35
L
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35
CK0
L
RODT1 -> ODT1 : DDR2 SDRAMs D18-D35
PCK7 -> CK : Register
OE
RESET
PCK7 -> CK : Register
* S0 connects to DCS and S0 connects to CSR on a Register, S1 connects to DCS and S0 connects to CSR on another Register.
** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Absolute Maximum DC Ratings
Symbol
Rating
Units
Notes
Voltage on VDD pin relative to VSS
- 1.0 V ~ 2.3 V
V
1
VDDQ
Voltage on VDDQ pin relative to VSS
- 0.5 V ~ 2.3 V
V
1
VDDL
Voltage on VDDL pin relative to VSS
- 0.5 V ~ 2.3 V
V
1
Voltage on any pin relative to VSS
- 0.5 V ~ 2.3 V
V
1
-55 to +100
°C
1, 2
VDD
VIN, VOUT
TSTG
Parameter
Storage Temperature
Note :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2
standard.
AC & DC Operating Conditions
Recommended DC Operating Conditions (SSTL - 1.8)
Symbol
Parameter
Rating
Min.
Typ.
Max.
1.7
1.8
1.9
Units
Notes
VDD
Supply Voltage
VDDL
Supply Voltage for DLL
1.7
1.8
1.9
V
4
VDDQ
Supply Voltage for Output
1.7
1.8
1.9
V
4
VREF
Input Reference Voltage
0.49*VDDQ
0.50*VDDQ
0.51*VDDQ
mV
1,2
Termination Voltage
VREF-0.04
VREF
VREF+0.04
V
3
VTT
V
Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal
to VDD.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5
x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).
3. VTT of transmitting device must track VREF of receiving device.
4. AC parameters are measured with VDD, VDDQ and VDDL tied together.
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Operating Temperature Condition
Symbol
Parameter
Rating
Units
Notes
TOPER
Operating Temperature
0 to 95
°C
1, 2, 3
Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2
standard.
2. At 0 - 85 °C, operation temperature range are the temperature which all DRAM specification will be supported.
3. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self
refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
Input DC Logic Level
Symbol
Parameter
Min.
Max.
Units
VIH(DC)
DC input logic high
VREF + 0.125
VDDQ + 0.3
V
VIL(DC)
DC input logic low
- 0.3
VREF - 0.125
V
Max.
Units
Notes
Input AC Logic Level
Symbol
Parameter
Min.
VIH(AC)
AC input logic high
VREF + 0.250
-
V
VIL(AC)
AC input logic low
-
VREF - 0.250
V
Notes
AC Input Test Conditions
Symbol
VREF
VSWING(MAX)
SLEW
Condition
Value
Units
Notes
0.5 * VDDQ
V
1
Input signal maximum peak to peak swing
1.0
V
1
Input signal minimum slew rate
1.0
V/ns
2, 3
Input reference voltage
Notes:
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC)
max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative
transitions.
VDDQ
VIH(AC) min
VIH(DC) min
VSWING(MAX)
VREF
VIL(DC) max
VIL(AC) max
delta TF
Falling Slew =
delta TR
VREF - VIL(AC) max
delta TF
Rising Slew =
VSS
VIH(AC) min - VREF
delta TR
< AC Input Test Signal Waveform >
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
IDD Specification Parameters Definition
(IDD values are for full operating range of Voltage and Temperature)
Symbol
Proposed Conditions
Units
IDD0
Operating one bank active-precharge current;
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD1
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =
tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern
is same as IDD4W
mA
IDD2P
Precharge power-down current;
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
mA
IDD2Q
Precharge quiet standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
mA
IDD2N
Precharge standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
mA
IDD3P
Active power-down current;
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
IDD3N
Active standby current;
All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD4W
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP
= tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD4R
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
mA
IDD5B
Burst auto refresh current;
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands;
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD6
Self refresh current;
CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
IDD7
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC =
tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following
page for detailed timing conditions
Fast PDN Exit MRS(12) = 0mA
mA
Slow PDN Exit MRS(12) = 1mA
mA
Normal
mA
Low Power
mA
Notes
mA
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Operating Current Table(1-1) (TA=0oC, VDD= 1.9V)
M393T6553BG(Z)3 / M393T6553BG(Z)0 : 512MB(64Mx8 *9) Module
Symbol
D5
(DDR2-533@CL=4)
CC
(DDR2-400@CL=3)
Unit
IDD0
1,420
1,265
mA
IDD1
1,540
1,330
mA
IDD2P
562
522
mA
IDD2Q
715
665
mA
IDD2N
730
670
mA
IDD3P-F
750
720
mA
IDD3P-S
375
365
mA
IDD3N
1,180
1,065
mA
IDD4W
2,340
1,725
mA
IDD4R
2,020
1,655
mA
IDD5B
2,275
2,125
mA
50
50
mA
3,155
3,020
mA
IDD6*
Normal
IDD7
Notes
* IDD6 = DRAM current + standby current of PLL and Register.
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M393T2953BG(Z)3 / M393T2953BG(Z)0 : 1GB(64Mx8 *18) Module
Symbol
D5
(DDR2-533@CL=4)
CC
(DDR2-400@CL=3)
Unit
IDD0
1,790
1,665
mA
IDD1
1,920
1,770
mA
IDD2P
784
724
mA
IDD2Q
1,110
1,040
mA
mA
IDD2N
1,090
1,060
IDD3P-F
1,190
1,130
mA
IDD3P-S
600
570
mA
IDD3N
1,480
1,415
mA
IDD4W
2,740
2,135
mA
IDD4R
2,420
2,055
mA
IDD5B
2,665
2,485
mA
99
99
mA
3,785
3,785
mA
IDD6*
Normal
IDD7
Notes
* IDD6 = DRAM current + standby current of PLL and Register.
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Operating Current Table(1-2) (TA=0oC, VDD= 1.9V)
M393T2950BG(Z)3 / M393T2950BG(Z)0 : 1GB(128Mx4 *18) Module
Symbol
D5
(DDR2-533@CL=4)
CC
(DDR2-400@CL=3)
Unit
IDD0
2,420
2,250
mA
IDD1
2,640
2,400
mA
IDD2P
784
724
mA
IDD2Q
1,110
1,040
mA
IDD2N
1,090
1,060
mA
IDD3P-F
1,190
1,130
mA
IDD3P-S
600
570
mA
mA
IDD3N
1,840
1,730
IDD4W
3,820
2,900
mA
IDD4R
3,590
3,000
mA
4,150
3,880
mA
99
99
mA
5,900
5,570
mA
IDD5B
IDD6*
Normal
IDD7
Notes
* IDD6 = DRAM current + standby current of PLL and Register.
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M393T5750BS(Y)3 / M393T5750BS(Y)0 : 2GB(128Mx4 *36) Module
Symbol
D5
(DDR2-533@CL=4)
CC
(DDR2-400@CL=3)
Unit
IDD0
3,250
3,010
mA
IDD1
3,520
3,220
mA
mA
IDD2P
1,238
1,138
IDD2Q
1,880
1,770
mA
IDD2N
1,850
1,810
mA
IDD3P-F
2,050
1,950
mA
IDD3P-S
1,030
980
mA
mA
IDD3N
2,620
2,500
IDD4W
4,710
3,690
mA
IDD4R
4,330
3,700
mA
4,990
4,660
mA
198
198
mA
7,140
6,600
mA
IDD5B
IDD6*
Normal
IDD7
Notes
* IDD6 = DRAM current + standby current of PLL and Register.
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Input/Output Capacitance(VDD=1.8V, VDDQ=1.8V, TA=25oC)
Parameter
Part-Number
Min
Symbol
Max
M393T6553BG(Z)3
M393T6553BG(Z)0
Min
Max
Min
Max
M393T2953BG(Z)3
M393T2950BG(Z)3
M393T2953BG(Z)0
M393T2950BG(Z)0
Min
Max
M393T5750BS(Y)3
M393T5750BS(Y)0
Input capacitance, CK and CK
CCK
-
11
-
11
-
11
-
11
Input capacitance, CKE and CS
CI1
-
12
-
12
-
12
-
12
Input capacitance, Addr,RAS,CAS,WE
CI2
-
12
-
12
-
12
-
12
Input/output capacitance, DQ, DM, DQS,
CIO
DQS
-
10
-
10
-
10
-
10
Units
pF
* DM is internally loaded to match DQ and DQS identically.
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Electrical Characteristics & AC Timing for DDR2-533/400 SDRAM
(0 °C < TCASE < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
Refresh Parameters by Device Density
Parameter
Refresh to active/Refresh command time
Average periodic refresh interval
Symbol
256Mb
512Mb
1Gb
2Gb
4Gb
Units
tRFC
tREFI
75
105
127.5
195
tbd
ns
0 °C ≤ TCASE ≤ 85°C
7.8
7.8
7.8
7.8
7.8
µs
85 °C < TCASE ≤ 95°C
3.9
3.9
3.9
3.9
3.9
µs
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
DDR2-533(D5)
Bin (CL - tRCD - tRP)
DDR2-400(CC)
4-4-4
Parameter
3-3-3
Units
min
max
min
max
tCK, CL=3
5
8
5
8
ns
tCK, CL=4
3.75
8
5
8
ns
-
-
-
-
ns
tCK, CL=5
tRCD
15
15
ns
tRP
15
15
ns
tRC
55
tRAS
40
55
70000
ns
70000
40
ns
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
Parameter
DDR2-533
Symbol
DDR2-400
Units
min
max
min
max
DQ output access time from CK/CK
tAC
-500
+500
-600
+600
DQS output access time from CK/CK
tDQSCK
-450
+450
-500
+500
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
CK half period
tHP
min(tCL, tCH)
x
min(tCL, tCH)
x
ps
Clock cycle time, CL=x
tCK
3750
8000
5000
8000
ps
DQ and DM input hold time
tDH
225
x
275
x
ps
DQ and DM input setup time
tDS
100
x
150
x
ps
Control & Address input pulse width for each input
tIPW
0.6
x
0.6
x
tCK
DQ and DM input pulse width for each input
tDIPW
0.35
x
0.35
x
tCK
Data-out high-impedance time from CK/CK
tHZ
DQS low-impedance time from CK/CK
tLZ(DQS)
DQ low-impedance time from CK/CK
Notes
ps
x
tAC max
x
tAC max
ps
tAC min
tAC max
tAC min
tAC max
ps
tLZ(DQ)
2* tACmin
tAC max
2* tACmin
tAC max
ps
DQS-DQ skew for DQS and associated DQ signals
tDQSQ
x
300
x
350
ps
DQ hold skew factor
tQHS
ps
DQ/DQS output hold time from DQS
tQH
Write command to first DQS latching transition
x
400
x
450
tHP - tQHS
x
tHP - tQHS
x
ps
tDQSS
WL-0.25
WL+0.25
WL-0.25
WL+0.25
tCK
DQS input high pulse width
tDQSH
0.35
x
0.35
x
tCK
DQS input low pulse width
tDQSL
0.35
x
0.35
x
tCK
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
Parameter
DDR2 SDRAM
DDR2-533
Symbol
DDR2-400
Units
min
max
min
max
DQS falling edge to CK setup time
tDSS
0.2
x
0.2
x
tCK
DQS falling edge hold time from CK
tDSH
0.2
x
0.2
x
tCK
Mode register set command cycle time
tMRD
2
x
2
x
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
Write preamble
tWPRE
0.35
x
0.35
x
tCK
Address and control input hold time
tIH
375
x
475
x
ps
Address and control input setup time
tIS
250
x
350
x
ps
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Active to active command period for 1KB page size products
tRRD
7.5
x
7.5
x
ns
Active to active command period for 2KB page size products
tRRD
10
x
10
x
ns
Four Activate Window for 1KB page size products
tFAW
37.5
37.5
ns
Four Activate Window for 2KB page size products
tFAW
50
50
ns
CAS to CAS command delay
tCCD
2
Write recovery time
tWR
15
x
15
x
ns
Auto precharge write recovery + precharge time
tDAL
tWR+tRP
x
tWR+tRP
x
tCK
Internal write to read command delay
tWTR
7.5
x
10
x
ns
Internal read to precharge command delay
tRTP
7.5
7.5
Exit self refresh to a non-read command
tXSNR
tRFC + 10
tRFC + 10
ns
Exit self refresh to a read command
tXSRD
200
200
tCK
Exit precharge power down to any non-read command
tXP
2
x
2
x
tCK
Exit active power down to read command
tXARD
2
x
2
x
tCK
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
CKE minimum pulse width
(high and low pulse width)
2
6 - AL
6 - AL
tCKE
3
3
ODT turn-on delay
tAOND
2
ODT turn-on
tAON
ODT turn-on(Power-Down mode)
tAONPD
ODT turn-off delay
tAOFD
ODT turn-off
tAOF
tCK
ns
tCK
tCK
2
2
2
tCK
tAC(min)
tAC(max)+1
tAC(min)
tAC(max)+1
ns
tAC(min)+2
2tCK+tAC(m
ax)+1
tAC(min)+2
2tCK+tAC
(max)+1
ns
2.5
2.5
2.5
2.5
tCK
tAC(min)
tAC(max)+ 0.6
tAC(min)
tAC(max)+ 0.6
ns
tAC(min)+2
2.5tCK+
tAC(max)+1
tAC(min)+2
2.5tCK+
tAC(max)+1
ns
ODT turn-off (Power-Down mode)
tAOFPD
ODT to power down entry latency
tANPD
3
3
tCK
ODT power down exit latency
tAXPD
8
8
tCK
OCD drive mode output delay
tOIT
Minimum time clocks remains ON after CKE asynchronously drops LOW
tDelay
0
tIS+tCK +tIH
12
Notes
0
12
tIS+tCK +tIH
ns
ns
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Physical Dimensions: 64Mbx8 based 64Mx72 Module(1 Rank)
M393T6553BG(Z)3 / M393T6553BG(Z)0
Units : Millimeters
2.70
Register
133.35
30.00
PLL
1.0 max
1.27 ± 0.10
A
B
63.00
4.00
4.00
3.00
2.50±0.20
5.00
55.00
0.80±0.05
3.80
2.50
1.50±0.10
Detail A
0.20
1.00
4.00
Detail B
The used device is 64M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T51083QB
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Physical Dimensions: 64Mbx8/128Mbx4 based 128Mx72 Module(2/1 Ranks)
M393T2953BG(Z)3 / M393T2953BG(Z)0
M393T2950BG(Z)3 / M393T2950BG(Z)0
Units : Millimeters
133.35
Register
4.00
30.00
PLL
1.0 max
1.7 max
1.27 ± 0.10
A
B
63.00
Register
55.00
4.00
4.00
3.00
2.50±0.20
5.00
0.80±0.05
3.80
2.50
1.50±0.10
Detail A
0.20
1.00
4.00
Detail B
The used device is 64M x8 / 128M x4 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T51083QB / K4T51043QB
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Physical Dimensions: 128Mbx4 based 256Mx72 Module(2 Ranks)
M393T5750BS(Y)3 / M393T5750BS(Y)0
Units : Millimeters
133.35
PLL
Register
Register
4.00
30.00
1.0 max
1.7 max
1.27 ± 0.10
A
B
63.00
5.00
4.00
4.00
Register
3.00
2.50±0.20
Register
55.00
0.80±0.05
3.80
2.50
1.50±0.10
Detail A
0.20
1.00
4.00
Detail B
The used device is 128M x4 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T51043QB
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
240 Pin DDR2 Registered DIMM Clock Topology
0ns (nominal)
PLL
DDR2 SDRAM
120 ohms
OUT1
CK0
120 ohms
IN
DDR2 SDRAM
CK0
Reg.A
120 ohms
C
OUTN
C
Feedback In
Feedback Out
120 ohms
Reg.B
Note:
1.
2.
3.
4.
The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to 0ns (nominal).
Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground.
Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner.
Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.
Rev. 1.3 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Revision History
Revision 1.0 (Jan. 2004)
- Initial Release
Revision 1.1 (Jun. 2004)
- Added lead-free part number in the ordering information
- Changed IDD2P
Revision 1.2 (Sep. 2004)
- Changed IDD6
Revision 1.3 (Aug. 2004)
- Added Dummy Pad PCB Product part number in the ordering information
Rev. 1.3 Aug. 2005